From b314b79c9d834cad5f7db9c5d7cf643b20c549ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 09:16:15 +0000 Subject: [PATCH] added missing source files from original code --- BaS_GNU/sources/div.s | 1326 +++++++++++++++++++++ BaS_GNU/sources/ewf.s | 1565 +++++++++++++++++++++++++ BaS_GNU/sources/exceptions.s | 799 +++++++++++++ BaS_GNU/sources/ii_add.h | 581 +++++++++ BaS_GNU/sources/ii_and.h | 441 +++++++ BaS_GNU/sources/ii_dbcc.h | 117 ++ BaS_GNU/sources/ii_ewf.h | 181 +++ BaS_GNU/sources/ii_exg.h | 120 ++ BaS_GNU/sources/ii_func.h | 945 +++++++++++++++ BaS_GNU/sources/ii_jmp.h | 59 + BaS_GNU/sources/ii_lea.h | 105 ++ BaS_GNU/sources/ii_macro.h | 144 +++ BaS_GNU/sources/ii_move.h | 1271 ++++++++++++++++++++ BaS_GNU/sources/ii_movem.h | 374 ++++++ BaS_GNU/sources/ii_movep.h | 179 +++ BaS_GNU/sources/ii_op.h | 661 +++++++++++ BaS_GNU/sources/ii_opc.h | 263 +++++ BaS_GNU/sources/ii_or.h | 442 +++++++ BaS_GNU/sources/ii_pea.h | 74 ++ BaS_GNU/sources/ii_shd.h | 247 ++++ BaS_GNU/sources/ii_shift.h | 687 +++++++++++ BaS_GNU/sources/ii_sub.h | 584 +++++++++ BaS_GNU/sources/illegal_instruction.s | 328 ++++++ BaS_GNU/sources/last.c | 11 + BaS_GNU/sources/last.s | 10 + BaS_GNU/sources/macro.h | 10 + BaS_GNU/sources/mmu.s | 196 ++++ BaS_GNU/sources/movem.h | 256 ++++ BaS_GNU/sources/sd_card.s | 406 +++++++ BaS_GNU/sources/sd_ide.c | 543 +++++++++ BaS_GNU/sources/sd_ide.s | 458 ++++++++ BaS_GNU/sources/startcf.S | 82 ++ BaS_GNU/sources/startcf.h | 47 + BaS_GNU/sources/supervisor.s | 585 +++++++++ 34 files changed, 14097 insertions(+) create mode 100644 BaS_GNU/sources/div.s create mode 100644 BaS_GNU/sources/ewf.s create mode 100644 BaS_GNU/sources/exceptions.s create mode 100644 BaS_GNU/sources/ii_add.h create mode 100644 BaS_GNU/sources/ii_and.h create mode 100644 BaS_GNU/sources/ii_dbcc.h create mode 100644 BaS_GNU/sources/ii_ewf.h create mode 100644 BaS_GNU/sources/ii_exg.h create mode 100644 BaS_GNU/sources/ii_func.h create mode 100644 BaS_GNU/sources/ii_jmp.h create mode 100644 BaS_GNU/sources/ii_lea.h create mode 100644 BaS_GNU/sources/ii_macro.h create mode 100644 BaS_GNU/sources/ii_move.h create mode 100644 BaS_GNU/sources/ii_movem.h create mode 100644 BaS_GNU/sources/ii_movep.h create mode 100644 BaS_GNU/sources/ii_op.h create mode 100644 BaS_GNU/sources/ii_opc.h create mode 100644 BaS_GNU/sources/ii_or.h create mode 100644 BaS_GNU/sources/ii_pea.h create mode 100644 BaS_GNU/sources/ii_shd.h create mode 100644 BaS_GNU/sources/ii_shift.h create mode 100644 BaS_GNU/sources/ii_sub.h create mode 100644 BaS_GNU/sources/illegal_instruction.s create mode 100644 BaS_GNU/sources/last.c create mode 100644 BaS_GNU/sources/last.s create mode 100644 BaS_GNU/sources/macro.h create mode 100644 BaS_GNU/sources/mmu.s create mode 100644 BaS_GNU/sources/movem.h create mode 100644 BaS_GNU/sources/sd_card.s create mode 100644 BaS_GNU/sources/sd_ide.c create mode 100644 BaS_GNU/sources/sd_ide.s create mode 100644 BaS_GNU/sources/startcf.S create mode 100644 BaS_GNU/sources/startcf.h create mode 100644 BaS_GNU/sources/supervisor.s diff --git a/BaS_GNU/sources/div.s b/BaS_GNU/sources/div.s new file mode 100644 index 0000000..f5f151c --- /dev/null +++ b/BaS_GNU/sources/div.s @@ -0,0 +1,1326 @@ + +/********************************************************************/ +// sd card +/********************************************************************/ +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 + +sd_test: + lea 0x40000,a5 // basis addresse + move.l #0x1fffffff,d0 // normal dspi + move.l d0,MCF_PAD_PAR_DSPI + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) // 8 bit 4MHz + move.l #0x38551120,d0 + move.l d0,dspi_dtar0(a0) // + move.l #0x08200000,d4 // tx vorbesetzen + mov3q.l #-1,dspi_dsr(a0) + + move.b #0xc0,(a0) // 8 bit 4MHz + bsr warte_1ms + move.b #0x80,(a0) // 8 bit 4MHz +// sd idle + moveq.l #100,d6 // 100 versuche +sd_idle: + bsr sd_16clk + move.b #0x40,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x01,d5 + beq wait_of_aktiv + subq.l #1,d6 + beq sd_not + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + move.b #0x77,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x05,d5 + beq wait_of_aktiv + + +wait_of_aktiv2: + bsr sd_16clk + move.b #0x69,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x02,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq wait_of_aktiv2 + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + move.b #0x50,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #02,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + move.b #0x51,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_rb + + move.l a5,a4 // adresse setzen + bsr sd_rcv_block + +// write block +sd_wb: + bsr sd_16clk + move.b #0x58,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_wb + + bsr sd_send_block + +// read block 2 +sd_rb2: + bsr sd_16clk + move.b #0x51,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_rb + + bsr sd_rcv_block + clr.l d0 + halt + halt + rts +// status holen ------------------------------- +sd_not: + moveq.l #-1,d0 + halt + halt + rts + +// status holen ------------------------------- +sd_get_status: + move.b #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_get_status + rts +// byt senden und holen --------------------- +sd_com: + move.l d4,dspi_dtfr(a0) +wait_auf_complett: + btst.b #7,dspi_dsr(a0) + beq wait_auf_complett + move.l dspi_drfr(a0),d5 + mov3q.l #-1,dspi_dsr(a0) // clr status register + rts + +// daten holen ---------------------------- +sd_rcv_block: + move.l #512,d3 // 512 byts + 2 ccr byts + move.b #0xff,d4 +sd_rcv_rb_w: + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rcv_rb_w // nein-> +sd_rcv_rd_rb: + bsr sd_com + move.b d5,(a4)+ + subq.l #1,d3 + bne sd_rcv_rd_rb +// crc holen + bsr sd_com // crc 1.byt + move.b d5,d1 + bsr sd_com // crc 2.byt + move.b d5,d2 + rts + +// daten schreiben ----------------------- +sd_send_block: + move.l #512,d3 + move.b #0xfe,d4 // start token + bsr sd_com // senden +sd_send_wr_wb: + move.b #0xc7,d4 // data + bsr sd_com // senden + subq.l #1,d3 + bne sd_send_wr_wb +// send crc + move.b d1,d4 + bsr sd_com // crc 1.byt + move.b d2,d4 + bsr sd_com // crc 2.byt +sd_send_wr_ww: + bsr sd_get_status + and.l #0x1f,d5 + cmp.b #0x05,d5 + bne sd_send_wr_ww +sd_sendwait_wr_f: + bsr sd_com + cmp.b #0xff,d5 + bne sd_sendwait_wr_f + rts +// clock einfügen ------------------------------------- +sd_16clk: + move.b #0xc0,(a0) // 8 bit 4MHz + nop + move.b #0x80,(a0) // 8 bit 4MHz + rts +// cdm 58 +read_ocr: + bsr sd_16clk + move.b #0x7a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + move.b #0xaa,d4 + bsr sd_com + move.b #0x87,d4 + bsr sd_com + + bsr sd_get_status + + halt + + move.l #'Ver1',d6 + cmp.b #5,d5 + beq sd_v1 + cmp.b #1,d5 + bne read_csd + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com +/******************************************/ +#include "MCF5475.h" +#include "startcf.h" + +extern unsigned long far __SP_AFTER_RESET[]; +extern unsigned long far __Bas_base[]; + + /* imported routines */ +//extern int warten_20ms(); +//extern int warten_200us(); +//extern int warten_10us(); + +/********************************************************************/ +void asm sd_test(void) +{ + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} + + +/**************************************************/ +void asm ide_test(void) +{ + lea MCF_PAD_PAR_DSPI,a0 + move.w #0x1fff,(a0) + lea MCF_DSPI_DCTAR0,a0 + move.l #0x38a644e4,(a0) + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) + clr.l MCF_DSPI_DTCR + bsr warten_20ms + lea MCF_DSPI_DTFR,a0 + lea MCF_DSPI_DRFR,a1 + + moveq #10,d0 +sd_reset: + move.l #0x000100ff,(a0) + bsr warten_20ms + and.l (a1),d0 + subq.l #1,d0 + bne sd_reset + + moveq #10,d1 +sd_loop1: + bsr warten_20ms + moveq #-1,d0 +// cmd 0 set to idle + move.l #0x00200040,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200095,(a0) + bsr warten_20ms + and.l (a1),d0 + cmp.w #0x0001,d0 + beq sd_loop2 + subq.l #1,d1 + bne sd_loop1 + moveq #10,d1 + bra sd_test +sd_loop2: + moveq #-1,d0 +// cmd 41 + move.l #0x00200069,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200001,(a0) + bsr warten_20ms + and.l (a1),d0 + tst.w d0 + bne sd_loop2 + + nop + nop +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst.b #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} +/********************************************************************/ +//.include "startcf.h" + +//.extern ___MBAR +//#define MCF_SLT0_SCNT ___MBAR+0x908 + +//.global ide_test + +.text +/********************************************************************/ +// sd card +/********************************************************************/ +sd_test: + lea 0x40000,a5 // basis addresse + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + move.l a5,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + move.l #513,d7 + moveq.l #0xbb,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0xbb,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + +halt +halt + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) // nCS=0 +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + bclr.b #0,(a1) // default 0 bit senden + btst d2,d4 // ist 0? + beq sd_com2 // ja-> + bset.b #0,(a1) // sonst auf 1 +sd_com2: + bsr sd_clk // clocken + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) // nCS=1 + bset.b #0,(a1) // daten = 0 + bsr warten_200us + rts +// clocken +sd_clk: + tst.b 0xfffff700 // wait + tst.b 0xfffff700 + bset.b #2,(a1) // clock high + tst.b 0xfffff700 // wait + tst.b 0xfffff700 // wait + move.b (a2),d3 // bit holen + bclr.b #2,(a1) // clock low + rts + +sd_16clk: + move.l #160,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +/********************************************************************/ +// video pll +/********************************************************************/ + lea 0xf0000800,a1 + + lea 0xf0000600,a0 + move.l #128,d0 +clr_pll: + bsr wait_pll + clr.w (a0) + addq.l #4,a0 + subq.l #1,d0 + bne clr_pll + + lea 0xf0000600,a0 + bsr wait_pll + move.w #27,0x48(a0) // loopfilter r + bsr wait_pll + move.w #1,0x08(a0) // charge pump I + bsr wait_pll + move.w #12,0x0(a0) // N counter high = 12 + bsr wait_pll + move.w #12,0x40(a0) // N counter low = 12 + bsr wait_pll + move.w #1,0x114(a0) // ck1 bypass + bsr wait_pll + move.w #1,0x118(a0) // ck2 bypass + bsr wait_pll + move.w #1,0x11c(a0) // ck3 bypass + bsr wait_pll + move.w #1,0x10(a0) // ck0 high = 1 + bsr wait_pll + move.w #1,0x50(a0) // ck0 low = 1 + + bsr wait_pll + move.w #1,0x144(a0) // M odd division + bsr wait_pll + move.w #1,0x44(a0) // M low = 1 + + bsr wait_pll + move.w #99,0x04(a0) // M high = 100 + + bsr wait_pll + clr.b (a1) // set + +set_pll: + bsr read_pll + halt + move.w d0,(a0) + bsr wait_pll + clr.b (a1) + bra set_pll + +read_pll: + lea 0xf0000600,a3 + lea 0x10000,a2 + move.l #128,d3 +read1_pll: + bsr wait_pll + move.w (a3),d1 + bsr wait_pll + move.w (a3),(a2) + addq.l #4,a3 + addq.l #4,a2 + subq.l #1,d3 + bne read1_pll + rts +wait_pll: + tst.w (a1) + bmi wait_pll + rts + +/********************************************************************/ +void ide_test(void) +/********************************************************************/ +{ + asm + { + halt + lea 0xfff00000,a0 + lea 0x80000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rxl +// read sector normal + move.b #1,seccnt(a0) // 1 sector 0x200 + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rxl +// write pattern 0x400 + move.l a1,a4 //a4=400 + move.l #256,d0 + clr.l d1 +ide_test_loop3: + move.w d1,(a1)+ + addq.l #1,d1 + subq.l #1,d0 + bne ide_test_loop3 + move.l a4,a1 +// write testpattern sector 0x400 + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait + bsr ds_txl + bsr wait_int + move.l a1,a2 //a2=600 + move.l #256,d4 +loop_rw: +// read testpattern sector 0x600 + move.l a2,a1 +// halt + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rxl +// verändere testpattern + move.l a2,a1 +// halt + move.l #256,d0 + move.l #0x100,d1 +verae_loop: + move.w (a1),d2 + add.l d1,d2 + move.w d2,(a1)+ + subq.l #1,d0 + bne verae_loop +// write testpattern sector 0x600 + move.l a2,a1 +// halt + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait + bsr ds_txl + bsr wait_int + subq.l #1,d4 +// bra verae_loop + bne loop_rw +// sector vergleichen +// halt + move.l #128,d0 + moveq.l #-1,d1 +verg_loop: + move.l (a2)+,d2 + cmp.l (a4)+,d2 + bne error + subq.l #1,d0 + bne verg_loop + clr.l d1 +error: + halt + rts +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_txl + + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben long +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts + } +} +/********************************************************************/ diff --git a/BaS_GNU/sources/ewf.s b/BaS_GNU/sources/ewf.s new file mode 100644 index 0000000..7f5a644 --- /dev/null +++ b/BaS_GNU/sources/ewf.s @@ -0,0 +1,1565 @@ +/*************************************************************************************************/ +// extension word format: a0 zeigt auf code, in a1 ist ay, d0/d1 wird zerstört +//------------------------------------------------------------------------------ + +.include "ii_macro.h" + +.global ewf +//----------------------------------------------------------- +.text +ewferr: + nop + halt + nop +//----------------------------------------------------------- +ewf: + mvz.b (a0)+,d1 // 1. byt ewf + mvs.w ewf_table-*-2(pc,d1*2),d1 + jmp ewf_table-*-2(pc,d1) +ewf_table: + .short ewf_00-ewf_table,ewf_01-ewf_table,ewf_02-ewf_table,ewf_03-ewf_table + .short ewf_04-ewf_table,ewf_05-ewf_table,ewf_06-ewf_table,ewf_07-ewf_table + .short ewferr-ewf_table,ewf_09-ewf_table,ewferr-ewf_table,ewf_0b-ewf_table + .short ewferr-ewf_table,ewf_0d-ewf_table,ewferr-ewf_table,ewf_0f-ewf_table + .short ewf_10-ewf_table,ewf_11-ewf_table,ewf_12-ewf_table,ewf_13-ewf_table + .short ewf_14-ewf_table,ewf_15-ewf_table,ewf_16-ewf_table,ewf_17-ewf_table + .short ewferr-ewf_table,ewf_19-ewf_table,ewferr-ewf_table,ewf_1b-ewf_table + .short ewferr-ewf_table,ewf_1d-ewf_table,ewferr-ewf_table,ewf_1f-ewf_table + .short ewf_20-ewf_table,ewf_21-ewf_table,ewf_22-ewf_table,ewf_23-ewf_table + .short ewf_24-ewf_table,ewf_25-ewf_table,ewf_26-ewf_table,ewf_27-ewf_table + .short ewferr-ewf_table,ewf_29-ewf_table,ewferr-ewf_table,ewf_2b-ewf_table + .short ewferr-ewf_table,ewf_2d-ewf_table,ewferr-ewf_table,ewf_2f-ewf_table + .short ewf_30-ewf_table,ewf_31-ewf_table,ewf_32-ewf_table,ewf_33-ewf_table + .short ewf_34-ewf_table,ewf_35-ewf_table,ewf_36-ewf_table,ewf_37-ewf_table + .short ewferr-ewf_table,ewf_39-ewf_table,ewferr-ewf_table,ewf_3b-ewf_table + .short ewferr-ewf_table,ewf_3d-ewf_table,ewferr-ewf_table,ewf_3f-ewf_table + .short ewf_40-ewf_table,ewf_41-ewf_table,ewf_42-ewf_table,ewf_43-ewf_table + .short ewf_44-ewf_table,ewf_45-ewf_table,ewf_46-ewf_table,ewf_47-ewf_table + .short ewferr-ewf_table,ewf_49-ewf_table,ewferr-ewf_table,ewf_4b-ewf_table + .short ewferr-ewf_table,ewf_4d-ewf_table,ewferr-ewf_table,ewf_4f-ewf_table + .short ewf_50-ewf_table,ewf_51-ewf_table,ewf_52-ewf_table,ewf_53-ewf_table + .short ewf_54-ewf_table,ewf_55-ewf_table,ewf_56-ewf_table,ewf_57-ewf_table + .short ewferr-ewf_table,ewf_59-ewf_table,ewferr-ewf_table,ewf_5b-ewf_table + .short ewferr-ewf_table,ewf_5d-ewf_table,ewferr-ewf_table,ewf_5f-ewf_table + .short ewf_60-ewf_table,ewf_61-ewf_table,ewf_62-ewf_table,ewf_63-ewf_table + .short ewf_64-ewf_table,ewf_65-ewf_table,ewf_66-ewf_table,ewf_67-ewf_table + .short ewferr-ewf_table,ewf_69-ewf_table,ewferr-ewf_table,ewf_6b-ewf_table + .short ewferr-ewf_table,ewf_6d-ewf_table,ewferr-ewf_table,ewf_6f-ewf_table + .short ewf_70-ewf_table,ewf_71-ewf_table,ewf_72-ewf_table,ewf_73-ewf_table + .short ewf_74-ewf_table,ewf_75-ewf_table,ewf_76-ewf_table,ewf_77-ewf_table + .short ewferr-ewf_table,ewf_79-ewf_table,ewferr-ewf_table,ewf_7b-ewf_table + .short ewferr-ewf_table,ewf_7d-ewf_table,ewferr-ewf_table,ewf_7f-ewf_table + .short ewf_80-ewf_table,ewf_81-ewf_table,ewf_82-ewf_table,ewf_83-ewf_table + .short ewf_84-ewf_table,ewf_85-ewf_table,ewf_86-ewf_table,ewf_87-ewf_table + .short ewferr-ewf_table,ewf_89-ewf_table,ewferr-ewf_table,ewf_8b-ewf_table + .short ewferr-ewf_table,ewf_8d-ewf_table,ewferr-ewf_table,ewf_8f-ewf_table + .short ewf_90-ewf_table,ewf_91-ewf_table,ewf_92-ewf_table,ewf_93-ewf_table + .short ewf_94-ewf_table,ewf_95-ewf_table,ewf_96-ewf_table,ewf_97-ewf_table + .short ewferr-ewf_table,ewf_99-ewf_table,ewferr-ewf_table,ewf_9b-ewf_table + .short ewferr-ewf_table,ewf_9d-ewf_table,ewferr-ewf_table,ewf_9f-ewf_table + .short ewf_a0-ewf_table,ewf_a1-ewf_table,ewf_a2-ewf_table,ewf_a3-ewf_table + .short ewf_a4-ewf_table,ewf_a5-ewf_table,ewf_a6-ewf_table,ewf_a7-ewf_table + .short ewferr-ewf_table,ewf_a9-ewf_table,ewferr-ewf_table,ewf_ab-ewf_table + .short ewferr-ewf_table,ewf_ad-ewf_table,ewferr-ewf_table,ewf_af-ewf_table + .short ewf_b0-ewf_table,ewf_b1-ewf_table,ewf_b2-ewf_table,ewf_b3-ewf_table + .short ewf_b4-ewf_table,ewf_b5-ewf_table,ewf_b6-ewf_table,ewf_b7-ewf_table + .short ewferr-ewf_table,ewf_b9-ewf_table,ewferr-ewf_table,ewf_bb-ewf_table + .short ewferr-ewf_table,ewf_bd-ewf_table,ewferr-ewf_table,ewf_bf-ewf_table + .short ewf_c0-ewf_table,ewf_c1-ewf_table,ewf_c2-ewf_table,ewf_c3-ewf_table + .short ewf_c4-ewf_table,ewf_c5-ewf_table,ewf_c6-ewf_table,ewf_c7-ewf_table + .short ewferr-ewf_table,ewf_c9-ewf_table,ewferr-ewf_table,ewf_cb-ewf_table + .short ewferr-ewf_table,ewf_cd-ewf_table,ewferr-ewf_table,ewf_cf-ewf_table + .short ewf_d0-ewf_table,ewf_d1-ewf_table,ewf_d2-ewf_table,ewf_d3-ewf_table + .short ewf_d4-ewf_table,ewf_d5-ewf_table,ewf_d6-ewf_table,ewf_d7-ewf_table + .short ewferr-ewf_table,ewf_d9-ewf_table,ewferr-ewf_table,ewf_db-ewf_table + .short ewferr-ewf_table,ewf_dd-ewf_table,ewferr-ewf_table,ewf_df-ewf_table + .short ewf_e0-ewf_table,ewf_e1-ewf_table,ewf_e2-ewf_table,ewf_e3-ewf_table + .short ewf_e4-ewf_table,ewf_e5-ewf_table,ewf_e6-ewf_table,ewf_e7-ewf_table + .short ewferr-ewf_table,ewf_e9-ewf_table,ewferr-ewf_table,ewf_eb-ewf_table + .short ewferr-ewf_table,ewf_ed-ewf_table,ewferr-ewf_table,ewf_ef-ewf_table + .short ewf_f0-ewf_table,ewf_f1-ewf_table,ewf_f2-ewf_table,ewf_f3-ewf_table + .short ewf_f4-ewf_table,ewf_f5-ewf_table,ewf_f6-ewf_table,ewf_f7-ewf_table + .short ewferr-ewf_table,ewf_f9-ewf_table,ewferr-ewf_table,ewf_fb-ewf_table + .short ewferr-ewf_table,ewf_fd-ewf_table,ewferr-ewf_table,ewf_ff-ewf_table +//d0.w * 1 +ewf_00: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_01: + mvs.w d0_off+6(a7),d0 + bra ewf_full +//d0.w * 2 +ewf_02: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_03: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d0.w * 4 +ewf_04: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_05: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d0.w * 8 +ewf_06: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_07: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 1 +ewf_09: + move.l d0_off+4(a7),d0 + bra ewf_full +//d0.l * 2 +ewf_0b: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 4 +ewf_0d: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 8 +ewf_0f: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 1 +ewf_10: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_11: + mvs.w d1_off+6(a7),d0 + bra ewf_full +//d1.w * 2 +ewf_12: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_13: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 4 +ewf_14: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_15: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 8 +ewf_16: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_17: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 1 +ewf_19: + move.l d1_off+4(a7),d0 + bra ewf_full +//d1.l * 2 +ewf_1b: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 4 +ewf_1d: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 8 +ewf_1f: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 1 +ewf_20: + mvs.b (a0)+,d1 + mvs.w d2,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_21: + mvs.w d2,d0 + bra ewf_full +//d2.w * 2 +ewf_22: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_23: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 4 +ewf_24: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_25: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 8 +ewf_26: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_27: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 1 +ewf_29: + move.l d2,d0 + bra ewf_full +//d2.l * 2 +ewf_2b: + move.l d2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 4 +ewf_2d: + move.l d2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 8 +ewf_2f: + move.l d2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 1 +ewf_30: + mvs.b (a0)+,d1 + mvs.w d3,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_31: + mvs.w d3,d0 + bra ewf_full +//d3.w * 2 +ewf_32: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_33: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 4 +ewf_34: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_35: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 8 +ewf_36: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_37: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 1 +ewf_39: + move.l d3,d0 + bra ewf_full +//d3.l * 3 +ewf_3b: + move.l d3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 4 +ewf_3d: + move.l d3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 8 +ewf_3f: + move.l d3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 1 +ewf_40: + mvs.b (a0)+,d1 + mvs.w d4,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_41: + mvs.w d4,d0 + bra ewf_full +//d4.w * 2 +ewf_42: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_43: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 4 +ewf_44: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_45: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 8 +ewf_46: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_47: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 1 +ewf_49: + move.l d4,d0 + bra ewf_full +//d4.l * 4 +ewf_4b: + move.l d4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 4 +ewf_4d: + move.l d4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 8 +ewf_4f: + move.l d4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 1 +ewf_50: + mvs.b (a0)+,d1 + mvs.w d5,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_51: + mvs.w d5,d0 + bra ewf_full +//d5.w * 2 +ewf_52: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_53: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 4 +ewf_54: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_55: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 8 +ewf_56: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_57: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 1 +ewf_59: + move.l d5,d0 + bra ewf_full +//d5.l * 5 +ewf_5b: + move.l d5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 4 +ewf_5d: + move.l d5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 8 +ewf_5f: + move.l d5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 1 +ewf_60: + mvs.b (a0)+,d1 + mvs.w d6,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_61: + mvs.w d6,d0 + bra ewf_full +//d6.w * 2 +ewf_62: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_63: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 4 +ewf_64: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_65: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 8 +ewf_66: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_67: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 1 +ewf_69: + move.l d6,d0 + bra ewf_full +//d6.l * 6 +ewf_6b: + move.l d6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 4 +ewf_6d: + move.l d6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 8 +ewf_6f: + move.l d6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 1 +ewf_70: + mvs.b (a0)+,d1 + mvs.w d7,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_71: + mvs.w d7,d0 + bra ewf_full +//d7.w * 2 +ewf_72: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_73: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 4 +ewf_74: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_75: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 8 +ewf_76: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_77: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 1 +ewf_79: + move.l d7,d0 + bra ewf_full +//d7.l * 7 +ewf_7b: + move.l d7,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 4 +ewf_7d: + move.l d7,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 8 +ewf_7f: + move.l d7,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 1 +ewf_80: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_81: + mvs.w a0_off+6(a7),d0 + bra ewf_full +//a0.w * 2 +ewf_82: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_83: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 4 +ewf_84: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_85: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 8 +ewf_86: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_87: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 1 +ewf_89: + move.l a0_off+4(a7),d0 + bra ewf_full +//a0.l * 2 +ewf_8b: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 4 +ewf_8d: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 8 +ewf_8f: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 1 +ewf_90: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_91: + mvs.w a1_off+6(a7),d0 + bra ewf_full +//a1.w * 2 +ewf_92: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_93: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 4 +ewf_94: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_95: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 8 +ewf_96: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_97: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 1 +ewf_99: + move.l a1_off+4(a7),d0 + bra ewf_full +//a1.l * 2 +ewf_9b: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 4 +ewf_9d: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 8 +ewf_9f: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 1 +ewf_a0: + mvs.b (a0)+,d1 + mvs.w a2,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_a1: + mvs.w a2,d0 + bra ewf_full +//a2.w * 2 +ewf_a2: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_a3: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 4 +ewf_a4: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_a5: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 8 +ewf_a6: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_a7: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 1 +ewf_a9: + move.l a2,d0 + bra ewf_full +//a2.l * 2 +ewf_ab: + move.l a2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 4 +ewf_ad: + move.l a2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 8 +ewf_af: + move.l a2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 1 +ewf_b0: + mvs.b (a0)+,d1 + mvs.w a3,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_b1: + mvs.w a3,d0 + bra ewf_full +//a3.w * 2 +ewf_b2: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_b3: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 4 +ewf_b4: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_b5: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 8 +ewf_b6: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_b7: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 1 +ewf_b9: + move.l a3,d0 + bra ewf_full +//a3.l * 3 +ewf_bb: + move.l a3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 4 +ewf_bd: + move.l a3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 8 +ewf_bf: + move.l a3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 1 +ewf_c0: + mvs.b (a0)+,d1 + mvs.w a4,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_c1: + mvs.w a4,d0 + bra ewf_full +//a4.w * 2 +ewf_c2: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_c3: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 4 +ewf_c4: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_c5: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 8 +ewf_c6: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_c7: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 1 +ewf_c9: + move.l a4,d0 + bra ewf_full +//a4.l * 4 +ewf_cb: + move.l a4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 4 +ewf_cd: + move.l a4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 8 +ewf_cf: + move.l a4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 1 +ewf_d0: + mvs.b (a0)+,d1 + mvs.w a5,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_d1: + mvs.w a5,d0 + bra ewf_full +//a5.w * 2 +ewf_d2: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_d3: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 4 +ewf_d4: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_d5: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 8 +ewf_d6: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_d7: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 1 +ewf_d9: + move.l a5,d0 + bra ewf_full +//a5.l * 5 +ewf_db: + move.l a5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 4 +ewf_dd: + move.l a5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 8 +ewf_df: + move.l a5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 1 +ewf_e0: + mvs.b (a0)+,d1 + mvs.w a6,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_e1: + mvs.w a6,d0 + bra ewf_full +//a6.w * 2 +ewf_e2: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_e3: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 4 +ewf_e4: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_e5: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 8 +ewf_e6: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_e7: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 1 +ewf_e9: + move.l a6,d0 + bra ewf_full +//a6.l * 6 +ewf_eb: + move.l a6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 4 +ewf_ed: + move.l a6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 8 +ewf_ef: + move.l a6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 1 +ewf_f0: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + add.l d1,a1 + rts +ewf_f1: + move.l a1,-(a7) + move.l usp,a1 + mvs.w a1,d0 + move.l (a7)+,a1 + bra ewf_full +//usp.w * 2 +ewf_f2: + mvs.b (a0)+,d1 + move.l usp,a1 + mvs.w a1,d0 + move.l (a7)+,a1 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_f3: + move.l usp,a1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 4 +ewf_f4: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_f5: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 8 +ewf_f6: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_f7: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 1 +ewf_f9: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + bra ewf_full +//usp.l * 7 +ewf_fb: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 4 +ewf_fd: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 8 +ewf_ff: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//----------------------------------------------------------------------------------- +// extension full format rest von ewf +//-------------------------------------------------------------------- +ewf_full: + mvz.b (a0)+,d1 + mvs.w ewff_table-*-2(pc,d1*2),d1 + jmp ewff_table-*-2(pc,d1) +ewff_table: + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //00 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //10 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsw-ewff_table,ewff_w0v-ewff_table,ewff_wwv-ewff_table,ewff_wlv-ewff_table //20 + .short ewff_end-ewff_table,ewff_w0n-ewff_table,ewff_wwn-ewff_table,ewff_wln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsl-ewff_table,ewff_l0v-ewff_table,ewff_lwv-ewff_table,ewff_llv-ewff_table //30 + .short ewff_end-ewff_table,ewff_l0n-ewff_table,ewff_lwn-ewff_table,ewff_lln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //40 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //50 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsw-ewff_table,ewff_wi0-ewff_table,ewff_wiw-ewff_table,ewff_wil-ewff_table //60 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsl-ewff_table,ewff_li0-ewff_table,ewff_liw-ewff_table,ewff_lil-ewff_table //70 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //80 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //90 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //a0 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //b0 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //c0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //d0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //e0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //f0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table +ewff_end: + rts +ewff_bsw: + mvs.w (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_bsl: + move.l (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_i0v: + add.l d0,a1 + move.l (a1),a1 + rts +ewff_iwv: + add.l d0,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_ilv: + add.l d0,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_i0n: + move.l (a1),a1 + add.l d0,a1 + rts +ewff_iwn: + move.l (a1),a1 + add.l d0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_iln: + move.l (a1),a1 + add.l d0,a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_mi0: + add.l d0,a1 + rts +ewff_miw: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_mil: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_wi0: + mvs.w (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_wiw: + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_wil: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_li0: + move.l (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_liw: + move.l (a0)+,d1 + add.l d1,a1 + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_lil: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_w0v: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + rts +ewff_wwv: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_wlv: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_l0v: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + rts +ewff_lwv: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_llv: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_w0n: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + add.l d0,a1 + rts +ewff_wwn: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_wln: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_l0n: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + add.l d0,a1 + rts +ewff_lwn: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_lln: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +/**************************************************************************************************************** + diff --git a/BaS_GNU/sources/exceptions.s b/BaS_GNU/sources/exceptions.s new file mode 100644 index 0000000..e0494c0 --- /dev/null +++ b/BaS_GNU/sources/exceptions.s @@ -0,0 +1,799 @@ +/********************************************************/ +/* exception vectoren intialisieren +/********************************************************/ + +.include "startcf.h" + +.extern ___Bas_base +.extern ___SUP_SP +.extern ___BOOT_FLASH +.extern ___RAMBAR0 +.extern _rt_cacr +.extern _rt_mod +.extern _rt_ssp +.extern _rt_usp +.extern _rt_vbr +.extern _illegal_instruction +.extern _privileg_violation +.extern _mmutr_miss +.extern ___MBAR +.extern ___MMUBAR +.extern _video_tlb +.extern _video_sbt +.extern cpusha + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + +#define MCF_EPORT_EPPAR ___MBAR+0xF00 +#define MCF_EPORT_EPDDR ___MBAR+0xF04 +#define MCF_EPORT_EPIER ___MBAR+0xF05 +#define MCF_EPORT_EPDR ___MBAR+0xF08 +#define MCF_EPORT_EPPDR ___MBAR+0xF09 +#define MCF_EPORT_EPFR ___MBAR+0xF0C + +#define MCF_GPIO_PODR_FEC1L ___MBAR+0xA07 + +#define MCF_PSC0_PSCTB_8BIT ___MBAR+0x860C + +#define MCF_PSC3_PSCRB_8BIT ___MBAR+0x890C +#define MCF_PSC3_PSCTB_8BIT ___MBAR+0x890C + +.public _vec_init + +//mmu --------------------------------------------------- +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + +#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V) +#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +//--------------------------------------------------- +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS ___MBAR+0x800 + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +#define MCF_SLT0_SCNT ___MBAR+0x908 + +/**********************************************************/ +// macros +/**********************************************************/ +irq: .macro vector,int_mask,clr_int + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern + lea MCF_EPORT_EPFR,a5 + move.b #clr_int,(a5) // clear int pending +// test auf protect mode --------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne @irq_protect // ja-> +// ------------------------------------------- + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + move.l vector,-(a7) + move #0x2\200,sr + rts +@irq_protect: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne @sev_supint // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben +#endif + bra @irq_end +@sev_supint: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec + bset #5,2(a5) // auf super setzen +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif +@irq_end: + move.l a5,usp // usp setzen + lea vector,a5 + adda.l _rt_vbr,a5 + move.l (a5),12(a7) // vectoradresse eintragen + move.b #int_mask,10(a7) // intmaske setzen + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg + .endm +/*********************************************************/ +.text +_vec_init: + mov3q.l #-1,_rt_mod // rt_mod auf super + clr.l _rt_ssp + clr.l _rt_usp + clr.l _rt_vbr + move.l #___RAMBAR0,d0 // sind in rambar0 + movec d0,VBR + move.l d0,a0 + move.l a0,a2 +init_vec: + move.l #256,d0 + lea std_exc_vec(pc),a1 // standard vector +init_vec_loop: + move.l a1,(a2)+ // mal standard vector für alle setzen + subq.l #1,d0 + bne init_vec_loop + + move.l #___SUP_SP,(a0) + lea reset_vector(pc),a1 + move.l a1,0x04(a0) + lea acess(pc),a1 + move.l a1,0x08(a0) + + move.b DIP_SWITCHa,d0 // ++ vr + btst #7,d0 + beq no_protect_vectors + + lea _illegal_instruction(pc),a1 + move.l a1,0x0c(a0) + lea _illegal_instruction(pc),a1 + move.l a1,0x10(a0) + lea zero_divide(pc),a1 + move.l a1,0x14(a0) + lea _privileg_violation(pc),a1 + move.l a1,0x20(a0) + lea linea(pc),a1 + move.l a1,0x28(a0) + lea linef(pc),a1 + move.l a1,0x2c(a0) + lea format(pc),a1 + move.l a1,0x38(a0) + + // floating point overflow + lea flpoow(pc),a1 + move.l a1,0xc0(a0) + lea flpoow(pc),a1 + move.l a1,0xc4(a0) + lea flpoow(pc),a1 + move.l a1,0xc8(a0) + lea flpoow(pc),a1 + move.l a1,0xcc(a0) + lea flpoow(pc),a1 + move.l a1,0xd0(a0) + lea flpoow(pc),a1 + move.l a1,0xd4(a0) + lea flpoow(pc),a1 + move.l a1,0xd8(a0) + lea flpoow(pc),a1 + move.l a1,0xdc(a0) +no_protect_vectors: + + +// int 1-7 + lea irq1(pc),a1 + move.l a1,0x104(a0) + lea irq2(pc),a1 + move.l a1,0x108(a0) + lea irq3(pc),a1 + move.l a1,0x10c(a0) + lea irq4(pc),a1 + move.l a1,0x110(a0) + lea irq5(pc),a1 + move.l a1,0x114(a0) + lea irq6(pc),a1 + move.l a1,0x118(a0) + lea irq7(pc),a1 + move.l a1,0x11c(a0) +//psc_vectors + lea psc3(pc),a1 + move.l a1,0x180(a0) +//timer 1 vectors + lea timer0(pc),a1 + move.l a1,0x1f8(a0) + rts +/********************************************************/ +/* exception vector routinen +/********************************************************/ +vector_table_start: +std_exc_vec: + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern +// test auf protect mode ------------------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne stv_protect // ja-> +//------------------------------------------------------ + move.w 8(a7),d0 // vector holen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),d0 + move.l 4(a7),a5 // a5 zurück + move.l d0,4(a7) + move.w 10(a7),d0 + bset #13,d0 // super + move.w d0,sr // orginal sr wert in super setzen + move.l (a7)+,d0 // d0 zurück + rts +stv_protect: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_sup // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),d0 // sr holen + move.l d0,-(a5) // sr transferieren + swap d0 // vec -> lw +#else + move.w 8(a7),d0 // vector holen + move.w d0,-(a5) // ablegen + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren +#endif + move.l a5,usp // usp setzen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),12(a7) // hier geht's weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg +sev_sup: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),d0 // sr holen + bset #13,d0 // war aus rt super + move.l d0,-(a5) // sr transferieren + swap d0 // vec -> lw +#else + move.w 8(a7),d0 // vector holen + move.w d0,-(a5) // ablegen + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren + bset #5,(a5) // war aus super +#endif + move.l a5,usp // usp setzen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),12(a7) // hier geht's weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg +//******************************************* +reset_vector: + move.w #0x2700,sr // disable interrupt + move.l #0x31415926,d0 + cmp.l 0x426,d0 // reset vector gültg? + beq std_exc_vec // ja-> + jmp ___BOOT_FLASH // sonst kaltstart +acess: + move.w #0x2700,sr // disable interrupt + move.l d0,-(sp) // ++ vr + move.w 4(sp),d0 + andi.l #0x0c03,d0 + cmpi.l #0x0401,d0 + beq access_mmu + cmpi.l #0x0402,d0 + beq access_mmu + cmpi.l #0x0802,d0 + beq access_mmu + cmpi.l #0x0c02,d0 + beq access_mmu + bra bus_error +access_mmu: + move.l MCF_MMU_MMUSR,d0 + btst #1,d0 + bne bus_error + move.l MCF_MMU_MMUAR,d0 + cmp.l #___Bas_base,d0 // max User RAM Bereich + bge bus_error // grösser -> bus error + bra _mmutr_miss +bus_error: + move.l (sp)+,d0 + bra std_exc_vec + +zero_divide: + move.w #0x2700,sr // disable interrupt + move.l a0,-(a7) + move.l d0,-(a7) + move.l 12(a7),a0 // pc + move.w (a0)+,d0 // befehlscode + btst #7,d0 // long? + beq zd_word // nein-> + addq.l #2,a0 +zd_word: + and.l 0x3f,d0 // ea ausmaskieren + cmp.w #0x08,d0 // -(ax) oder weniger + ble zd_end + addq.l #2,a0 + cmp.w #0x39,d0 // xxx.L + bne zd_nal + addq.l #2,a0 + bra zd_end +zd_nal: cmp.w #0x3c,d0 // immediate? + bne zd_end // nein-> + btst #7,d0 // long? + beq zd_end // nein + addq.l #2,a0 +zd_end: + move.l a0,12(a7) + move.l (a7)+,d0 + move.l (a7)+,a0 + rte + +linea: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +linef: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +format: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +//floating point +flpoow: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +irq1: + irq 0x64,1,0x02 +irq2: // hbl + // move.b #3,2(a7) + // rte + irq 0x68,2,0x04 +irq3: + irq 0x6c,3,0x08 +irq4: // vbl + irq 0x70,4,0x10 +irq5: // acp + irq 0x74,5,0x20 +irq6: // mfp + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern + lea MCF_EPORT_EPFR,a5 + move.b #0x40,(a5) // clear int6 +// test auf timeout screen adr change ------------------------------------------------------- + move.l _video_sbt,d0 + beq irq6_non_sca // wenn 0 nichts zu tun + sub.l #0x70000000,d0 // 14 sec abzählen + lea MCF_SLT0_SCNT,a5 + cmp.l (a5),d0 // aktuelle zeit weg + ble irq6_non_sca // noch nicht abgelaufen + lea -28(a7),a7 + movem.l d0-d4/a0-a1,(a7) // register sichern + clr.l d3 // beginn mit 0 + bsr cpusha // cache leeren + // eintrag suchen + irq6_next_sca: + move.l d3,d0 + move.l d0,MCF_MMU_MMUAR // addresse + move.l #0x106,d4 + move.l d4,MCF_MMU_MMUOR // suchen -> + nop + move.l MCF_MMU_MMUOR,d4 + clr.w d4 + swap d4 + move.l d4,MCF_MMU_MMUAR + mvz.w #0x10e,d4 + move.l d4,MCF_MMU_MMUOR // einträge holen aus mmu + nop + move.l MCF_MMU_MMUTR,d4 // ID holen + lsr.l #2,d4 // bit 9 bis 2 + cmp.w #sca_page_ID,d4 // ist screen change ID? + bne irq6_sca_pn // nein -> page keine screen area next +// eintrag ändern + add.l #std_mmutr,d0 + move.l d3,d1 // page 0? + beq irq6_sca_pn0 // ja -> + add.l #cb_mmudr,d1 // sonst page cb + bra irq6_sca_pn1c +irq6_sca_pn0: + add.l #wt_mmudr|MCF_MMU_MMUDR_LK,d1 // page wt and locked +irq6_sca_pn1c: + mvz.w #0x10b,d2 // MMU update + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setze tlb data only + nop +// page copy + move.l d3,a0 + add.l #0x60000000,a0 + move.l d3,a1 + move.l #0x10000,d4 // die ganze page +irq6_vcd0_loop: + move.l (a0)+,(a1)+ // page copy + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + subq.l #1,d4 + bne irq6_vcd0_loop + nop +irq6_sca_pn: + add.l #0x00100000,d3 // next + cmp.l #0x00d00000,d3 // ende? + blt irq6_next_sca // nein-> + + move.l #0x2000,d0 + move.l d0,_video_tlb // anfangszustand wieder herstellen + clr.l _video_sbt // zeit löschen + + movem.l (a7),d0-d4/a0-a1 // register zurück + lea 28(a7),a7 +irq6_non_sca: +// test auf acsi dma ----------------------------------------------------------------- + lea 0xfffffa0b,a5 + bset #7,-4(a5) // int ena + btst.b #7,(a5) // acsi dma int? + beq non_acsi_dma + bsr acsi_dma +non_acsi_dma: +// ---------------------------------------------------------------------------------- + tst.b (a5) + bne irq6_1 + tst.b 2(a5) + bne irq6_1 + movem.l (a7),d0/a5 + addq.l #8,a7 + rte +irq6_1: + lea MCF_GPIO_PODR_FEC1L,a5 + bclr.b #4,(a5) // led on + lea blinker(pc),a5 + addq.l #1,(a5) // +1 + move.l (a5),d0 + and.l #0x80,d0 + bne irq6_2 + lea MCF_GPIO_PODR_FEC1L,a5 + bset.b #4,(a5) // led off +irq6_2: +// test auf protect mode --------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne irq6_3 // ja-> +// ------------------------------------------- + move.l 0xF0020000,a5 // vector holen + add.l _rt_vbr,a5 // basis + move.l (a5),d0 // vector holen + move.l 4(a7),a5 // a5 zurück + move.l d0,4(a7) // vector eintragen + move.l (a7)+,d0 // d0 zurück + move #0x2600,sr + rts +irq6_3: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_sup6 // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr transferieren +#else + move.w 8(a7),-(a5) // vector transferieren + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren +#endif + move.l a5,usp // usp setzen + move.l 0xF0020000,a5 // vector holen: intack routine + add.l _rt_vbr,a5 // virtuelle VBR des Systems + move.l (a5),12(a7) // hier gehts weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + move.b #6,2(a7) // intmaske setzen + rte // und weg +sev_sup6: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec + bset #5,2(a5) // auf super setzen +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif + move.l a5,usp // usp setzen + move.l 0xF0020000,a5 // vector holen: intack routine + add.l _rt_vbr,a5 // virtuelle VBR des Systems + move.l (a5),12(a7) // hier gehts weiter + movem.l (a7),d0/a5 // register zurück + rts +blinker:.long 0 +/**************************************************/ +/* pseudo dma */ +/**************************************************/ +acsi_dma: // atari dma + move.l a1,-(a7) + move.l d1,-(a7) + + lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr + move.l #'DMA ',(a1) + move.l #'INT!',(a1) + + lea 0xf0020110,a5 // fifo daten +acsi_dma_start: + move.l -12(a5),a1 // dma adresse + move.l -8(a5),d0 // byt counter + ble acsi_dma_end + btst.b #0,-16(a5) // write? (dma modus reg) + bne acsi_dma_wl // ja-> +acsi_dma_rl: + tst.b -4(a5) // dma req? + bpl acsi_dma_fertig // nein-> + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + + moveq #'.',d1 + move.b d1,MCF_PSC0_PSCTB_8BIT + + sub.l #16,d0 // byt counter -16 + bpl acsi_dma_rl + bra acsi_dma_fertig +acsi_dma_wl: + tst.b -4(a5) // dma req? + bpl acsi_dma_fertig // nein-> + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + + moveq #'.',d1 + move.b d1,MCF_PSC0_PSCTB_8BIT + + sub.l #16,d0 // byt counter -16 + bpl acsi_dma_wl +acsi_dma_fertig: + move.l a1,-12(a5) // adresse zurück + move.l d0,-8(a5) // byt counter zurück +acsi_dma_end: + tst.b -4(a5) // dma req? + bmi acsi_dma_start // ja-> + lea 0xfffffa0b,a5 + bclr.b #7,4(a5) // clear int in service mfp + bclr.b #7,(a5) // clear int pending mfp 0xfffffa0b + + move.w #0x0d0a,d1 + move.w d1,MCF_PSC0_PSCTB_8BIT + + move.l (a7)+,d1 + move.l (a7)+,a1 + rts +/**************************************************/ +/* irq 7 = pseudo bus error */ +/**************************************************/ +irq7: + lea -12(sp),sp + movem.l d0/a0,(sp) + + move.l ___RAMBAR0+0x008,a0 // Real Access Error handler + move.l a0,8(sp) // This will be the return address for rts + + move.w 12(sp),d0 // Format/Vector word + andi.l #0xf000,d0 // Keep only the Format + ori.l #2*4,d0 // Simulate Vector #2, no Fault + move.w d0,12(sp) + + // TODO: Inside an interrupt handler, 16(sp) is the return address. + // For an Access Error, it should be the address of the fault instruction instead + + lea MCF_EPORT_EPFR,a0 + move.b #0x80,(a0) // clear int7 + move.l (sp)+,d0 + move.l (sp)+,a0 + rts // Forward to the Access Error handler + +/**************************************************/ +/* psc3 com PIC MCF */ +/**************************************************/ +psc3: + move.w #0x2700,sr // disable interrupt + lea -20(a7),a7 + movem.l d0-d2/a0/a3,(a7) + lea MCF_PSC3_PSCRB_8BIT,a3 + move.b (a3),d1 + cmp.b #2,d1 // anforderung rtc daten? + bne psc3_fertig + + lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr + move.l #'PIC ',(a0) + move.l #'INT ',(a0) + move.l #'RTC!',(a0) + move.l #0x0d0a,(a0) + + lea 0xffff8961,a0 + lea MCF_PSC3_PSCTB_8BIT,a3 + clr.l d1 + moveq #64,d2 + move.b #0x82,(a3) // header: rtcd mcf->pic +loop_sr2: + move.b d1,(a0) + move.b 2(a0),d0 + move.b d0,(a3) + addq.l #1,d1 + cmp.b d1,d2 + bne loop_sr2 +psc3_fertig: + movem.l (a7),d0-d2/a0/a3 // register zurück + lea 20(a7),a7 + RTE +/**************************************************/ +/* timer 0: video change later also others +/**************************************************/ +timer0: + move #0x2700,sr +// halt + lea -28(a7),a7 + movem.l d0-d4/a0-a1,(a7) + mvz.b 0xffff8201,d0 // löschen und high byt + cmp.w #2,d0 + blt video_chg_end + cmp.w #0xd0,d0 // normale addresse + blt sca_other // nein-> + lea MCF_SLT0_SCNT,a0 + move.l (a0),d4 + move.l d4,_video_sbt // time sichern +sca_other: + lsl.l #8,d0 + move.b 0xffff8203,d0 // mid byt + lsl.l #8,d0 + move.b 0xffff820d,d0 // low byt + move.l d0,d3 +video_chg_1page: +// test ob page schon gesetzt + moveq #20,d4 + move.l d0,d2 + lsr.l d4,d2 // neue page + move.l _video_tlb,d4 + bset.l d2,d4 // setzen als geändert + bne video_chg_2page // schon gesetzt gewesen? ja->weg + move.l d4,_video_tlb + bsr cpusha // cache leeren +// daten copieren +video_copy_data: + move.l d4,_video_tlb + and.l #0x00f00000,d0 + move.l d0,a0 + move.l a0,a1 + add.l #0x60000000,a1 + move.l #0x10000,d4 // die ganze page +video_copy_data_loop: + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + subq.l #1,d4 + bne video_copy_data_loop +// eintrag suchen + move.l d0,MCF_MMU_MMUAR // addresse + move.l #0x106,d4 + move.l d4,MCF_MMU_MMUOR // suchen -> schlägt neuen vor wenn keiner + nop + move.l MCF_MMU_MMUOR,d4 + clr.w d4 + swap d4 + move.l d4,MCF_MMU_MMUAR + move.l d0,d1 + add.l #MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 + add.l #0x60000000|wt_mmudr|MCF_MMU_MMUDR_LK,d1 + mvz.w #0x10b,d2 // MMU update + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen vidoe maped to 60xxx only data + nop +video_chg_2page: +// test ob evt. anschliessende page gesetzt werden muss + move.l d3,d0 + mvz.w 0xffff8210,d4 // byts pro zeile + mvz.w 0xffff82aa,d2 // zeilen ende + mvz.w 0xffff82a8,d1 // zeilenstart + sub.l d1,d2 // differenz = anzahl zeilen + mulu d2,d4 // maximal 480 zeilen + add.l d4,d0 // video grösse + cmp.l #0xe00000,d0 // maximale addresse + bge video_chg_end // wenn gleich oder grösser -> fertig + moveq #20,d4 + move.l d0,d2 + lsr.l d4,d2 // neue page + move.l _video_tlb,d4 + bset.l d2,d4 // setzen als geändert + beq video_copy_data // nein nochmal +video_chg_end: +// int pending löschen + lea MCF_GPT0_GMS,a0 + bclr.b #0,3(a0) + nop + bset.b #0,3(a0) + + movem.l (a7),d0-d4/a0-a1 + lea 28(a7),a7 +//-------------------------------------------------------------------------------------------------------- + RTE + diff --git a/BaS_GNU/sources/ii_add.h b/BaS_GNU/sources/ii_add.h new file mode 100644 index 0000000..bc23f63 --- /dev/null +++ b/BaS_GNU/sources/ii_add.h @@ -0,0 +1,581 @@ +//-------------------------------------------------------------------- +// add +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// add.b #im,dx +//-------------------------------------------------------------------- +addbir_macro:.macro + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + add.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add ea,dx +//-------------------------------------------------------------------- +adddd:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add ea,dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddd:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add (ea),dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +adddda:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add (ay)+,dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddai:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add -(ay),dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d16(ay),dx +//-------------------------------------------------------------------- +addd16ad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d8(ay,dy),dx +//-------------------------------------------------------------------- +addd8ad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add xxx.w,dx +//-------------------------------------------------------------------- +addxwd:.macro +#ifdef halten_add + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add xxx.l,dx +//-------------------------------------------------------------------- +addxld:.macro +#ifdef halten_add + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d16(pc),dx +//-------------------------------------------------------------------- +addd16pcd:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d8(pc,dy),dx +//-------------------------------------------------------------------- +addd8pcd:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// add dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // add dx,(ay) (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addeda:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,(ay)+ (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addedai:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,(ay)+ +//-------------------------------------------------------------------- +addedaid:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,-(ay) +//-------------------------------------------------------------------- +addedad:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,-(ay) +//-------------------------------------------------------------------- +addedadd:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,d16(ay) +//-------------------------------------------------------------------- +adde16ad:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add.w d8(ay,dy),dx +//-------------------------------------------------------------------- +adde8ad:.macro +#ifdef halten_add + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,xxx.w +//-------------------------------------------------------------------- +addxwe:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,xxx.l +//-------------------------------------------------------------------- +addxle:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// // adda.w ea,ax (ea = dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addaw:.macro +#ifdef halten_add + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + mvs.w \1,d0 + adda.l d0,\2 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// add.w ea,usp +//-------------------------------------------------------------------- +addawa7:.macro +#ifdef halten_add + halt +#endif + mvs.w \1,d0 + move.l usp,a1 + add.l d0,a1 + move.l a1,usp + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w ea,usp (ea = dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addawu:.macro +#ifdef halten_add + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + move.l a7,_a7_save + move.l usp,a7 + move.l \1,d0 + adda.l d0,\2 + move.l a7,usp + move.l _a7_save,a7 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// // adda.w ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addawua7:.macro + addawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // adda.w d16(ay),ax +//-------------------------------------------------------------------- +addawd16a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + adda.l d0,a1 + mvs.w (a1),d0 + move.l \2,a1 + add.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d8(ay,dy),ax +//-------------------------------------------------------------------- +addawd8a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + add.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w xxx.w,ax +//-------------------------------------------------------------------- +addawxwax:.macro +#ifdef halten_add + halt +#endif + move.w \1,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w xxx.l,ax +//-------------------------------------------------------------------- +addawxlax:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d16(pc),ax +//-------------------------------------------------------------------- +addawd16pcax:.macro +#ifdef halten_add + halt +#endif + move.w \1,a1 + adda.l a0,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d8(pc,dy),ax +//-------------------------------------------------------------------- +addawd8pcax:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w #im,ax +//-------------------------------------------------------------------- +addawim:.macro +#ifdef halten_add + halt +#endif + mvs.w \1,d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.l d8(ay,dy),ax +//-------------------------------------------------------------------- +addald8a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.l d8(pc,dy),ax +//-------------------------------------------------------------------- +addakd8pcax:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//***************************************************************************************** +// addx +//***************************************************************************************** +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +adddx:.macro +#ifdef halten_add + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + mvs.\3 \2,d0 + mvs.\3 \1,d1 + addx.l d0,d1 + set_cc0 + move.\3 d1,\1 + ii_end + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +adddax:.macro +#ifdef halten_add + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + move.l \1,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d0 +.endif + move.l \2,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d1 +.endif + addx.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_and.h b/BaS_GNU/sources/ii_and.h new file mode 100644 index 0000000..f74afde --- /dev/null +++ b/BaS_GNU/sources/ii_and.h @@ -0,0 +1,441 @@ +//-------------------------------------------------------------------- +// and +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// and.b #im,dx +//-------------------------------------------------------------------- +andbir_macro:.macro + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + and.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea,dx +//-------------------------------------------------------------------- +anddd:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +andddd:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and (ea)->dy,dx +//-------------------------------------------------------------------- +anddda:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +andddai:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea->ay,-(ay),dx +//-------------------------------------------------------------------- +andddad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d16(ay),dx +//-------------------------------------------------------------------- +andd16ad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d8(ay,dy),dx +//-------------------------------------------------------------------- +andd8ad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and xxx.w,dx +//-------------------------------------------------------------------- +andxwd:.macro +#ifdef halten_and + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and xxx.l,dx +//-------------------------------------------------------------------- +andxld:.macro +#ifdef halten_and + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d16(pc),dx +//-------------------------------------------------------------------- +andd16pcd:.macro +#ifdef halten_and + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d8(pc,dy),dx +//-------------------------------------------------------------------- +andd8pcd:.macro +#ifdef halten_and + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// and dx,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // and dx,(ea)->dy +//-------------------------------------------------------------------- +andeda:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +andedai:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +andedaid:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +andedad:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +andedadd:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,d16(ay) +//-------------------------------------------------------------------- +ande16ad:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and.w dx,d8(ay,dy) +//-------------------------------------------------------------------- +ande8ad:.macro +#ifdef halten_and + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,xxx.w +//-------------------------------------------------------------------- +andxwe:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,xxx.l +//-------------------------------------------------------------------- +andxle:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // anda.w ea,ax +//-------------------------------------------------------------------- +andaw:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// and.w ea,usp +//-------------------------------------------------------------------- +andawa7:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w usp?,ax +//-------------------------------------------------------------------- +andawu:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w usp?,usp +//-------------------------------------------------------------------- +andawua7:.macro + andawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // anda.w d16(ay),ax +//-------------------------------------------------------------------- +andawd16a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d8(ay,dy),ax +//-------------------------------------------------------------------- +andawd8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w xxx.w,ax +//-------------------------------------------------------------------- +andawxwax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w xxx.l,ax +//-------------------------------------------------------------------- +andawxlax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d16(pc),ax +//-------------------------------------------------------------------- +andawd16pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d8(pc,dy),ax +//-------------------------------------------------------------------- +andawd8pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w #im,ax +//-------------------------------------------------------------------- +andawim:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.l d8(ay,dy),ax +//-------------------------------------------------------------------- +andald8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.l d8(pc,dy),ax +//-------------------------------------------------------------------- +andald8pcax:.macro + jmp ii_error + .endm; +//***************************************************************************************** +// spezial addx subx etc. +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +anddx:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +anddax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_dbcc.h b/BaS_GNU/sources/ii_dbcc.h new file mode 100644 index 0000000..652cdbe --- /dev/null +++ b/BaS_GNU/sources/ii_dbcc.h @@ -0,0 +1,117 @@ +//-------------------------------------------------------------------- +// dbcc,trapcc +//-------------------------------------------------------------------- +.text +ii_lset_dbcc:.macro +// dbra + ii_lset_opeau 51,c + ii_lset_opeau 52,c + ii_lset_opeau 53,c + ii_lset_opeau 54,c + ii_lset_opeau 55,c + ii_lset_opeau 56,c + ii_lset_opeau 57,c + ii_lset_opeau 58,c + ii_lset_opeau 59,c + ii_lset_opeau 5a,c + ii_lset_opeau 5b,c + ii_lset_opeau 5c,c + ii_lset_opeau 5d,c + ii_lset_opeau 5e,c + ii_lset_opeau 5f,c +.endm + +ii_dbcc_func:.macro +ii_0x51c8: + dbra_macro d0_off+2(a7) +ii_0x51c9: + dbra_macro d1_off+2(a7) +ii_0x51ca: + dbra_macro d2 +ii_0x51cb: + dbra_macro d3 +ii_0x51cc: + dbra_macro d4 +ii_0x51cd: + dbra_macro d5 +ii_0x51ce: + dbra_macro d6 +ii_0x51cf: + dbra_macro d7 +//--------------------------------------------------------------------------------------------- +// dbcc dx +//--------------------------------------------------------------------------------------------- + ii_dbcc 2,hi + ii_dbcc 3,ls + ii_dbcc 4,cc + ii_dbcc 5,cs + ii_dbcc 6,ne + ii_dbcc 7,eq + ii_dbcc 8,vc + ii_dbcc 9,vs + ii_dbcc a,pl + ii_dbcc b,mi + ii_dbcc c,ge + ii_dbcc d,lt + ii_dbcc e,gt + ii_dbcc f,le +.endm +//--------------------------------------------------------------------------------------------- +// dbra dx +//--------------------------------------------------------------------------------------------- +dbra_macro:.macro +#ifdef halten_dbcc + halt +#endif + mvz.w \1,d1 // dx holen + subq.l #1,d1 // dx-1 + bcc dbra\@ // bra if plus? + addq.l #2,a0 // offset überspringen + move.w d1,\1 // dx sichern + ii_end +dbra\@: + move.w (a0),a1 // offset (wird auf long erweitert) + add.l a1,a0 // dazuadieren + move.w d1,\1 // dx sichern + ii_end +.endm +//--------------------------------------------------------------------------------------------- +// dbcc dx +//--------------------------------------------------------------------------------------------- +dbcc_macro:.macro +#ifdef halten_dbcc + halt +#endif + b\2 dbncc\@ + mvz.w \1,d1 // dx holen + subq.l #1,d1 // dx-1 + bcc dbcc\@ // bra if plus? +dbncc\@: + addq.l #2,a0 // offset überspringen + move.w d1,\1 // dx sichern + ii_end +dbcc\@: + move.w (a0),a1 // offset (wird auf long erweitert) + add.l a1,a0 // dazuadieren + move.w d1,\1 // dx sichern + ii_end +.endm +//db +ii_dbcc:.macro +ii_0x5\1c8: + dbcc_macro d0_off+2(a7),\2 +ii_0x5\1c9: + dbcc_macro d1_off+2(a7),\2 +ii_0x5\1ca: + dbcc_macro d2,\2 +ii_0x5\1cb: + dbcc_macro d3,\2 +ii_0x5\1cc: + dbcc_macro d4,\2 +ii_0x5\1cd: + dbcc_macro d5,\2 +ii_0x5\1ce: + dbcc_macro d6,\2 +ii_0x5\1cf: + dbcc_macro d7,\2 +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_ewf.h b/BaS_GNU/sources/ii_ewf.h new file mode 100644 index 0000000..34d2483 --- /dev/null +++ b/BaS_GNU/sources/ii_ewf.h @@ -0,0 +1,181 @@ +//-------------------------------------------------------------------- +// extension word format missing +//-------------------------------------------------------------------- +.text +ii_ewf_lset:.macro +// pea + ii_lset_opeag 48,7 + ii_lset 0x487b +// jmp + ii_lset_opeag 4e,f + ii_lset 0x4efb +// jsr + ii_lset_opeag 4e,b + ii_lset 0x4ebb +// tas + ii_lset_opeag 4a,f + ii_lset 0x4ebb +// tst.b + ii_lset_opeag 4a,3 + ii_lset 0x4ebb +// tst.w + ii_lset_opeag 4a,7 + ii_lset 0x4ebb +// tst.l + ii_lset_opeag 4a,b + ii_lset 0x4ebb +// clr.b + ii_lset_opeag 42,3 + ii_lset 0x423b +// clr.w + ii_lset_opeag 42,7 + ii_lset 0x423b +// clr.l + ii_lset_opeag 42,b + ii_lset 0x423b +.endm +//--------------------------------------------------------------------------------------------- +ii_ewf_func:.macro + ewf_func_macro pea,487 + ewf_func_macro jmp,4ef + ewf_func_macro jsr,4eb + ewf_func_macro tas,4af + ewf_func_macro tstb,4a3 + ewf_func_macro tstw,4a7 + ewf_func_macro tstl,4ab + ewf_func_macro clrb,423 + ewf_func_macro clrw,427 + ewf_func_macro clrl,42b +.endm +//--------------------------------------------------------------------------------------------- +pea_macro:.macro + jsr ewf + move.l (a1),d0 + move.l usp,a1 + move.l d0,-(a1) + move.l a1,usp + ii_end +.endm + +jmp_macro:.macro + jsr ewf + move.l a1,a0 + ii_end +.endm + +jsr_macro:.macro + jsr ewf + move.l a1,d0 + move.l usp,a1 + move.l a0,-(a1) + move.l a1,usp + move.l d0,a0 + ii_end +.endm + +tas_macro:.macro + jsr ewf + tas (a1) + set_cc0 + ii_end +.endm + +tstb_macro:.macro + jsr ewf + tst.b (a1) + set_cc0 + ii_end +.endm + +tstw_macro:.macro + jsr ewf + tst.w (a1) + set_cc0 + ii_end +.endm + +tstl_macro:.macro + jsr ewf + tst.l (a1) + set_cc0 + ii_end +.endm + +clrb_macro:.macro + jsr ewf + clr.b (a1) + set_cc0 + ii_end +.endm + +clrw_macro:.macro + jsr ewf + clr.w (a1) + set_cc0 + ii_end +.endm + +clrl_macro:.macro + jsr ewf + clr.l (a1) + set_cc0 + ii_end +.endm +//-------------------------------------------------------------------- +ewf_func_macro:.macro //1=art 2=code +ii_0x\20: +#ifdef halten_ewf + halt +#endif + move.l a0_off(a7),a1 + \1_macro +ii_0x\21: +#ifdef halten_ewf + halt +#endif + move.l a1_off(a7),a1 + \1_macro +ii_0x\22: +#ifdef halten_ewf + halt +#endif + move.l a2,a1 + \1_macro +ii_0x\23: +#ifdef halten_ewf + halt +#endif + move.l a3,a1 + \1_macro +ii_0x\24: +#ifdef halten_ewf + halt +#endif + move.l a4,a1 + \1_macro +ii_0x\25: +#ifdef halten_ewf + halt +#endif + move.l a5,a1 + \1_macro +ii_0x\26: +#ifdef halten_ewf + halt +#endif + move.l a6,a1 + \1_macro +ii_0x\27: +#ifdef halten_ewf + halt +#endif + move.l usp,a1 + \1_macro +ii_0x\2b: +#ifdef halten_ewf + halt +#endif + move.l a0,a1 + \1_macro +.endm + diff --git a/BaS_GNU/sources/ii_exg.h b/BaS_GNU/sources/ii_exg.h new file mode 100644 index 0000000..a0544af --- /dev/null +++ b/BaS_GNU/sources/ii_exg.h @@ -0,0 +1,120 @@ +//-------------------------------------------------------------------- +// exg +//-------------------------------------------------------------------- +.text +ii_exg_lset:.macro +/* ii_lset_dxu c,40 //dx,d0 + ii_lset_dxu c,41 //dx,d1 + ii_lset_dxu c,42 //dx,d2 + ii_lset_dxu c,43 //dx,d3 + ii_lset_dxu c,44 //dx,d4 + ii_lset_dxu c,45 //dx,d5 + ii_lset_dxu c,46 //dx,d6 + ii_lset_dxu c,47 //dx,d7 + ii_lset_dxu c,48 //ax,a0 + ii_lset_dxu c,49 //ax,a1 + ii_lset_dxu c,4a //ax,a2 + ii_lset_dxu c,4b //ax,a3 + ii_lset_dxu c,4c //ax,a4 + ii_lset_dxu c,4d //ax,a5 + ii_lset_dxu c,4e //ax,a6 + ii_lset_dxu c,4f //ax,a7 */ -->setting by "and" + ii_lset_dxu c,88 //dx,a0 + ii_lset_dxu c,89 //dx,a1 + ii_lset_dxu c,8a //dx,a2 + ii_lset_dxu c,8b //dx,a3 + ii_lset_dxu c,8c //dx,a4 + ii_lset_dxu c,8d //dx,a5 + ii_lset_dxu c,8e //dx,a6 + ii_lset_dxu c,8f //dx,a7 +.endm +//--------------------------------------------------------------------------------------------- +ii_exg_func:.macro +// exg dx,dy + ii_exg_dx_dx 14,d0_off(a7) + ii_exg_dx_dx 34,d1_off(a7) + ii_exg_dx_dx 54,d2 + ii_exg_dx_dx 74,d3 + ii_exg_dx_dx 94,d4 + ii_exg_dx_dx b4,d5 + ii_exg_dx_dx d4,d6 + ii_exg_dx_dx f4,d7 +// exg ax,ay + ii_exg_to_ax 14,a0_off(a7) + ii_exg_to_ax 34,a1_off(a7) + ii_exg_to_ax 54,a2 + ii_exg_to_ax 74,a3 + ii_exg_to_ax 94,a4 + ii_exg_to_ax b4,a5 + ii_exg_to_ax d4,a6 + ii_exg_to_ax f4,usp +// exg dx,ay + ii_exg_to_ax 18,d0_off(a7) + ii_exg_to_ax 38,d1_off(a7) + ii_exg_to_ax 58,d2 + ii_exg_to_ax 78,d3 + ii_exg_to_ax 98,d4 + ii_exg_to_ax b8,d5 + ii_exg_to_ax d8,d6 + ii_exg_to_ax f8,d7 +.endm +//--------------------------------------------------------------------------------------------- +exg_macro:.macro +#ifdef halten_exg + halt +#endif + move.l \1,a1 +.ifc \2,usp + move.l a1,d0 + move.l \2,a1 + move.l a1,\1 + move.l d0,a1 +.else + .ifc \1,usp + move.l a1,d0 + move.l \2,a1 + move.l a1,\1 + move.l d0,a1 + .else + move.l \2,\1 + .endif +.endif + move.l a1,\2 + ii_end +.endm +ii_exg_dx_dx:.macro +ii_0xc\10: + exg_macro \2,d0_off(a7) +ii_0xc\11: + exg_macro \2,d1_off(a7) +ii_0xc\12: + exg_macro \2,d2 +ii_0xc\13: + exg_macro \2,d3 +ii_0xc\14: + exg_macro \2,d4 +ii_0xc\15: + exg_macro \2,d5 +ii_0xc\16: + exg_macro \2,d6 +ii_0xc\17: + exg_macro \2,d7 +.endm +ii_exg_to_ax:.macro +ii_0xc\18: + exg_macro \2,a0_off(a7) +ii_0xc\19: + exg_macro \2,a1_off(a7) +ii_0xc\1a: + exg_macro \2,a2 +ii_0xc\1b: + exg_macro \2,a3 +ii_0xc\1c: + exg_macro \2,a4 +ii_0xc\1d: + exg_macro \2,a5 +ii_0xc\1e: + exg_macro \2,a6 +ii_0xc\1f: + exg_macro \2,usp +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_func.h b/BaS_GNU/sources/ii_func.h new file mode 100644 index 0000000..f545f47 --- /dev/null +++ b/BaS_GNU/sources/ii_func.h @@ -0,0 +1,945 @@ +//-------------------------------------------------------------------- +// functionen macros +//-------------------------------------------------------------------- +ii_lset_func:.macro +/******************************************************/ +// byt +/******************************************************/ +// func.b dy,dx + ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,01 + ii_lset_dx \1,02 + ii_lset_dx \1,03 + ii_lset_dx \1,04 + ii_lset_dx \1,05 + ii_lset_dx \1,06 + ii_lset_dx \1,07 +// func.b ax,dx + ii_lset_dxu \1,08 + ii_lset_dxu \1,09 + ii_lset_dxu \1,0a + ii_lset_dxu \1,0b + ii_lset_dxu \1,0c + ii_lset_dxu \1,0d + ii_lset_dxu \1,0e + ii_lset_dxu \1,0f +// func.b (ax),dx + ii_lset_dx \1,10 + ii_lset_dx \1,11 + ii_lset_dx \1,12 + ii_lset_dx \1,13 + ii_lset_dx \1,14 + ii_lset_dx \1,15 + ii_lset_dx \1,16 + ii_lset_dx \1,17 +// func.b (ax)+,dx + ii_lset_dx \1,18 + ii_lset_dx \1,19 + ii_lset_dx \1,1a + ii_lset_dx \1,1b + ii_lset_dx \1,1c + ii_lset_dx \1,1d + ii_lset_dx \1,1e + ii_lset_dx \1,1f +// func.b -(ax),dx + ii_lset_dx \1,20 + ii_lset_dx \1,21 + ii_lset_dx \1,22 + ii_lset_dx \1,23 + ii_lset_dx \1,24 + ii_lset_dx \1,25 + ii_lset_dx \1,26 + ii_lset_dx \1,27 +// func.b d16(ax),dx + ii_lset_dx \1,28 + ii_lset_dx \1,29 + ii_lset_dx \1,2a + ii_lset_dx \1,2b + ii_lset_dx \1,2c + ii_lset_dx \1,2d + ii_lset_dx \1,2e + ii_lset_dx \1,2f +// func.b dd8(ax,dy),dx + ii_lset_dx \1,30 + ii_lset_dx \1,31 + ii_lset_dx \1,32 + ii_lset_dx \1,33 + ii_lset_dx \1,34 + ii_lset_dx \1,35 + ii_lset_dx \1,36 + ii_lset_dx \1,37 +// func.b xxx.w,dx + ii_lset_dx \1,38 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b xxx.l,dx + ii_lset_dx \1,39 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b d16(pc),dx + ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b d8(pc,dy),dx + ii_lset_dxg \1,3b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b #im,dx + ii_lset_dxg \1,3c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// word +/******************************************************/ +// func.w dy,dx + ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,41 + ii_lset_dx \1,42 + ii_lset_dx \1,43 + ii_lset_dx \1,44 + ii_lset_dx \1,45 + ii_lset_dx \1,46 + ii_lset_dx \1,47 +// func.w ax,dx + ii_lset_dx \1,48 + ii_lset_dx \1,49 + ii_lset_dx \1,4a + ii_lset_dx \1,4b + ii_lset_dx \1,4c + ii_lset_dx \1,4d + ii_lset_dx \1,4e + ii_lset_dx \1,4f +// func.w (ax),dx + ii_lset_dx \1,50 + ii_lset_dx \1,51 + ii_lset_dx \1,52 + ii_lset_dx \1,53 + ii_lset_dx \1,54 + ii_lset_dx \1,55 + ii_lset_dx \1,56 + ii_lset_dx \1,57 +// func.w (ax)+,dx + ii_lset_dx \1,58 + ii_lset_dx \1,59 + ii_lset_dx \1,5a + ii_lset_dx \1,5b + ii_lset_dx \1,5c + ii_lset_dx \1,5d + ii_lset_dx \1,5e + ii_lset_dx \1,5f +// func.w -(ax),dx + ii_lset_dx \1,60 + ii_lset_dx \1,61 + ii_lset_dx \1,62 + ii_lset_dx \1,63 + ii_lset_dx \1,64 + ii_lset_dx \1,65 + ii_lset_dx \1,66 + ii_lset_dx \1,67 +// func.w d16(ax),dx + ii_lset_dx \1,68 + ii_lset_dx \1,69 + ii_lset_dx \1,6a + ii_lset_dx \1,6b + ii_lset_dx \1,6c + ii_lset_dx \1,6d + ii_lset_dx \1,6e + ii_lset_dx \1,6f +// func.w d8(ax,dy),dx + ii_lset_dx \1,70 + ii_lset_dx \1,71 + ii_lset_dx \1,72 + ii_lset_dx \1,73 + ii_lset_dx \1,74 + ii_lset_dx \1,75 + ii_lset_dx \1,76 + ii_lset_dx \1,77 +// func.w xxx.w,dx + ii_lset_dx \1,78 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w xxx.l,dx + ii_lset_dx \1,79 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w d16(pc),dx + ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w d8(pc,dy),dx + ii_lset_dxg \1,7b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w #im,dx + ii_lset_dxg \1,7c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// long +/******************************************************/ +// func.l ax,dx -> -(ay),-(ax) + ii_lset_dxu \1,c8 + ii_lset_dxu \1,c9 + ii_lset_dxu \1,ca + ii_lset_dxu \1,cb + ii_lset_dxu \1,cc + ii_lset_dxu \1,cd + ii_lset_dxu \1,ce + ii_lset_dxu \1,cf +// func.w d8(ax,dy),dx + ii_lset_dx \1,b0 + ii_lset_dx \1,b1 + ii_lset_dx \1,b2 + ii_lset_dx \1,b3 + ii_lset_dx \1,b4 + ii_lset_dx \1,b5 + ii_lset_dx \1,b6 + ii_lset_dx \1,b7 +// func.l d8(pc,dy),dx + ii_lset_dxg \1,bb // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// adress register +/******************************************************/ +//func.w dy,ax + ii_lset_dxg \1,c0 + ii_lset_dxg \1,c1 + ii_lset_dxg \1,c2 + ii_lset_dxg \1,c3 + ii_lset_dxg \1,c4 + ii_lset_dxg \1,c5 + ii_lset_dxg \1,c6 + ii_lset_dxg \1,c7 +//func.w ay,ax + ii_lset_dxg \1,c8 + ii_lset_dxg \1,c9 + ii_lset_dxg \1,ca + ii_lset_dxg \1,cb + ii_lset_dxg \1,cc + ii_lset_dxg \1,cd + ii_lset_dxg \1,ce + ii_lset_dxg \1,cf +//func.w (ay),ax + ii_lset_dxg \1,d0 + ii_lset_dxg \1,d1 + ii_lset_dxg \1,d2 + ii_lset_dxg \1,d3 + ii_lset_dxg \1,d4 + ii_lset_dxg \1,d5 + ii_lset_dxg \1,d6 + ii_lset_dxg \1,d7 +//func.w (ay)+,ax + ii_lset_dxg \1,d8 + ii_lset_dxg \1,d9 + ii_lset_dxg \1,da + ii_lset_dxg \1,db + ii_lset_dxg \1,dc + ii_lset_dxg \1,dd + ii_lset_dxg \1,de + ii_lset_dxg \1,df +//func.w -(ay),ax + ii_lset_dxg \1,e0 + ii_lset_dxg \1,e1 + ii_lset_dxg \1,e2 + ii_lset_dxg \1,e3 + ii_lset_dxg \1,e4 + ii_lset_dxg \1,e5 + ii_lset_dxg \1,e6 + ii_lset_dxg \1,e7 +//func.w d16(ay),ax + ii_lset_dxg \1,e8 + ii_lset_dxg \1,e9 + ii_lset_dxg \1,ea + ii_lset_dxg \1,eb + ii_lset_dxg \1,ec + ii_lset_dxg \1,ed + ii_lset_dxg \1,ee + ii_lset_dxg \1,ef +//func.w d8(ay,dy),ax + ii_lset_dxg \1,f0 + ii_lset_dxg \1,f1 + ii_lset_dxg \1,f2 + ii_lset_dxg \1,f3 + ii_lset_dxg \1,f4 + ii_lset_dxg \1,f5 + ii_lset_dxg \1,f6 + ii_lset_dxg \1,f7 +// func.w xxx.w,ax + ii_lset_dxg \1,f8 +// func.w xxx.l,ax + ii_lset_dxg \1,f9 +// func.w d16(pc),ax + ii_lset_dxg \1,fa +// func.w d8(pc,dy),ax + ii_lset_dxg \1,fb +// func.w #im,ax + ii_lset_dxg \1,fc +//-------------------------------------------------------------------- +// ende + .endm; +/*****************************************************************************************/ +ii_func:.macro +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.b ds,dx +//-------------------------------------------------------------------- + funcbeadx \1,00,\2dd,d0_off+3(a7) + funcbeadx \1,01,\2dd,d1_off+3(a7) + funcbeadx \1,02,\2dd,d2 + funcbeadx \1,03,\2dd,d3 + funcbeadx \1,04,\2dd,d4 + funcbeadx \1,05,\2dd,d5 + funcbeadx \1,06,\2dd,d6 + funcbeadx \1,07,\2dd,d7 +//-------------------------------------------------------------------- +// func.b (ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,10,\2dda,a0_off(a7) + funcbeadx \1,11,\2dda,a1_off(a7) + funcbeadx \1,12,\2dd,(a2) + funcbeadx \1,13,\2dd,(a3) + funcbeadx \1,14,\2dd,(a4) + funcbeadx \1,15,\2dd,(a5) + funcbeadx \1,16,\2dd,(a6) + funcbeadx \1,17,\2dda,usp +//-------------------------------------------------------------------- +// func.b (ax)+,dx +//-------------------------------------------------------------------- + funcbeadx \1,18,\2ddai,a0_off(a7) + funcbeadx \1,19,\2ddai,a1_off(a7) + funcbeadx \1,1a,\2dd,(a2)+ + funcbeadx \1,1b,\2dd,(a3)+ + funcbeadx \1,1c,\2dd,(a4)+ + funcbeadx \1,1d,\2dd,(a5)+ + funcbeadx \1,1e,\2dd,(a6)+ + funcbeadx \1,1f,\2ddai,usp +//-------------------------------------------------------------------- +// func.b -(ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,20,\2ddad,a0_off(a7) + funcbeadx \1,21,\2ddad,a1_off(a7) + funcbeadx \1,22,\2dd,-(a2) + funcbeadx \1,23,\2dd,-(a3) + funcbeadx \1,24,\2dd,-(a4) + funcbeadx \1,25,\2dd,-(a5) + funcbeadx \1,26,\2dd,-(a6) + funcbeadx \1,27,\2ddad,usp +//-------------------------------------------------------------------- +// func.b d16(ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,28,\2d16ad,a0_off(a7) + funcbeadx \1,29,\2d16ad,a1_off(a7) + funcbeadx \1,2a,\2d16ad,a2 + funcbeadx \1,2b,\2d16ad,a3 + funcbeadx \1,2c,\2d16ad,a4 + funcbeadx \1,2d,\2d16ad,a5 + funcbeadx \1,2e,\2d16ad,a6 + funcbeadx \1,2f,\2d16ad,usp +//-------------------------------------------------------------------- +// func.b d8(ax,dy),dx +//-------------------------------------------------------------------- + funcbeadx \1,30,\2d8ad,a0_off(a7) + funcbeadx \1,31,\2d8ad,a1_off(a7) + funcbeadx \1,32,\2d8ad,a2 + funcbeadx \1,33,\2d8ad,a3 + funcbeadx \1,34,\2d8ad,a4 + funcbeadx \1,35,\2d8ad,a5 + funcbeadx \1,36,\2d8ad,a6 + funcbeadx \1,37,\2d8ad,usp +//-------------------------------------------------------------------- +// func.b xxx.w,dx +//-------------------------------------------------------------------- + funcbeadx \1,38,\2xwd,(a0)+ +//-------------------------------------------------------------------- +// func.b xxx.w,dx +//-------------------------------------------------------------------- + funcbeadx \1,39,\2xld,(a0)+ +//-------------------------------------------------------------------- +// func.b d16(pc),dx +//-------------------------------------------------------------------- + funcbeadx \1,3a,\2d16pcd,(a0)+ +//-------------------------------------------------------------------- +// func.b d8(pc,dy),dx +//-------------------------------------------------------------------- + funcbeadx \1,3b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.b #im,dx +//-------------------------------------------------------------------- + funcbeadx \1,3c,\2bir_macro,(a0)+ +//-------------------------------------------------------------------- +// func.b dy,ea +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.b dx,dd -> addx subx etc. src und dest vertauscht! +//-------------------------------------------------------------------- + funcbdxea \1,00,\2dx,d0_off+3(a7) + funcbdxea \1,01,\2dx,d1_off+3(a7) + funcbdxea \1,02,\2dx,d2 + funcbdxea \1,03,\2dx,d3 + funcbdxea \1,04,\2dx,d4 + funcbdxea \1,05,\2dx,d5 + funcbdxea \1,06,\2dx,d6 + funcbdxea \1,07,\2dx,d7 +//-------------------------------------------------------------------- +// func.b -(ax),-(ay) addx subx etc. src und dest vertauscht! +//-------------------------------------------------------------------- + funcaxay \1,08,\2dax,a0_off(a7),b + funcaxay \1,09,\2dax,a1_off(a7).b + funcaxay \1,0a,\2dax,a2,b + funcaxay \1,0b,\2dax,a3,b + funcaxay \1,0c,\2dax,a4,b + funcaxay \1,0d,\2dax,a5,b + funcaxay \1,0e,\2dax,a6,b + funcaxay \1,0f,\2dax,usp,b +//-------------------------------------------------------------------- +// func.b dy,(ax) +//-------------------------------------------------------------------- + funcbdxea \1,10,\2eda,a0_off(a7) + funcbdxea \1,11,\2eda,a1_off(a7) + funcbdxea \1,12,\2dd,(a2) + funcbdxea \1,13,\2dd,(a3) + funcbdxea \1,14,\2dd,(a4) + funcbdxea \1,15,\2dd,(a5) + funcbdxea \1,16,\2dd,(a6) + funcbdxea \1,17,\2eda,usp +//-------------------------------------------------------------------- +// func.b dy,(ax)+ +//-------------------------------------------------------------------- + funcbdxea \1,18,\2edai,a0_off(a7) + funcbdxea \1,19,\2edai,a1_off(a7) + funcbdxea \1,1a,\2edaid,(a2) + funcbdxea \1,1b,\2edaid,(a3) + funcbdxea \1,1c,\2edaid,(a4) + funcbdxea \1,1d,\2edaid,(a5) + funcbdxea \1,1e,\2edaid,(a6) + funcbdxea \1,1f,\2edai,usp +//-------------------------------------------------------------------- +// func.b dy,-(ax) +//-------------------------------------------------------------------- + funcbdxea \1,20,\2edad,a0_off(a7) + funcbdxea \1,21,\2edad,a1_off(a7) + funcbdxea \1,22,\2edadd,(a2) + funcbdxea \1,23,\2edadd,(a3) + funcbdxea \1,24,\2edadd,(a4) + funcbdxea \1,25,\2edadd,(a5) + funcbdxea \1,26,\2edadd,(a6) + funcbdxea \1,27,\2edad,usp +//-------------------------------------------------------------------- +// func.b dy,d16(ax) +//-------------------------------------------------------------------- + funcbdxea \1,28,\2e16ad,a0_off(a7) + funcbdxea \1,29,\2e16ad,a1_off(a7) + funcbdxea \1,2a,\2e16ad,a2 + funcbdxea \1,2b,\2e16ad,a3 + funcbdxea \1,2c,\2e16ad,a4 + funcbdxea \1,2d,\2e16ad,a5 + funcbdxea \1,2e,\2e16ad,a6 + funcbdxea \1,2f,\2e16ad,usp +//-------------------------------------------------------------------- +// func.b dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcbdxea \1,30,\2e8ad,a0_off(a7) + funcbdxea \1,31,\2e8ad,a1_off(a7) + funcbdxea \1,32,\2e8ad,a2 + funcbdxea \1,33,\2e8ad,a3 + funcbdxea \1,34,\2e8ad,a4 + funcbdxea \1,35,\2e8ad,a5 + funcbdxea \1,36,\2e8ad,a6 + funcbdxea \1,37,\2e8ad,usp +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,38,\2xwe,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,39,\2xld,(a0)+ +/*****************************************************************************************/ +// word +/*****************************************************************************************/ +// func.w ds,dx +//-------------------------------------------------------------------- + funcweadx \1,40,\2dd,d0_off+2(a7) + funcweadx \1,41,\2dd,d1_off+2(a7) + funcweadx \1,42,\2dd,d2 + funcweadx \1,43,\2dd,d3 + funcweadx \1,44,\2dd,d4 + funcweadx \1,45,\2dd,d5 + funcweadx \1,46,\2dd,d6 + funcweadx \1,47,\2dd,d7 +//-------------------------------------------------------------------- +// func.w ax,dx +//-------------------------------------------------------------------- + funcweadx \1,48,\2dd,a0_off+2(a7) + funcweadx \1,49,\2dd,a1_off+2(a7) + funcweadx \1,4a,\2dd,a2 + funcweadx \1,4b,\2dd,a3 + funcweadx \1,4c,\2dd,a4 + funcweadx \1,4d,\2dd,a5 + funcweadx \1,4e,\2dd,a6 + funcweadx \1,4f,\2ddd,usp +//-------------------------------------------------------------------- +// func.w (ax),dx +//-------------------------------------------------------------------- + funcweadx \1,50,\2dda,a0_off(a7) + funcweadx \1,51,\2dda,a1_off(a7) + funcweadx \1,52,\2dd,(a2) + funcweadx \1,53,\2dd,(a3) + funcweadx \1,54,\2dd,(a4) + funcweadx \1,55,\2dd,(a5) + funcweadx \1,56,\2dd,(a6) + funcweadx \1,57,\2dda,usp +//-------------------------------------------------------------------- +// func.w (ax)+,dx +//-------------------------------------------------------------------- + funcweadx \1,58,\2ddai,a0_off(a7) + funcweadx \1,59,\2ddai,a1_off(a7) + funcweadx \1,5a,\2dd,(a2)+ + funcweadx \1,5b,\2dd,(a3)+ + funcweadx \1,5c,\2dd,(a4)+ + funcweadx \1,5d,\2dd,(a5)+ + funcweadx \1,5e,\2dd,(a6)+ + funcweadx \1,5f,\2ddai,usp +//-------------------------------------------------------------------- +// func.w -(ax),dx +//-------------------------------------------------------------------- + funcweadx \1,60,\2ddad,a0_off(a7) + funcweadx \1,61,\2ddad,a1_off(a7) + funcweadx \1,62,\2dd,-(a2) + funcweadx \1,63,\2dd,-(a3) + funcweadx \1,64,\2dd,-(a4) + funcweadx \1,65,\2dd,-(a5) + funcweadx \1,66,\2dd,-(a6) + funcweadx \1,67,\2ddad,usp +//-------------------------------------------------------------------- +// func.w d16(ax),dx +//-------------------------------------------------------------------- + funcweadx \1,68,\2d16ad,a0_off(a7) + funcweadx \1,69,\2d16ad,a1_off(a7) + funcweadx \1,6a,\2d16ad,a2 + funcweadx \1,6b,\2d16ad,a3 + funcweadx \1,6c,\2d16ad,a4 + funcweadx \1,6d,\2d16ad,a5 + funcweadx \1,6e,\2d16ad,a6 + funcweadx \1,6f,\2d16ad,usp +//-------------------------------------------------------------------- +// func.w d8(ax,dy),dx +//-------------------------------------------------------------------- + funcweadx \1,70,\2d8ad,a0_off(a7) + funcweadx \1,71,\2d8ad,a1_off(a7) + funcweadx \1,72,\2d8ad,a2 + funcweadx \1,73,\2d8ad,a3 + funcweadx \1,74,\2d8ad,a4 + funcweadx \1,75,\2d8ad,a5 + funcweadx \1,76,\2d8ad,a6 + funcweadx \1,77,\2d8ad,usp +//-------------------------------------------------------------------- +// func.w xxx.w,dx +//-------------------------------------------------------------------- + funcweadx \1,78,\2xwd,(a0)+ +//-------------------------------------------------------------------- +// func.w xxx.w,dx +//-------------------------------------------------------------------- + funcweadx \1,79,\2xld,(a0)+ +//-------------------------------------------------------------------- +// func.w d16(pc),dx +//-------------------------------------------------------------------- + funcweadx \1,7a,\2d16pcd,(a0)+ +//-------------------------------------------------------------------- +// func.w d8(pc,dy),dx +//-------------------------------------------------------------------- + funcweadx \1,7b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.w #im,dx +//-------------------------------------------------------------------- + funcweadx \1,7c,\2dd,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,ea +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.w dx,dd -> addx subx etc. +//-------------------------------------------------------------------- +.ifnc \2,and //platz für exg + funcwdxea \1,40,\2dx,d0_off+2(a7) + funcwdxea \1,41,\2dx,d1_off+2(a7) + funcwdxea \1,42,\2dx,d2 + funcwdxea \1,43,\2dx,d3 + funcwdxea \1,44,\2dx,d4 + funcwdxea \1,45,\2dx,d5 + funcwdxea \1,46,\2dx,d6 + funcwdxea \1,47,\2dx,d7 +//-------------------------------------------------------------------- +// func.w -(ax),-(ay) -> addx,subx +//-------------------------------------------------------------------- + funcaxay \1,48,\2dax,a0_off(a7),w + funcaxay \1,49,\2dax,a1_off(a7).w + funcaxay \1,4a,\2dax,a2,w + funcaxay \1,4b,\2dax,a3,w + funcaxay \1,4c,\2dax,a4,w + funcaxay \1,4d,\2dax,a5,w + funcaxay \1,4e,\2dax,a6,w + funcaxay \1,4f,\2dax,usp,w +.endif +//-------------------------------------------------------------------- +// func.w dy,(ax) +//-------------------------------------------------------------------- + funcwdxea \1,50,\2eda,a0_off(a7) + funcwdxea \1,51,\2eda,a1_off(a7) + funcwdxea \1,52,\2dd,(a2) + funcwdxea \1,53,\2dd,(a3) + funcwdxea \1,54,\2dd,(a4) + funcwdxea \1,55,\2dd,(a5) + funcwdxea \1,56,\2dd,(a6) + funcwdxea \1,57,\2eda,usp +//-------------------------------------------------------------------- +// func.w dy,(ax)+ +//-------------------------------------------------------------------- + funcwdxea \1,58,\2edai,a0_off(a7) + funcwdxea \1,59,\2edai,a1_off(a7) + funcwdxea \1,5a,\2edaid,(a2) + funcwdxea \1,5b,\2edaid,(a3) + funcwdxea \1,5c,\2edaid,(a4) + funcwdxea \1,5d,\2edaid,(a5) + funcwdxea \1,5e,\2edaid,(a6) + funcwdxea \1,5f,\2edai,usp +//-------------------------------------------------------------------- +// func.w dy,-(ax) +//-------------------------------------------------------------------- + funcwdxea \1,60,\2edad,a0_off(a7) + funcwdxea \1,61,\2edad,a1_off(a7) + funcwdxea \1,62,\2edadd,(a2) + funcwdxea \1,63,\2edadd,(a3) + funcwdxea \1,64,\2edadd,(a4) + funcwdxea \1,65,\2edadd,(a5) + funcwdxea \1,66,\2edadd,(a6) + funcwdxea \1,67,\2edad,usp +//-------------------------------------------------------------------- +// func.w dy,d16(ax) +//-------------------------------------------------------------------- + funcwdxea \1,68,\2e16ad,a0_off(a7) + funcwdxea \1,69,\2e16ad,a1_off(a7) + funcwdxea \1,6a,\2e16ad,a2 + funcwdxea \1,6b,\2e16ad,a3 + funcwdxea \1,6c,\2e16ad,a4 + funcwdxea \1,6d,\2e16ad,a5 + funcwdxea \1,6e,\2e16ad,a6 + funcwdxea \1,6f,\2e16ad,usp +//-------------------------------------------------------------------- +// func.w dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcwdxea \1,70,\2e8ad,a0_off(a7) + funcwdxea \1,71,\2e8ad,a1_off(a7) + funcwdxea \1,72,\2e8ad,a2 + funcwdxea \1,73,\2e8ad,a3 + funcwdxea \1,74,\2e8ad,a4 + funcwdxea \1,75,\2e8ad,a5 + funcwdxea \1,76,\2e8ad,a6 + funcwdxea \1,77,\2e8ad,usp +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,78,\2xwe,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,79,\2xld,(a0)+ +/*****************************************************************************************/ +// long +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// func.l -(ax),-(ay) +//-------------------------------------------------------------------- + funcaxay \1,c8,\2dax,a0_off(a7),l + funcaxay \1,c9,\2dax,a1_off(a7).l + funcaxay \1,ca,\2dax,a2,l + funcaxay \1,cb,\2dax,a3,l + funcaxay \1,cc,\2dax,a4,l + funcaxay \1,cd,\2dax,a5,l + funcaxay \1,ce,\2dax,a6,l + funcaxay \1,cf,\2dax,usp,l +//-------------------------------------------------------------------- +// func.l d8(ax,dy),dx +//-------------------------------------------------------------------- + funcleadx \1,b0,\2d8ad,a0_off(a7) + funcleadx \1,b1,\2d8ad,a1_off(a7) + funcleadx \1,b2,\2d8ad,a2 + funcleadx \1,b3,\2d8ad,a3 + funcleadx \1,b4,\2d8ad,a4 + funcleadx \1,b5,\2d8ad,a5 + funcleadx \1,b6,\2d8ad,a6 + funcleadx \1,b7,\2d8ad,usp +//-------------------------------------------------------------------- +// func.l d8(pc,dy),dx +//-------------------------------------------------------------------- + funcleadx \1,bb,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.l dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcldxea \1,b0,\2e8ad,a0_off(a7) + funcldxea \1,b1,\2e8ad,a1_off(a7) + funcldxea \1,b2,\2e8ad,a2 + funcldxea \1,b3,\2e8ad,a3 + funcldxea \1,b4,\2e8ad,a4 + funcldxea \1,b5,\2e8ad,a5 + funcldxea \1,b6,\2e8ad,a6 + funcldxea \1,b7,\2e8ad,usp +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// func.w ea,ax +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// func.w dx,ax +//-------------------------------------------------------------------- + funcweaax \1,c0,\2aw,d0 + funcweaax \1,c1,\2aw,d1 + funcweaax \1,c2,\2aw,d2 + funcweaax \1,c3,\2aw,d3 + funcweaax \1,c4,\2aw,d4 + funcweaax \1,c5,\2aw,d5 + funcweaax \1,c6,\2aw,d6 + funcweaax \1,c7,\2aw,d7 +//-------------------------------------------------------------------- +// func.w ay,ax +//-------------------------------------------------------------------- + funcweaax \1,c8,\2aw,a0 + funcweaax \1,c9,\2aw,a1 + funcweaax \1,ca,\2aw,a2 + funcweaax \1,cb,\2aw,a3 + funcweaax \1,cc,\2aw,a4 + funcweaax \1,cd,\2aw,a5 + funcweaax \1,ce,\2aw,a6 + funcweaax \1,cf,\2awu,a7 +//-------------------------------------------------------------------- +// func.w (ay),ax +//-------------------------------------------------------------------- + funcweaax \1,d0,\2aw,(a0) + funcweaax \1,d1,\2aw,(a1) + funcweaax \1,d2,\2aw,(a2) + funcweaax \1,d3,\2aw,(a3) + funcweaax \1,d4,\2aw,(a4) + funcweaax \1,d5,\2aw,(a5) + funcweaax \1,d6,\2aw,(a6) + funcweaax \1,d7,\2awu,(a7) +//-------------------------------------------------------------------- +// func.w (ay)+,ax +//-------------------------------------------------------------------- + funcweaax \1,d8,\2aw,(a0)+ + funcweaax \1,d9,\2aw,(a1)+ + funcweaax \1,da,\2aw,(a2)+ + funcweaax \1,db,\2aw,(a3)+ + funcweaax \1,dc,\2aw,(a4)+ + funcweaax \1,dd,\2aw,(a5)+ + funcweaax \1,de,\2aw,(a6)+ + funcweaax \1,df,\2awu,(a7)+ +//-------------------------------------------------------------------- +// func.w -(ay),ax +//-------------------------------------------------------------------- + funcweaax \1,e0,\2aw,-(a0) + funcweaax \1,e1,\2aw,-(a1) + funcweaax \1,e2,\2aw,-(a2) + funcweaax \1,e3,\2aw,-(a3) + funcweaax \1,e4,\2aw,-(a4) + funcweaax \1,e5,\2aw,-(a5) + funcweaax \1,e6,\2aw,-(a6) + funcweaax \1,e7,\2awu,-(a7) +//-------------------------------------------------------------------- +// func.w d16(ay),ax +//-------------------------------------------------------------------- + funcweaaxn \1,e8,\2awd16a,a0_off(a7) + funcweaaxn \1,e9,\2awd16a,a1_off(a7) + funcweaaxn \1,ea,\2awd16a,a2 + funcweaaxn \1,eb,\2awd16a,a3 + funcweaaxn \1,ec,\2awd16a,a4 + funcweaaxn \1,ed,\2awd16a,a5 + funcweaaxn \1,ee,\2awd16a,a6 + funcweaaxn \1,ef,\2awd16a,usp +//-------------------------------------------------------------------- +// func.w d8(ay,dy),ax +//-------------------------------------------------------------------- + funcweaaxn \1,f0,\2awd8a,a0_off(a7) + funcweaaxn \1,f1,\2awd8a,a1_off(a7) + funcweaaxn \1,f2,\2awd8a,a2 + funcweaaxn \1,f3,\2awd8a,a3 + funcweaaxn \1,f4,\2awd8a,a4 + funcweaaxn \1,f5,\2awd8a,a5 + funcweaaxn \1,f6,\2awd8a,a6 + funcweaaxn \1,f7,\2awd8a,usp +//-------------------------------------------------------------------- +// func.w xxx.w,ax +//-------------------------------------------------------------------- + funcweaaxn \1,f8,\2awxwax,(a0)+ +//-------------------------------------------------------------------- +// func.w xxxlw,ax +//-------------------------------------------------------------------- + funcweaaxn \1,f9,\2awxlax,(a0)+ +//-------------------------------------------------------------------- +// func.w d16(pc),ax +//-------------------------------------------------------------------- + funcweaaxn \1,fa,\2awd16pcax,(a0)+ +//-------------------------------------------------------------------- +// func.w d8(pc,dy),ax +//-------------------------------------------------------------------- + funcweaaxn \1,fb,\2awd8pcax,(a0)+ //(a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.w #im,ax +//-------------------------------------------------------------------- + funcweaaxn \1,fc,\2awim,(a0)+ +//-------------------------------------------------------------------- +// ende + .endm; +//-------------------------------------------------------------------- +// byt +funcbeadx:.macro // function byt: im,dx +ii_0x\10\2: + \3 \4,d0_off+3(a7),b +ii_0x\12\2: + \3 \4,d1_off+3(a7),b +ii_0x\14\2: + \3 \4,d2,b +ii_0x\16\2: + \3 \4,d3,b +ii_0x\18\2: + \3 \4,d4,b +ii_0x\1a\2: + \3 \4,d5,b +ii_0x\1c\2: + \3 \4,d6,b +ii_0x\1e\2: + \3 \4,d7,b + .endm; +funcbdxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off+3(a7),\4,b +ii_0x\13\2: + \3 d1_off+3(a7),\4,b +ii_0x\15\2: + \3 d2,\4,b +ii_0x\17\2: + \3 d3,\4,b +ii_0x\19\2: + \3 d4,\4,b +ii_0x\1b\2: + \3 d5,\4,b +ii_0x\1d\2: + \3 d6,\4,b +ii_0x\1f\2: + \3 d7,\4,b + .endm; +//-------------------------------------------------------------------- +// word +funcweadx:.macro // dx function(\3) ea(\4) -> dx +ii_0x\10\2: + \3 \4,d0_off+2(a7),w +ii_0x\12\2: + \3 \4,d1_off+2(a7),w +ii_0x\14\2: + \3 \4,d2,w +ii_0x\16\2: + \3 \4,d3,w +ii_0x\18\2: + \3 \4,d4,w +ii_0x\1a\2: + \3 \4,d5,w +ii_0x\1c\2: + \3 \4,d6,w +ii_0x\1e\2: + \3 \4,d7,w + .endm; +funcwdxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off+2(a7),\4,w +ii_0x\13\2: + \3 d1_off+2(a7),\4,w +ii_0x\15\2: + \3 d2,\4,w +ii_0x\17\2: + \3 d3,\4,w +ii_0x\19\2: + \3 d4,\4,w +ii_0x\1b\2: + \3 d5,\4,w +ii_0x\1d\2: + \3 d6,\4,w +ii_0x\1f\2: + \3 d7,\4,w + .endm; +//-------------------------------------------------------------------- +// long +funcleadx:.macro // dx function(\3) ea(\4) -> dx +ii_0x\10\2: + \3 \4,d0_off(a7),w +ii_0x\12\2: + \3 \4,d1_off(a7),w +ii_0x\14\2: + \3 \4,d2,w +ii_0x\16\2: + \3 \4,d3,w +ii_0x\18\2: + \3 \4,d4,w +ii_0x\1a\2: + \3 \4,d5,w +ii_0x\1c\2: + \3 \4,d6,w +ii_0x\1e\2: + \3 \4,d7,w + .endm; +funcldxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off(a7),\4,w +ii_0x\13\2: + \3 d1_off(a7),\4,w +ii_0x\15\2: + \3 d2,\4,w +ii_0x\17\2: + \3 d3,\4,w +ii_0x\19\2: + \3 d4,\4,w +ii_0x\1b\2: + \3 d5,\4,w +ii_0x\1d\2: + \3 d6,\4,w +ii_0x\1f\2: + \3 d7,\4,w + .endm; +//-------------------------------------------------------------- +// address +funcweaax:.macro // ax function(\3) ea(\4)(ext long!) -> ax +ii_0x\10\2: + \3 \4,a0 +ii_0x\12\2: + \3 \4,a1 +ii_0x\14\2: + \3 \4,a2 +ii_0x\16\2: + \3 \4,a3 +ii_0x\18\2: + \3 \4,a4 +ii_0x\1a\2: + \3 \4,a5 +ii_0x\1c\2: + \3 \4,a6 +ii_0x\1e\2: + \3a7 \4,a7 // "a7" beachten wegen usp + .endm; +funcweaaxn:.macro // ax function(\3) ea(\4)(ext long!) -> ax +ii_0x\10\2: + \3 \4,a0_off(a7) +ii_0x\12\2: + \3 \4,a1_off(a7) +ii_0x\14\2: + \3 \4,a2 +ii_0x\16\2: + \3 \4,a3 +ii_0x\18\2: + \3 \4,a4 +ii_0x\1a\2: + \3 \4,a5 +ii_0x\1c\2: + \3 \4,a6 +ii_0x\1e\2: + \3 \4,usp + .endm; +//-------------------------------------------------------------- +// byt, word, long +//-------------------------------------------------------------- +funcaxay:.macro // ea(\4) function(\3) dx -> ea,\5 = size +ii_0x\11\2: + \3 a0_off(a7),\4,\5 +ii_0x\13\2: + \3 a1_off(a7),\4,\5 +ii_0x\15\2: + \3 a2,\4,\5 +ii_0x\17\2: + \3 a3,\4,\5 +ii_0x\19\2: + \3 a4,\4,\5 +ii_0x\1b\2: + \3 a5,\4,\5 +ii_0x\1d\2: + \3 a6,\4,\5 +ii_0x\1f\2: + \3 usp,\4,\5 + .endm; diff --git a/BaS_GNU/sources/ii_jmp.h b/BaS_GNU/sources/ii_jmp.h new file mode 100644 index 0000000..1896118 --- /dev/null +++ b/BaS_GNU/sources/ii_jmp.h @@ -0,0 +1,59 @@ +//-------------------------------------------------------------------- +// extension word format missing +//-------------------------------------------------------------------- +ii_\1_func:.macro +ii_0x\20: +#ifdef halten_\1 + halt +#endif + move.l a0_off(a7),a1 + \1_macro +ii_0x\21: +#ifdef halten_\1 + halt +#endif + move.l a1_off(a7),a1 + \1_macro +ii_0x\22: +#ifdef halten_\1 + halt +#endif + move.l a2,a1 + \1_macro +ii_0x\23: +#ifdef halten_\1 + halt +#endif + move.l a3,a1 + \1_macro +ii_0x\24: +#ifdef halten_\1 + halt +#endif + move.l a4,a1 + \1_macro +ii_0x\25: +#ifdef halten_\1 + halt +#endif + move.l a5,a1 + \1_macro +ii_0x\26: +#ifdef halten_\1 + halt +#endif + move.l a6,a1 + \1_macro +ii_0x\27: +#ifdef halten_\1 + halt +#endif + move.l usp,a1 + \1_macro +ii_0x\2b: +#ifdef halten_\1 + halt +#endif + move.l a0,a1 + \1_macro +.endm diff --git a/BaS_GNU/sources/ii_lea.h b/BaS_GNU/sources/ii_lea.h new file mode 100644 index 0000000..7a422a7 --- /dev/null +++ b/BaS_GNU/sources/ii_lea.h @@ -0,0 +1,105 @@ +//------------------------------------------------------------------- +// lea +//------------------------------------------------------------------- +.text +ii_lea_lset:.macro + ii_lset_dxu 4,f0 // lea d8(a0,dy.w),a0-a7 + ii_lset_dxu 4,f1 // lea d8(a1,dy.w),a0-a7 + ii_lset_dxu 4,f2 // lea d8(a2,dy.w),a0-a7 + ii_lset_dxu 4,f3 // lea d8(a3,dy.w),a0-a7 + ii_lset_dxu 4,f4 // lea d8(a4,dy.w),a0-a7 + ii_lset_dxu 4,f5 // lea d8(a5,dy.w),a0-a7 + ii_lset_dxu 4,f6 // lea d8(a6,dy.w),a0-a7 + ii_lset_dxu 4,f7 // lea d8(a7,dy.w),a0-a7 + ii_lset_dxu 4,fb // lea d8(pc,dy.w),a0-a7 +.endm + +//--------------------------------------------------------------------------------------------- +// function +//--------------------------------------------------------------------------------------------- +ii_lea_sub:.macro +ii_0x4\1\2: +#ifdef halten_lea + halt +#endif + move.l \4,a1 + jsr ewf + move.l a1,\3 + ii_end +.endm +ii_lea_func:.macro +//lea d8(ax,dy.w),a0-a7 + ii_lea_sub 1,f0,a0_off(a7),a0_off(a7) + ii_lea_sub 1,f1,a0_off(a7),a1_off(a7) + ii_lea_sub 1,f2,a0_off(a7),a2 + ii_lea_sub 1,f3,a0_off(a7),a3 + ii_lea_sub 1,f4,a0_off(a7),a4 + ii_lea_sub 1,f5,a0_off(a7),a5 + ii_lea_sub 1,f6,a0_off(a7),a6 + ii_lea_sub 1,f7,a0_off(a7),usp + ii_lea_sub 3,f0,a1_off(a7),a0_off(a7) + ii_lea_sub 3,f1,a1_off(a7),a1_off(a7) + ii_lea_sub 3,f2,a1_off(a7),a2 + ii_lea_sub 3,f3,a1_off(a7),a3 + ii_lea_sub 3,f4,a1_off(a7),a4 + ii_lea_sub 3,f5,a1_off(a7),a5 + ii_lea_sub 3,f6,a1_off(a7),a6 + ii_lea_sub 3,f7,a1_off(a7),usp + ii_lea_sub 5,f0,a2,a0_off(a7) + ii_lea_sub 5,f1,a2,a1_off(a7) + ii_lea_sub 5,f2,a2,a2 + ii_lea_sub 5,f3,a2,a3 + ii_lea_sub 5,f4,a2,a4 + ii_lea_sub 5,f5,a2,a5 + ii_lea_sub 5,f6,a2,a6 + ii_lea_sub 5,f7,a2,usp + ii_lea_sub 7,f0,a3,a0_off(a7) + ii_lea_sub 7,f1,a3,a1_off(a7) + ii_lea_sub 7,f2,a3,a2 + ii_lea_sub 7,f3,a3,a3 + ii_lea_sub 7,f4,a3,a4 + ii_lea_sub 7,f5,a3,a5 + ii_lea_sub 7,f6,a3,a6 + ii_lea_sub 7,f7,a3,usp + ii_lea_sub 9,f0,a4,a0_off(a7) + ii_lea_sub 9,f1,a4,a1_off(a7) + ii_lea_sub 9,f2,a4,a2 + ii_lea_sub 9,f3,a4,a3 + ii_lea_sub 9,f4,a4,a4 + ii_lea_sub 9,f5,a4,a5 + ii_lea_sub 9,f6,a4,a6 + ii_lea_sub 9,f7,a4,usp + ii_lea_sub b,f0,a5,a0_off(a7) + ii_lea_sub b,f1,a5,a1_off(a7) + ii_lea_sub b,f2,a5,a2 + ii_lea_sub b,f3,a5,a3 + ii_lea_sub b,f4,a5,a4 + ii_lea_sub b,f5,a5,a5 + ii_lea_sub b,f6,a5,a6 + ii_lea_sub b,f7,a6,usp + ii_lea_sub d,f0,a6,a0_off(a7) + ii_lea_sub d,f1,a6,a1_off(a7) + ii_lea_sub d,f2,a6,a2 + ii_lea_sub d,f3,a6,a3 + ii_lea_sub d,f4,a6,a4 + ii_lea_sub d,f5,a6,a5 + ii_lea_sub d,f6,a6,a6 + ii_lea_sub d,f7,a6,usp + ii_lea_sub f,f0,usp,a0_off(a7) + ii_lea_sub f,f1,usp,a1_off(a7) + ii_lea_sub f,f2,usp,a2 + ii_lea_sub f,f3,usp,a3 + ii_lea_sub f,f4,usp,a4 + ii_lea_sub f,f5,usp,a5 + ii_lea_sub f,f6,usp,a6 + ii_lea_sub f,f7,usp,usp +// lea d8(pc,dy.w),az + ii_lea_sub 1,fb,a0_off(a7),a0 + ii_lea_sub 3,fb,a1_off(a7),a0 + ii_lea_sub 5,fb,a2,a0 + ii_lea_sub 7,fb,a3,a0 + ii_lea_sub 9,fb,a4,a0 + ii_lea_sub b,fb,a5,a0 + ii_lea_sub d,fb,a6,a0 + ii_lea_sub f,fb,usp,a0 +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_macro.h b/BaS_GNU/sources/ii_macro.h new file mode 100644 index 0000000..5db7460 --- /dev/null +++ b/BaS_GNU/sources/ii_macro.h @@ -0,0 +1,144 @@ +/*******************************************************/ +// constanten +/*******************************************************/ +.extern ___RAMBAR1 +.extern _rt_cacr +.extern _rt_mod +.extern _rt_ssp +.extern _rt_usp +.extern _rt_vbr +.extern _d0_save +.extern _a7_save + +ii_ss = 16 +d0_off = 0 +d1_off = 4 +a0_off = 8 +a1_off = 12 +format_off = 16 +sr_off = 18 +ccr_off = 19 +pc_off = 20 + +#define table 0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle -> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle + +/*******************************************************/ +// allgemeine macros +/*******************************************************/ +ii_end: .macro + move.l a0,pc_off(a7) + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 + rte + .endm; + +set_cc0:.macro + move.w ccr,d0 + move.b d0,ccr_off(a7) + .endm; + +ii_esr: .macro // geht nicht!!?? + movem.l (a7),d0/d1/a0/a1 + lea ii_ss+8(a7),a7 // stack erhöhen + move.w d0,_d0_save // d0.w sicheren + move.w -6(a7),d0 // sr holen + move.w d0,sr // sr setzen + nop + move.w _d0_save,d0 // d0.w zurück + .endm; + +ii_end_mvm:.macro + move.l a0_off(a7),a0 + lea 16(a7),a7 + rte + .endm; + +ii_endj:.macro + movem.l (a7),d0/d1/a0/a1 // register zurück + lea ii_ss(a7),a7 // korr + rte // ende + .endm; + +set_nzvc:.macro // set ccr bits nzvc + move.w ccr,d1 + bclr #4,d1 + btst #4,ccr_off(a7) + beq snzvc2\@ + bset #4,d1 +snzvc2\@: + move.b d1,ccr_off(a7) + .endm; + +set_cc1:.macro + move.w ccr,d1 + move.b d1,ccr_off(a7) + .endm; + +set_cc_b:.macro + move.w ccr,d1 + btst #7,d0 // byt negativ? + beq set_cc_b2\@ + bset #3,d1 // make negativ +set_cc_b2\@: + move.b d1,ccr_off(a7) + .endm; + +set_cc_w:.macro + move.w ccr,d1 + btst #15,d0 // byt negativ? + beq set_cc_w2\@ + bset #3,d1 // make negativ +set_cc_w2\@: + move.b d1,ccr_off(a7) + .endm; + +get_pc: .macro + lea.l (a0),a1 + .endm; + +//-------------------------------------------------------------------- +ii_lset:.macro + lea table+\1*4,a0 + move.l #ii_\1,(a0) + .endm; +ii_lset_dx:.macro // 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 + ii_lset_dxg \1,\2 + ii_lset_dxu \1,\2 + .endm; +ii_lset_dxg:.macro // gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 + lea table+0x\10\2*4,a0 + move.l #ii_0x\10\2,(a0) + lea 0x800(a0),a0 // 4 * 0x200 + move.l #ii_0x\12\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\14\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\16\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\18\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1a\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1c\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1e\2,(a0) + .endm; +ii_lset_dxu:.macro // ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40 + lea table+0x\11\2*4,a0 + move.l #ii_0x\11\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\13\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\15\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\17\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\19\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1b\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1d\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1f\2,(a0) + .endm; + diff --git a/BaS_GNU/sources/ii_move.h b/BaS_GNU/sources/ii_move.h new file mode 100644 index 0000000..1ae8213 --- /dev/null +++ b/BaS_GNU/sources/ii_move.h @@ -0,0 +1,1271 @@ +//------------------------------------------------------------------- +// move +//------------------------------------------------------------------- +.extern ewf + +.text +ii_move_lset:.macro +//------------------------------------------------------------------------- +// 0x1000 move.b +//------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 11,e +// move.x d16(ax),xxx.l + ii_lset_opeau 13,e +// move.x d16(pc),xxx.w + ii_lset 0x11fa +// move.x d16(pc),xxx.l + ii_lset 0x13fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 1,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 1,79 +// move.x #xx,d16(ax) + ii_lset_dxu 1,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x11f8 +// move.x xxx.l,xxx.w + ii_lset 0x11f9 +// move.x xxx.w,xxx.l + ii_lset 0x13f8 +// move.x xxx.l,xxx.l + ii_lset 0x13f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x11fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x13fc +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 11,8 + ii_lset_opeag 13,8 + ii_lset_opeag 15,8 + ii_lset_opeag 17,8 + ii_lset_opeag 19,8 + ii_lset_opeag 1b,8 + ii_lset_opeag 1d,8 + ii_lset_opeag 1f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 11,9 + ii_lset_opea 13,9 + ii_lset_opea 15,9 + ii_lset_opea 17,9 + ii_lset_opea 19,9 + ii_lset_opea 1b,9 + ii_lset_opea 1d,9 + ii_lset_opea 1f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 11,a + ii_lset_opeag 13,a + ii_lset_opeag 15,a + ii_lset_opeag 17,a + ii_lset_opeag 19,a + ii_lset_opeag 1b,a + ii_lset_opeag 1d,a + ii_lset_opeag 1f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) + ii_lset_opeag 17,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 17,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 17,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 10,3 + ii_lset_opeag 12,3 + ii_lset_opeag 14,3 + ii_lset_opeag 16,3 + ii_lset_opeag 18,3 + ii_lset_opeag 1a,3 + ii_lset_opeag 1c,3 + ii_lset_opeag 1e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 10,7 + ii_lset_opeag 12,7 + ii_lset_opeag 14,7 + ii_lset_opeag 16,7 + ii_lset_opeag 18,7 + ii_lset_opeag 1a,7 + ii_lset_opeag 1c,7 + ii_lset_opeag 1e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 10,b + ii_lset_opeag 12,b + ii_lset_opeag 14,b + ii_lset_opeag 16,b + ii_lset_opeag 18,b + ii_lset_opeag 1a,b + ii_lset_opeag 1c,b + ii_lset_opeag 1e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 10,f + ii_lset_opeag 12,f + ii_lset_opeag 14,f + ii_lset_opeag 16,f + ii_lset_opeag 18,f + ii_lset_opeag 1a,f + ii_lset_opeag 1c,f + ii_lset_opeag 1e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 11,3 + ii_lset_opeag 13,3 + ii_lset_opeag 15,3 + ii_lset_opeag 17,3 + ii_lset_opeag 19,3 + ii_lset_opeag 1b,3 + ii_lset_opeag 1d,3 + ii_lset_opeag 1f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 1,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 1,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 1,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 1,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 1,3b +//------------------------------------------------------------------------- +// 0x2000 move.l +//------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 21,e +// move.x d16(ax),xxx.l + ii_lset_opeau 23,e +// move.x d16(pc),xxx.w + ii_lset 0x21fa +// move.x d16(pc),xxx.l + ii_lset 0x23fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 2,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 2,79 +// move.x #xx,d16(ax) + ii_lset_dxu 2,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x21f8 +// move.x xxx.l,xxx.w + ii_lset 0x21f9 +// move.x xxx.w,xxx.l + ii_lset 0x23f8 +// move.x xxx.l,xxx.l + ii_lset 0x23f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x21fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x23fc +// move.x ea,d8(ax,dy) ------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 21,8 + ii_lset_opeag 23,8 + ii_lset_opeag 25,8 + ii_lset_opeag 27,8 + ii_lset_opeag 29,8 + ii_lset_opeag 2b,8 + ii_lset_opeag 2d,8 + ii_lset_opeag 2f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 21,9 + ii_lset_opea 23,9 + ii_lset_opea 25,9 + ii_lset_opea 27,9 + ii_lset_opea 29,9 + ii_lset_opea 2b,9 + ii_lset_opea 2d,9 + ii_lset_opea 2f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 21,a + ii_lset_opeag 23,a + ii_lset_opeag 25,a + ii_lset_opeag 27,a + ii_lset_opeag 29,a + ii_lset_opeag 2b,a + ii_lset_opeag 2d,a + ii_lset_opeag 2f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) +// move.x ax,d8(pc,dy) + ii_lset_opea 27,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 27,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 27,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 20,3 + ii_lset_opeag 22,3 + ii_lset_opeag 24,3 + ii_lset_opeag 26,3 + ii_lset_opeag 28,3 + ii_lset_opeag 2a,3 + ii_lset_opeag 2c,3 + ii_lset_opeag 2e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 20,7 + ii_lset_opeag 22,7 + ii_lset_opeag 24,7 + ii_lset_opeag 26,7 + ii_lset_opeag 28,7 + ii_lset_opeag 2a,7 + ii_lset_opeag 2c,7 + ii_lset_opeag 2e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 20,b + ii_lset_opeag 22,b + ii_lset_opeag 24,b + ii_lset_opeag 26,b + ii_lset_opeag 28,b + ii_lset_opeag 2a,b + ii_lset_opeag 2c,b + ii_lset_opeag 2e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 20,f + ii_lset_opeag 22,f + ii_lset_opeag 24,f + ii_lset_opeag 26,f + ii_lset_opeag 28,f + ii_lset_opeag 2a,f + ii_lset_opeag 2c,f + ii_lset_opeag 2e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 21,3 + ii_lset_opeag 23,3 + ii_lset_opeag 25,3 + ii_lset_opeag 27,3 + ii_lset_opeag 29,3 + ii_lset_opeag 2b,3 + ii_lset_opeag 2d,3 + ii_lset_opeag 2f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 2,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 2,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 2,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 2,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 2,3b +//------------------------------------------------------------------------- +// 0x3000 move.w +///------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 31,e +// move.x d16(ax),xxx.l + ii_lset_opeau 33,e +// move.x d16(pc),xxx.w + ii_lset 0x31fa +// move.x d16(pc),xxx.l + ii_lset 0x33fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 3,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 3,79 +// move.x #xx,d16(ax) + ii_lset_dxu 3,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x31f8 +// move.x xxx.l,xxx.w + ii_lset 0x31f9 +// move.x xxx.w,xxx.l + ii_lset 0x33f8 +// move.x xxx.l,xxx.l + ii_lset 0x33f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x31fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x33fc +// move.x ea,d8(ax,dy) ------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 31,8 + ii_lset_opeag 33,8 + ii_lset_opeag 35,8 + ii_lset_opeag 37,8 + ii_lset_opeag 39,8 + ii_lset_opeag 3b,8 + ii_lset_opeag 3d,8 + ii_lset_opeag 3f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 31,9 + ii_lset_opea 33,9 + ii_lset_opea 35,9 + ii_lset_opea 37,9 + ii_lset_opea 39,9 + ii_lset_opea 3b,9 + ii_lset_opea 3d,9 + ii_lset_opea 3f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 31,a + ii_lset_opeag 33,a + ii_lset_opeag 35,a + ii_lset_opeag 37,a + ii_lset_opeag 39,a + ii_lset_opeag 3b,a + ii_lset_opeag 3d,a + ii_lset_opeag 3f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) +// move.x ax,d8(pc,dy) + ii_lset_opea 37,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 37,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 37,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 30,3 + ii_lset_opeag 32,3 + ii_lset_opeag 34,3 + ii_lset_opeag 36,3 + ii_lset_opeag 38,3 + ii_lset_opeag 3a,3 + ii_lset_opeag 3c,3 + ii_lset_opeag 3e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 30,7 + ii_lset_opeag 32,7 + ii_lset_opeag 34,7 + ii_lset_opeag 36,7 + ii_lset_opeag 38,7 + ii_lset_opeag 3a,7 + ii_lset_opeag 3c,7 + ii_lset_opeag 3e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 30,b + ii_lset_opeag 32,b + ii_lset_opeag 34,b + ii_lset_opeag 36,b + ii_lset_opeag 38,b + ii_lset_opeag 3a,b + ii_lset_opeag 3c,b + ii_lset_opeag 3e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 30,f + ii_lset_opeag 32,f + ii_lset_opeag 34,f + ii_lset_opeag 36,f + ii_lset_opeag 38,f + ii_lset_opeag 3a,f + ii_lset_opeag 3c,f + ii_lset_opeag 3e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 31,3 + ii_lset_opeag 33,3 + ii_lset_opeag 35,3 + ii_lset_opeag 37,3 + ii_lset_opeag 39,3 + ii_lset_opeag 3b,3 + ii_lset_opeag 3d,3 + ii_lset_opeag 3f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 3,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 3,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 3,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 3,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 3,3b +.endm +//--------------------------------------------------------------------------------------------- +// function +//--------------------------------------------------------------------------------------------- +ii_move_op:.macro +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_move_d16ax_xxx 1e8,a0_off(a7),w + ii_move_d16ax_xxx 1e9,a1_off(a7),w + ii_move_d16ax_xxx 1ea,a2,w + ii_move_d16ax_xxx 1eb,a3,w + ii_move_d16ax_xxx 1ec,a4,w + ii_move_d16ax_xxx 1ed,a5,w + ii_move_d16ax_xxx 1ee,a6,w + ii_move_d16ax_xxx 1ef,usp,w +// move.x d16(ax),xxx.l + ii_move_d16ax_xxx 3e8,a0_off(a7),l + ii_move_d16ax_xxx 3e9,a1_off(a7),l + ii_move_d16ax_xxx 3ea,a2,l + ii_move_d16ax_xxx 3eb,a3,l + ii_move_d16ax_xxx 3ec,a4,l + ii_move_d16ax_xxx 3ed,a5,l + ii_move_d16ax_xxx 3ee,a6,l + ii_move_d16ax_xxx 3ef,usp,l +// move.x d16(pc),xxx.w + ii_move_d16ax_xxx 1fa,a0,w +// move.x d16(pc),xxx.l + ii_move_d16ax_xxx 3fa,a0,l +// move.x xxx.w,d16(ax) +// move.x xxx.l,d16(ax) +// move.x #xx,d16(ax) + ii_move_xxx_d16ax 1,a0_off(a7) + ii_move_xxx_d16ax 3,a1_off(a7) + ii_move_xxx_d16ax 5,a2 + ii_move_xxx_d16ax 7,a3 + ii_move_xxx_d16ax 9,a4 + ii_move_xxx_d16ax b,a5 + ii_move_xxx_d16ax d,a6 + ii_move_xxx_d16ax f,usp +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_move_xxx_xxx b,w,w,11f8 + ii_move_xxx_xxx l,w,w,21f8 + ii_move_xxx_xxx w,w,w,31f8 +// move.x xxx.l,xxx.w + ii_move_xxx_xxx b,l,w,11f9 + ii_move_xxx_xxx l,l,w,21f9 + ii_move_xxx_xxx w,l,w,31f9 +// move.x xxx.w,xxx.l + ii_move_xxx_xxx b,w,l,13f8 + ii_move_xxx_xxx l,w,l,23f8 + ii_move_xxx_xxx w,w,l,33f8 +// move.x xxx.l,xxx.l + ii_move_xxx_xxx b,l,l,13f9 + ii_move_xxx_xxx l,l,l,23f9 + ii_move_xxx_xxx w,l,l,33f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_move_im_xxx b,w,11fc + ii_move_im_xxx l,w,21fc + ii_move_im_xxx w,w,31fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_move_im_xxx b,l,13fc + ii_move_im_xxx l,l,23fc + ii_move_im_xxx w,l,33fc +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(ax/pc,dy) + ii_move_dxxia d0_off(a7),80,id,d,c0 + ii_move_dxxia d1_off(a7),81,id,d,c1 + ii_move_dxxia d2,82,d,d,c2 + ii_move_dxxia d3,83,d,d,c3 + ii_move_dxxia d4,84,d,d,c4 + ii_move_dxxia d5,85,d,d,c5 + ii_move_dxxia d6,86,d,d,c6 + ii_move_dxxia d7,87,d,d,c7 +// move.x ax,d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),88,id,d,c8 + ii_move_dxxia a1_off(a7),89,id,d,c9 + ii_move_dxxia a2,8a,d,da,ca + ii_move_dxxia a3,8b,d,da,cb + ii_move_dxxia a4,8c,d,da,cc + ii_move_dxxia a5,8d,d,da,cd + ii_move_dxxia a6,8e,d,da,ce + ii_move_dxxia a7,8f,a7,da,cf +// move.x (ax),d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),90,ia,d,d0 + ii_move_dxxia a1_off(a7),91,ia,d,d1 + ii_move_dxxia (a2),92,d,d,d2 + ii_move_dxxia (a3),93,d,d,d3 + ii_move_dxxia (a4),94,d,d,d4 + ii_move_dxxia (a5),95,d,d,d5 + ii_move_dxxia (a6),96,d,d,d6 + ii_move_dxxia (a7),97,a7,d,d7 +// move.x (ax)+,d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),98,iap,d,d8 + ii_move_dxxia a1_off(a7),99,iap,d,d9 + ii_move_dxxia (a2)+,9a,d,d,da + ii_move_dxxia (a3)+,9b,d,d,db + ii_move_dxxia (a4)+,9c,d,d,dc + ii_move_dxxia (a5)+,9d,d,d,dd + ii_move_dxxia (a6)+,9e,d,d,de + ii_move_dxxia (a7)+,9f,a7,d,df +// move.x -(ax),d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),a0,iam,d,e0 + ii_move_dxxia a1_off(a7),a1,iam,d,e1 + ii_move_dxxia -(a2),a2,d,d,e2 + ii_move_dxxia -(a3),a3,d,d,e3 + ii_move_dxxia -(a4),a4,d,d,e4 + ii_move_dxxia -(a5),a5,d,d,e5 + ii_move_dxxia -(a6),a6,d,d,e6 + ii_move_dxxia -(a7),a7,a7,d,e7 +//--------------------------------------------------------------------- +// move.x d8(ax/pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax/pc,dy),dz + ii_move_d8_dest d0,id,03,dx + ii_move_d8_dest d1,id,23,dx + ii_move_d8_dest d2,d,43,dx + ii_move_d8_dest d3,d,63,dx + ii_move_d8_dest d4,d,83,dx + ii_move_d8_dest d5,d,a3,dx + ii_move_d8_dest d6,d,c3,dx + ii_move_d8_dest d7,d,e3,dx +// move.x d8(ax/pc,dy),az + ii_move_d8_dest a0,id,07,ax + ii_move_d8_dest a1,id,27,ax + ii_move_d8_dest a2,d,47,ax + ii_move_d8_dest a3,d,67,ax + ii_move_d8_dest a4,d,87,ax + ii_move_d8_dest a5,d,a7,ax + ii_move_d8_dest a6,d,c7,ax + ii_move_d8_dest usp,id,e7,ax +// move.x d8(ax/pc,dy),(az) + ii_move_d8_dest a0_off(a7),id,0b,ia + ii_move_d8_dest a1_off(a7),id,2b,ia + ii_move_d8_dest (a2),d,4b,ia + ii_move_d8_dest (a3),d,6b,ia + ii_move_d8_dest (a4),d,8b,ia + ii_move_d8_dest (a5),d,ab,ia + ii_move_d8_dest (a6),d,cb,ia + ii_move_d8_dest usp,id,eb,ia +// move.x d8(ax/pc,dy),(az)+ + ii_move_d8_dest a0_off(a7),id,0f,iap + ii_move_d8_dest a1_off(a7),id,2f,iap + ii_move_d8_dest (a2)+,d,4f,iap + ii_move_d8_dest (a3)+,d,6f,iap + ii_move_d8_dest (a4)+,d,8f,iap + ii_move_d8_dest (a5)+,d,af,iap + ii_move_d8_dest (a6)+,d,cf,iap + ii_move_d8_dest usp,id,ef,iap +// move.x d8(ax/pc,dy),-(az) + ii_move_d8_dest a0_off(a7),id,13,iam + ii_move_d8_dest a1_off(a7),id,33,iam + ii_move_d8_dest -(a2),d,53,iam + ii_move_d8_dest -(a3),d,73,iam + ii_move_d8_dest -(a4),d,93,iam + ii_move_d8_dest -(a5),d,b3,iam + ii_move_d8_dest -(a6),d,d3,iam + ii_move_d8_dest usp,id,f3,iam +.endm //end function +//==================================================================== +// subs ---------------------------------------------------------- +//==================================================================== +// move.x d16(ax),xxx.w/l 1=code 2=adress register 3=dest adr size +ii_move_d16ax_xxx:.macro +ii_0x1\1: //byt: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.b (a1),d0 + move.\3 (a0)+,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x2\1: //long: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.l (a1),d0 + move.\3 (a0)+,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x3\1: //word: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.w (a1),d0 + move.\3 (a0)+,a1 + move.w d0,(a1) + set_cc0 + ii_end +.endm +//---------------------------------------- +// move.x xxx.w,d16(ax) +// move.x xxx.l,d16(ax) +// move.x #xx,d16(ax) +ii_move_xxx_d16ax:.macro //1=code 2=adress register +ii_0x1\178: //byt xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.b (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x1\179: //byt xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.b (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x1\17c: //byt #x +#ifdef halten_move + halt +#endif + mvs.b (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x2\178: //long xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.l (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x2\179: //long xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.l (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x2\17c: //long #x +#ifdef halten_move + halt +#endif + move.l (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end + ii_end +ii_0x3\178: //word xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.w (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +ii_0x3\179: //word xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.w (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +ii_0x3\17c: //word #x +#ifdef halten_move + halt +#endif + move.w (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +.endm +// move.x xxx,xxx +ii_move_xxx_xxx:.macro //1=size 2=size source adr 3=size dest adr 4=code +ii_0x\4: +#ifdef halten_move + halt +#endif + move.\2 (a0)+,a1 + move.\1 (a1),d0 + move.\3 (a0)+,d1 + move.\1 d0,(a1) + set_cc0 + ii_end +.endm +// move.x im,xxx +ii_move_im_xxx:.macro //1=size 2=size dest adr 3=code +ii_0x\3: +#ifdef halten_move + halt +#endif +.ifc 1,b + move.w (a0)+,d0 +.else + move.\1 (a0)+,d0 +.endif + move.\2 (a0)+,a1 + move.\1 d0,(a1) + set_cc0 + ii_end +.endm +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// ea=dx,ax,(ax),(ax)+,-(ax) +//--------------------------------------------------------------------- +ii_move_dxxia:.macro //1=source 2=code 1.stelle 3=code 2 letzte Stellen 4=art 5=code d8(pc,dy) +.ifc \3,id + ii_move_dxxi b,\1+3,1,\2,\3,\5 + ii_move_dxxi w,\1+2,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 +.else + .ifc \4,da + ii_move_dxxi w,\1,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 + .else + ii_move_dxxi b,\1,1,\2,\3,\5 + ii_move_dxxi w,\1,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 + .endif +.endif +.endm + +ii_move_dxxi:.macro +ii_0x\31\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + move_end \1,\2,\5 +ii_0x\33\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + move_end \1,\2,\5 +ii_0x\35\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a2,a1 + move_end \1,\2,\5 +ii_0x\37\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a3,a1 + move_end \1,\2,\5 +ii_0x\39\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a4,a1 + move_end \1,\2,\5 +ii_0x\3b\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a5,a1 + move_end \1,\2,\5 +ii_0x\3d\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a6,a1 + move_end \1,\2,\5 +ii_0x\3f\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l usp,a1 + move_end \1,\2,\5 +ii_0x\37\6: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a0,a1 + move_end \1,\2,\5 +.endm +//------------------------------------ +move_end:.macro + jsr ewf +.ifc 3,a7 + move.l a7,d1 // a7 sichern + move.l usp,a7 // a7 holen +.endif +.ifc 3,ia + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 (a2),(a1) + move.l d1,a2 // a2 zurück +.else + .ifc 3,iap + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 (a2)+,(a1) + .else + .ifc 3,iam + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 -(a2),(a1) + .else + move.\1 \2,(a1) + .endif + .endif +.endif +.ifc 3,a7 + movea.l a7,usp // a7 zurück + movea.l d1,a7 // a7 setzen +.endif + set_cc0 +.ifc 3,iap + move.l d1,a2 // a2 zurück +.endif +.ifc 3,iam + move.l d1,a2 // a2 zurück +.endif + ii_end +.endm +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) +//--------------------------------------------------------------------- + +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea --------------------------------------------- +//--------------------------------------------------------------------- +ii_move_d8_dest:.macro //1=dest 2=art 3=code 2.+3.stelle 4=art adresse +//byt +ii_0x1\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + moveb_a1_src\4 \1,\2 +ii_0x1\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + moveb_a1_src\4 \1,\2 +ii_0x1\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +//long +ii_0x2\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + movel_a1_src\4 \1,\2 +ii_0x2\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + movel_a1_src\4 \1,\2 +ii_0x2\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + movel_a1_src\4 \1,\2 +ii_0x2\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + movel_a1_src\4 \1,\2 +ii_0x2\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + movel_a1_src\4 \1,\2 +ii_0x2\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + movel_a1_src\4 \1,\2 +ii_0x2\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + movel_a1_src\4 \1,\2 +ii_0x2\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + movel_a1_src\4 \1,\2 +ii_0x2\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +//word +ii_0x3\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + movew_a1_src\4 \1,\2 +ii_0x3\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + movew_a1_src\4 \1,\2 +ii_0x3\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + movew_a1_src\4 \1,\2 +ii_0x3\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + movew_a1_src\4 \1,\2 +ii_0x3\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + movew_a1_src\4 \1,\2 +ii_0x3\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + movew_a1_src\4 \1,\2 +ii_0x3\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + movew_a1_src\4 \1,\2 +ii_0x3\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + movew_a1_src\4 \1,\2 +ii_0x3\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +.endm +//--------------------------------------------------------------------- +//dx +moveb_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.b (a1),\1_off+3(a7) +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.l (a1),\1_off(a7) +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.w (a1),\1_off+2(a7) +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// ax +moveb_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.w (a1),a1 + move.l a1,usp + .else + move.w (a1),\1_off+2(a7) + .endif +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.l (a1),a1 + move.l a1,usp + .else + move.l (a1),\1_off(a7) + .endif +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.w (a1),a1 + move.l a1,usp + .else + move.w (a1),\1_off+2(a7) + .endif +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// (ax) +moveb_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,(a1) +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,(a1) +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,(a1) +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// (ax)+ +moveb_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,(a1)+ + move.l a1,\1 +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,(a1)+ + move.l a1,\1 +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,(a1)+ + move.l a1,\1 +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// -(ax) +moveb_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,-(a1) + move.l a1,\1 +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,-(a1) + move.l a1,\1 +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,-(a1) + move.l a1,\1 +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm + +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea +//--------------------------------------------------------------------- + + + +/*============================================================ +// move.w dx,(a0,dx.w*SF) + ii_lset 0x3180 + ii_lset 0x3181 + ii_lset 0x3182 + ii_lset 0x3183 + ii_lset 0x3184 + ii_lset 0x3185 + ii_lset 0x3186 + ii_lset 0x3187 + +//-------------------------------------------------------------------- +// // move.w dx,d(ay,dz.w*sf) +//-------------------------------------------------------------------- +movew_ewfw:.macro + move.l \2,a1 + jsr ewf + move.w \1,(a1) + set_cc0 + ii_end + .endm +ii_0x3180: + movew_ewfw d0_off+2(a7),a0_off(a7) +ii_0x3181: + movew_ewfw d0_off+2(a7),a0_off(a7) +ii_0x3182: + movew_ewfw d2,a0_off(a7) +ii_0x3183: + movew_ewfw d3,a0_off(a7) +ii_0x3184: + movew_ewfw d4,a0_off(a7) +ii_0x3185: + movew_ewfw d5,a0_off(a7) +ii_0x3186: + movew_ewfw d6,a0_off(a7) +ii_0x3187: + movew_ewfw d7,a0_off(a7) diff --git a/BaS_GNU/sources/ii_movem.h b/BaS_GNU/sources/ii_movem.h new file mode 100644 index 0000000..5e8a470 --- /dev/null +++ b/BaS_GNU/sources/ii_movem.h @@ -0,0 +1,374 @@ +//***********************************************************************************/ +// movem +//***********************************************************************************/ +ii_movem_lset: .macro +// movem.l rx,xxx.L + ii_lset 0x48f9 +// movem.l xxx.L,rx + ii_lset 0x4cf9 +// movem.w rx,xxx.L + ii_lset 0x48b9 +// movem.w xxx.L,rx + ii_lset 0x4cb9 +// movem.l rx,-(ax) + ii_lset 0x48e0 + ii_lset 0x48e1 + ii_lset 0x48e2 + ii_lset 0x48e3 + ii_lset 0x48e4 + ii_lset 0x48e5 + ii_lset 0x48e6 + ii_lset 0x48e7 +// movem.l (ax)+,rx + ii_lset 0x4cd8 + ii_lset 0x4cd9 + ii_lset 0x4cda + ii_lset 0x4cdb + ii_lset 0x4cdc + ii_lset 0x4cdd + ii_lset 0x4cde + ii_lset 0x4cdf +.endm +//***********************************************************************************/ +ii_movem_func: .macro +//------------------------------------------------------------------- +// movem.l +//-------------------------------------------------------------------- +// movem.l (ax)+,reg +//-------------------------------------------------------------------- + .long 0 +az_reg_table: + .byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70 + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0 + .byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0 +//------------------------------------------------------------------------------- +ii_0x48e0: // movem.l reglist,-(a0) + mvm_mem_macro 0x48d0,a0_off(a7),2 +ii_0x48e1: // movem.l reglist,-(a1) + mvm_mem_macro 0x48d1,a1_off(a7),2 +ii_0x48e2: // movem.l reglist,-(a2) + mvm_mem_macro 0x48d2,a2,2 +ii_0x48e3: // movem.l reglist,-(a3) + mvm_mem_macro 0x48d3,a3,2 +ii_0x48e4: // movem.l reglist,-(a4) + mvm_mem_macro 0x48d4,a4,2 +ii_0x48e5: // movem.l reglist,-(a5) + mvm_mem_macro 0x48d5,a5,2 +ii_0x48e6: // movem.l reglist,-(a6) + mvm_mem_macro 0x48d6,a6,2 +ii_0x48e7: // movem.l reglist,-(a7) + mvm_mem_macro 0x48d7,usp,2 +//------------------------------------------------------------------------------- +ii_0x4cd8: // movem.l (a0)+,reglist + mvm_reg_macro 0x4cd0,0x41e8,2 +ii_0x4cd9: // movem.l (a1)+,reglist + mvm_reg_macro 0x4cd1,0x43e9,2 +ii_0x4cda: // movem.l (a2)+,reglist + mvm_reg_macro 0x4cd2,0x45ea,2 +ii_0x4cdb: // movem.l (a3)+,reglist + mvm_reg_macro 0x4cd3,0x47eb,2 +ii_0x4cdc: // movem.l (a4)+,reglist + mvm_reg_macro 0x4cd4,0x49ec,2 +ii_0x4cdd: // movem.l (a5)+,reglist + mvm_reg_macro 0x4cd5,0x4bed,2 +ii_0x4cde: // movem.l (a6)+,reglist + mvm_reg_macro 0x4cd6,0x4dee,2 +ii_0x4cdf: // movem.l (a7)+,reglist + mvm_reg_macro 0x4cd7,0x4fef,2 +//---------------------------------------------------------------------------- +ii_0x48f9: // movem.l reg,xxx.L +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro l +//--------------------------------------------------------------------------------------------- +ii_0x4cf9: // movem.l xxx.L,reg +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro l +//---------------------------------------------------------------------------- +ii_0x48b9: // movem.w reg,xxx.L +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro w +//--------------------------------------------------------------------------------------------- +ii_0x4cb9: // movem.w xxx.L,reg +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro w +.endm +//============================================================== +mvm_mem_macro:.macro +#ifdef halten_movem + halt +#endif + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lsl.l #\3,d1 // * anzahl byts pro wert + move.l \2,a1 + sub.l d1,a1 // ax-anzahl byts + move.l a1,\2 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x reg_list,-(a7) + move.w (a0)+,(a1)+ // register list + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte +.endm +//--------------------------------------------------------------------------------- +mvm_reg_macro:.macro +#ifdef halten_movem + halt +#endif + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x (ax),reg_list + move.w (a0)+,(a1)+ // register list + move.w #\2,(a1)+ // lea 0(ax),ax + lsl.l #\3,d1 // * anzahl byts pro wert + move.w d1,(a1)+ // offset von lea + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte +.endm +//--------------------------------------------------------------------------------- +movemrm_macro:.macro // in d0 register liste, in a1 zieladresse +#ifdef halten_movem + halt +#endif + tst.b d0 // datenregister zu verschieben? + bne mrm_dx\@ // ja-> + lsr.l #8,d0 // sonst zu addressregister + jmp mmrm_nd7\@ // -> +mrm_dx\@: + lsr.l #1,d0 + bcc mmrm_nd0\@ +.ifc 1,l + move.l d0_off(a7),(a1)+ +.else + move.w d0_off+2(a7),(a1)+ +.endif +mmrm_nd0\@: + lsr.l #1,d0 + bcc mmrm_nd1\@ +.ifc 1,l + move.l d1_off(a7),(a1)+ +.else + move.w d1_off+2(a7),(a1)+ +.endif +mmrm_nd1\@: + lsr.l #1,d0 + bcc mmrm_nd2\@ + move.\1 d2,(a1)+ +mmrm_nd2\@: + lsr.l #1,d0 + bcc mmrm_nd3\@ + move.\1 d3,(a1)+ +mmrm_nd3\@: + lsr.l #1,d0 + bcc mmrm_nd4\@ + move.\1 d4,(a1)+ +mmrm_nd4\@: + lsr.l #1,d0 + bcc mmrm_nd5\@ + move.\1 d5,(a1)+ +mmrm_nd5\@: + lsr.l #1,d0 + bcc mmrm_nd6\@ + move.l d6,(a1)+ +mmrm_nd6\@: + lsr.l #1,d0 + bcc mmrm_nd7\@ + move.\1 d7,(a1)+ +mmrm_nd7\@: + tst.b d0 // addressregister zu verschieben? + beq mmrm_na7\@ + lsr.l #1,d0 + bcc mmrm_na0\@ +.ifc 1,l + move.l a0_off(a7),(a1)+ +.else + move.w a0_off+2(a7),(a1)+ +.endif +mmrm_na0\@: + lsr.l #1,d0 + bcc mmrm_na1\@ +.ifc 1,l + move.l a1_off(a7),(a1)+ +.else + move.w a1_off+2(a7),(a1)+ +.endif +mmrm_na1\@: + lsr.l #1,d0 + bcc mmrm_na2\@ + move.\1 a2,(a1)+ +mmrm_na2\@: + lsr.l #1,d0 + bcc mmrm_na3\@ + move.\1 a3,(a1)+ +mmrm_na3\@: + lsr.l #1,d0 + bcc mmrm_na4\@ + move.\1 a4,(a1)+ +mmrm_na4\@: + lsr.l #1,d0 + bcc mmrm_na5\@ + move.\1 a5,(a1)+ +mmrm_na5\@: + lsr.l #1,d0 + bcc mmrm_na6\@ + move.\1 a6,(a1)+ +mmrm_na6\@: + lsr.l #1,d0 + bcc mmrm_na7\@ + move.l a0,d1 // sichern + move.l usp,a0 // ist ja usp + move.\1 a0,(a1)+ // nach a0 + move.l d1,a0 // pc zurück +mmrm_na7\@: + ii_end + .endm +//--------------------------------------------------------------------------------------------- +movemmr_macro:.macro // in d0 register liste, in a1 source adr +#ifdef halten_movem + halt +#endif + tst.b d0 // datenregister zu verschieben? + bne mmr_dx\@ // ja-> + lsr.l #8,d0 // sonst zu addressregister + bra mmmr_nd7\@ // -> +mmr_dx\@: + lsr.l #1,d0 + bcc mmmr_nd0\@ +.ifc 1,l + move.l (a1)+,d0_off(a7) +.else + move.w (a1)+,d0_off+2(a7) +.endif +mmmr_nd0\@: + lsr.l #1,d0 + bcc mmmr_nd1\@ +.ifc 1,l + move.l (a1)+,d1_off(a7) +.else + move.w (a1)+,d1_off+2(a7) +.endif +mmmr_nd1\@: + lsr.l #1,d0 + bcc mmmr_nd2\@ + move.\1 (a1)+,d2 +mmmr_nd2\@: + lsr.l #1,d0 + bcc mmmr_nd3\@ + move.\1 (a1)+,d3 +mmmr_nd3\@: + lsr.l #1,d0 + bcc mmmr_nd4\@ + move.\1 (a1)+,d4 +mmmr_nd4\@: + lsr.l #1,d0 + bcc mmmr_nd5\@ + move.\1 (a1)+,d5 +mmmr_nd5\@: + lsr.l #1,d0 + bcc mmmr_nd6\@ + move.\1 (a1)+,d6 +mmmr_nd6\@: + lsr.l #1,d0 + bcc mmmr_nd7\@ + move.\1 (a1)+,d7 +mmmr_nd7\@: + tst.b d0 // addressregister zu verschieben? + beq mmmr_na7\@ // nein-> + lsr.l #1,d0 + bcc mmmr_na0\@ +.ifc 1,l + move.l (a1)+,a0_off(a7) +.else + move.w (a1)+,a0_off+2(a7) +.endif +mmmr_na0\@: + lsr.l #1,d0 + bcc mmmr_na1\@ +.ifc 1,l + move.l (a1)+,a1_off(a7) +.else + move.w (a1)+,a1_off+2(a7) +.endif +mmmr_na1\@: + lsr.l #1,d0 + bcc mmmr_na2\@ + move.\1 (a1)+,a2 +mmmr_na2\@: + lsr.l #1,d0 + bcc mmmr_na3\@ + move.\1 (a1)+,a3 +mmmr_na3\@: + lsr.l #1,d0 + bcc mmmr_na4\@ + move.\1 (a1)+,a4 +mmmr_na4\@: + lsr.l #1,d0 + bcc mmmr_na5\@ + move.\1 (a1)+,a5 +mmmr_na5\@: + lsr.l #1,d0 + bcc mmmr_na6\@ + move.\1 (a1)+,a6 +mmmr_na6\@: + lsr.l #1,d0 + bcc mmmr_na7\@ + move.\1 (a1)+,a1 // nach a0 + move.l a1,usp // war ja usp +mmmr_na7\@: + ii_end + .endm diff --git a/BaS_GNU/sources/ii_movep.h b/BaS_GNU/sources/ii_movep.h new file mode 100644 index 0000000..830fdf7 --- /dev/null +++ b/BaS_GNU/sources/ii_movep.h @@ -0,0 +1,179 @@ +//-------------------------------------------------------------------- +// movep +//-------------------------------------------------------------------- +.text +ii_movep_lset:.macro + ii_lset_opeau 01,0 //movep.w d(a0-7),d0 + ii_lset_opeau 03,0 //movep.w d(a0-7),d1 + ii_lset_opeau 05,0 //movep.w d(a0-7),d2 + ii_lset_opeau 07,0 //movep.w d(a0-7),d3 + ii_lset_opeau 09,0 //movep.w d(a0-7),d4 + ii_lset_opeau 0b,0 //movep.w d(a0-7),d5 + ii_lset_opeau 0d,0 //movep.w d(a0-7),d6 + ii_lset_opeau 0f,0 //movep.w d(a0-7),d7 + + ii_lset_opeau 01,4 //movep.w d0,d(a0-7) + ii_lset_opeau 03,4 //movep.w d1,d(a0-7) + ii_lset_opeau 05,4 //movep.w d2,d(a0-7) + ii_lset_opeau 07,4 //movep.w d3,d(a0-7) + ii_lset_opeau 09,4 //movep.w d4,d(a0-7) + ii_lset_opeau 0b,4 //movep.w d5,d(a0-7) + ii_lset_opeau 0d,4 //movep.w d6,d(a0-7) + ii_lset_opeau 0f,4 //movep.w d7,d(a0-7) + + ii_lset_opeau 01,8 //movep.l d(a0-7),d0 + ii_lset_opeau 03,8 //movep.l d(a0-7),d1 + ii_lset_opeau 05,8 //movep.l d(a0-7),d2 + ii_lset_opeau 07,8 //movep.l d(a0-7),d3 + ii_lset_opeau 09,8 //movep.l d(a0-7),d4 + ii_lset_opeau 0b,8 //movep.l d(a0-7),d5 + ii_lset_opeau 0d,8 //movep.l d(a0-7),d6 + ii_lset_opeau 0f,8 //movep.l d(a0-7),d7 + + ii_lset_opeau 01,c //movep.l d0,d(a0-7) + ii_lset_opeau 03,c //movep.l d1,d(a0-7) + ii_lset_opeau 05,c //movep.l d2,d(a0-7) + ii_lset_opeau 07,c //movep.l d3,d(a0-7) + ii_lset_opeau 09,c //movep.l d4,d(a0-7) + ii_lset_opeau 0b,c //movep.l d5,d(a0-7) + ii_lset_opeau 0d,c //movep.l d6,d(a0-7) + ii_lset_opeau 0f,c //movep.l d7,d(a0-7) +.endm +//--------------------------------------------------------------------------------------------- +ii_movep_func:.macro +//movep.w d(a0-7),d0-7 + ii_movep 010,d0_off(a7),wad + ii_movep 030,d1_off(a7),wad + ii_movep 050,d2,wad + ii_movep 070,d3,wad + ii_movep 090,d4,wad + ii_movep 0b0,d5,wad + ii_movep 0d0,d6,wad + ii_movep 0f0,d7,wad +//movep.w d0-7,d(a0-7) + ii_movep 014,d0_off(a7),wda + ii_movep 034,d1_off(a7),wda + ii_movep 054,d2,wda + ii_movep 074,d3,wda + ii_movep 094,d4,wda + ii_movep 0b4,d5,wda + ii_movep 0d4,d6,wda + ii_movep 0f4,d7,wda +//movep.l d(a0-7),d0-7 + ii_movep 018,d0_off(a7),lad + ii_movep 038,d1_off(a7),lad + ii_movep 058,d2,lad + ii_movep 078,d3,lad + ii_movep 098,d4,lad + ii_movep 0b8,d5,lad + ii_movep 0d8,d6,lad + ii_movep 0f8,d7,lad +//movep.l d0-7,d(a0-7) + ii_movep 01c,d0_off(a7),lda + ii_movep 03c,d1_off(a7),lda + ii_movep 05c,d2,lda + ii_movep 07c,d3,lda + ii_movep 09c,d4,lda + ii_movep 0bc,d5,lda + ii_movep 0dc,d6,lda + ii_movep 0fc,d7,lda +.endm +//--------------------------------------------------------------------------------------------- +ii_movep:.macro //1=code ziffer 1-3 2=register 3=art +ii_0x\18: +#ifdef halten_movep + halt +#endif + move.l a0_off(a7),a1 + ii_movep\3_up1 \2 +ii_0x\19: +#ifdef halten_movep + halt +#endif + move.l a1_off(a7),a1 + ii_movep\3_up1 \2 +ii_0x\1a: +#ifdef halten_movep + halt +#endif + move.l a2,a1 + ii_movep\3_up1 \2 +ii_0x\1b: +#ifdef halten_movep + halt +#endif + move.l a3,a1 + ii_movep\3_up1 \2 +ii_0x\1c: +#ifdef halten_movep + halt +#endif + move.l a4,a1 + ii_movep\3_up1 \2 +ii_0x\1d: +#ifdef halten_movep + halt +#endif + move.l a5,a1 + ii_movep\3_up1 \2 +ii_0x\1e: +#ifdef halten_movep + halt +#endif + move.l a6,a1 + ii_movep\3_up1 \2 +ii_0x\1f: +#ifdef halten_movep + halt +#endif + move.l usp,a1 + ii_movep\3_up1 \2 +.endm + +ii_movepwad_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.b (a1),d0 + lsl.l #8,d0 + move.b 2(a1,d1.l),d0 + move.w d0,\1 + ii_end +.endm + +ii_movepwda_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.w \1,d0 + move.b d0,2(a1) + lsr.l #8,d0 + move.b d0,(a1) + ii_end +.endm + +ii_moveplad_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.b (a1),d0 + lsl.l #8,d0 + move.b 2(a1),d0 + lsl.l #8,d0 + move.b 4(a1),d0 + lsl.l #8,d0 + move.b 6(a1),d0 + move.l d0,\1 + ii_end +.endm + +ii_moveplda_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.l \1,d0 + move.b d0,6(a1) + lsr.l #8,d0 + move.b d0,4(a1) + lsr.l #8,d0 + move.b d0,2(a1) + lsr.l #8,d0 + move.b d0,(a1) + ii_end +.endm diff --git a/BaS_GNU/sources/ii_op.h b/BaS_GNU/sources/ii_op.h new file mode 100644 index 0000000..a3fc0cf --- /dev/null +++ b/BaS_GNU/sources/ii_op.h @@ -0,0 +1,661 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_lset_op:.macro +//byt + ii_lset_opea \1,0 // dx,ax + ii_lset_opea \1,1 // (ax), (ax)+ + ii_lset_opea \1,2 // -(ax),d16(ax) + ii_lset_opeag \1,3 // d8(ax,dy) + lea table+0x\1\238*4,a0 + move.l #ii_0x\138,(a0)+ // xxx.w + move.l #ii_0x\139,(a0)+ // xxx.l +//word + ii_lset_opea \1,4 // dx,ax + ii_lset_opea \1,5 // (ax), (ax)+ + ii_lset_opea \1,6 // -(ax),d16(ax) + ii_lset_opeag \1,7 // d8(ax,dy) + lea table+0x\178*4,a0 + move.l #ii_0x\178,(a0)+ // xxx.w + move.l #ii_0x\179,(a0)+ // xxx.l +//long + ii_lset_opea \1,8 // dx,ax + ii_lset_opea \1,9 // (ax), (ax)+ + ii_lset_opea \1,a // -(ax),d16(ax) + ii_lset_opeag \1,b // d8(ax,dy) + lea table+0x\1b8*4,a0 + move.l #ii_0x\1b8,(a0)+ // xxx.w + move.l #ii_0x\1b9,(a0)+ // xxx.l + .endm + +ii_lset_opeag:.macro // 0x1120-0x1127 + lea table+0x\1\20*4,a0 + move.l #ii_0x\1\20,(a0)+ + move.l #ii_0x\1\21,(a0)+ + move.l #ii_0x\1\22,(a0)+ + move.l #ii_0x\1\23,(a0)+ + move.l #ii_0x\1\24,(a0)+ + move.l #ii_0x\1\25,(a0)+ + move.l #ii_0x\1\26,(a0)+ + move.l #ii_0x\1\27,(a0)+ + .endm; + +ii_lset_opeau:.macro // 0x1128-0x112f + lea table+0x\1\28*4,a0 + move.l #ii_0x\1\28,(a0)+ + move.l #ii_0x\1\29,(a0)+ + move.l #ii_0x\1\2a,(a0)+ + move.l #ii_0x\1\2b,(a0)+ + move.l #ii_0x\1\2c,(a0)+ + move.l #ii_0x\1\2d,(a0)+ + move.l #ii_0x\1\2e,(a0)+ + move.l #ii_0x\1\2f,(a0)+ + .endm; + +ii_lset_opea:.macro + ii_lset_opeag \1,\2 + ii_lset_opeau \1,\2 + .endm +/******************************************************/ +ii_op:.macro // 1=code 2=operation 3 = normal oder immediat/quick +// byt + opdx \1,\2,b,0,\3 // dx,ax + opia \1,\2,b,1,\3 // (ax),(ax)+ + opdia \1,\2,b,2,\3 // -(ax),d16(ax) + opd8a \1,\2,b,3,\3 // d8(ax),xxx +// word + opdx \1,\2,w,4,\3 // dx,ax + opia \1,\2,w,5,\3 // (ax),(ax)+ + opdia \1,\2,w,6,\3 // -(ax),d16(ax) + opd8a \1,\2,w,7,\3 // d8(ax),xxx +// long + opdx \1,\2,l,8,\3 // dx,ax + opia \1,\2,l,9,\3 // (ax),(ax)+ + opdia \1,\2,l,a,\3 // -(ax),d16(ax) + opd8a \1,\2,l,b,\3 // d8(ax),xxx + .endm +/******************************************************/ +// byt word long +/******************************************************/ +opdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + .ifc \3,b + op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 + .else + op\5smd \2,d0_off(a7),d0_off(a7),\3 + .endif + .endif +ii_0x\1\41: + .ifc \3,b + op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 + .else + op\5smd \2,d1_off(a7),d1_off(a7),\3 + .endif +.endif +ii_0x\1\42: + op\5smd \2,d2,d2,\3 +ii_0x\1\43: + op\5smd \2,d3,d3,\3 +ii_0x\1\44: + op\5smd \2,d4,d4,\3 +ii_0x\1\45: + op\5smd \2,d5,d5,\3 +ii_0x\1\46: + op\5smd \2,d6,d6,\3 +ii_0x\1\47: + op\5smd \2,d7,d7,\3 +//ax +ii_0x\1\48: + opa\5smd \2,a0_off(a7),a0_off(a7),\3 +ii_0x\1\49: + opa\5smd \2,a1_off(a7),a1_off(a7),\3 +ii_0x\1\4a: + opa\5smd \2,a2,a2,\3 +ii_0x\1\4b: + opa\5smd \2,a3,a3,\3 +ii_0x\1\4c: + opa\5smd \2,a4,a4,\3 +ii_0x\1\4d: + opa\5smd \2,a5,a5,\3 +ii_0x\1\4e: + opa\5smd \2,a6,a6,\3 +ii_0x\1\4f: + opa\5smd \2,usp,usp,\3 +.endm; +//----------------------------------------------- +opia: .macro // (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +//(ax) +ii_0x\1\40: + op\5sia \2,a0_off(a7),(a1),(a1),\3 +ii_0x\1\41: + op\5sia \2,a1_off(a7),(a1),(a1),\3 +ii_0x\1\42: + op\5smd \2,(a2),(a2),\3 +ii_0x\1\43: + op\5smd \2,(a3),(a3),\3 +ii_0x\1\44: + op\5smd \2,(a4),(a4),\3 +ii_0x\1\45: + op\5smd \2,(a5),(a5),\3 +ii_0x\1\46: + op\5smd \2,(a6),(a6),\3 +ii_0x\1\47: + op\5sia \2,usp,(a1),(a1),\3 +//(ax)+ +ii_0x\1\48: + op\5sia \2,a0_off(a7),(a1),(a1)+,\3 +ii_0x\1\49: + op\5sia \2,a1_off(a7),(a1),(a1)+,\3 +ii_0x\1\4a: + op\5smd \2,(a2),(a2)+,\3 +ii_0x\1\4b: + op\5smd \2,(a3),(a3)+,\3 +ii_0x\1\4c: + op\5smd \2,(a4),(a4)+,\3 +ii_0x\1\4d: + op\5smd \2,(a5),(a5)+,\3 +ii_0x\1\4e: + op\5smd \2,(a6),(a6)+,\3 +ii_0x\1\4f: + op\5sia \2,usp,(a1),(a1)+,\3 +.endm; +//----------------------------------------------- +opdia: .macro // -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + op\5sia \2,a0_off(a7),-(a1),(a1),\3 +ii_0x\1\41: + op\5sia \2,a1_off(a7),-(a1),(a1),\3 +ii_0x\1\42: + op\5smd \2,-(a2),(a2),\3 +ii_0x\1\43: + op\5smd \2,-(a3),(a3),\3 +ii_0x\1\44: + op\5smd \2,-(a4),(a4),\3 +ii_0x\1\45: + op\5smd \2,-(a5),(a5),\3 +ii_0x\1\46: + op\5smd \2,-(a6),(a6),\3 +ii_0x\1\47: + op\5sia \2,usp,-(a1),(a1),\3 + +ii_0x\1\48: + op\5sd16a \2,a0_off(a7),\3 +ii_0x\1\49: + op\5sd16a \2,a1_off(a7),\3 +ii_0x\1\4a: + op\5sd16a \2,a2,\3 +ii_0x\1\4b: + op\5sd16a \2,a3,\3 +ii_0x\1\4c: + op\5sd16a \2,a4,\3 +ii_0x\1\4d: + op\5sd16a \2,a5,\3 +ii_0x\1\4e: + op\5sd16a \2,a6,\3 +ii_0x\1\4f: + op\5sd16a \2,usp,\3 +.endm; +//----------------------------------------------- +opd8a: .macro // d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + op\5sd8a \2,a0_off(a7),\3 +ii_0x\1\41: + op\5sd8a \2,a1_off(a7),\3 +ii_0x\1\42: + op\5sd8a \2,a2,\3 +ii_0x\1\43: + op\5sd8a \2,a3,\3 +ii_0x\1\44: + op\5sd8a \2,a4,\3 +ii_0x\1\45: + op\5sd8a \2,a5,\3 +ii_0x\1\46: + op\5sd8a \2,a6,\3 +ii_0x\1\47: + op\5sd8a \2,usp,\3 + +ii_0x\1\48: + op\5sxx \2,\3,w +ii_0x\1\49: + op\5sxx \2,\3,l +.endm; +//----------------------------------------------- +opnsmd:.macro // direct dx: 1=operation 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opansmd:.macro // direct ax: 1=operation 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d1 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end +.endm; + +opnsia:.macro // indirect: 1=operation 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opnsd16a:.macro // indirect: 1=operation 2=adress register 3=size +#ifdef halten_op + halt +#endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opnsd8a:.macro // indirect: 1=operation 2=adress register 3=size +#ifdef halten_op + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opnsxx:.macro // indirect: 1=operation 2=size 3=size adresse +#ifdef halten_op + halt +#endif + +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif + move.\3 (a0)+,a1 + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; +//*******************************************************************************3 +opismd:.macro // immediate dx: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\4 d1,\3 +.endif + ii_end +.endm; + +opaismd:.macro // immediate ax: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d0,d1 +.ifnc \1,cmp.l +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif +.endif + ii_end +.endm; + +opisia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + +.ifc \5,l + move.l (a0)+,d0 +.else + .ifc \5,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\5 d1,\4 +.endif + ii_end +.endm; + +opisd16a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + +.ifc \3,l + move.l (a0)+,d0 +.else + .ifc \3,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\3 d1,(a1) +.endif + ii_end + .endm; + +opisd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + +.ifc \3,l + move.l (a0)+,d0 +.else + .ifc \3,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\3 d1,(a1) +.endif + ii_end + .endm; + +opisxx:.macro // immediate: 1=opieration 2=size 3=size adresse +.ifc \2,l + move.l (a0)+,d0 +.else + .ifc \2,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\2 d1,(a1) +.endif + ii_end + .endm; +//*******************************************************************************3 +opqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opaqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 ,d1 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end + .endm; + +opqsia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opqsd16a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opqsd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opqsxx:.macro // quick: 1=opieration 2=size 3=size adresse +#ifdef halten_op + halt +#endif + + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; diff --git a/BaS_GNU/sources/ii_opc.h b/BaS_GNU/sources/ii_opc.h new file mode 100644 index 0000000..8b887ce --- /dev/null +++ b/BaS_GNU/sources/ii_opc.h @@ -0,0 +1,263 @@ +/*****************************************************************************************/ +// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax +// zusammen mit op.h +/*****************************************************************************************/ +ii_lset_opc:.macro + ii_lset_opeag \1,c // dx,ax + ii_lset_opea \1,d // (ax), (ax)+ + ii_lset_opea \1,e // -(ax),d16(ax) + ii_lset_opeag \1,f // d8(ax,dy) + lea table+0x\1b8*4,a0 + move.l #ii_0x\1b8,(a0)+ // xxx.w + move.l #ii_0x\1b9,(a0)+ // xxx.l + .endm + +/******************************************************/ +ii_opc:.macro // 1=code 2=operation 3 = normal oder immediat + opcdx \1,\2,l,c,\3 // dx,ax + opia \1,\2,l,d,\3 // (ax),(ax)+ + opdia \1,\2,l,e,\3 // -(ax),d16(ax) + opd8a \1,\2,l,f,\3 // d8(ax),xxx + .endm +//*******************************************************************************3 +/******************************************************/ +// byt word long +/******************************************************/ +opcdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: +#ifdef halten_opc + halt +#endif + .ifc \3,b + op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 + .else + op\5smd \2,d0_off(a7),d0_off(a7),\3 + .endif + .endif +ii_0x\1\41: + .ifc \3,b + op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 + .else + op\5smd \2,d1_off(a7),d1_off(a7),\3 + .endif +.endif +ii_0x\1\42: + op\5smd \2,d2,d2,\3 +ii_0x\1\43: + op\5smd \2,d3,d3,\3 +ii_0x\1\44: + op\5smd \2,d4,d4,\3 +ii_0x\1\45: + op\5smd \2,d5,d5,\3 +ii_0x\1\46: + op\5smd \2,d6,d6,\3 +ii_0x\1\47: + op\5smd \2,d7,d7,\3 +.endm +//----------------------------------------------------- +opcsmd:.macro // dx: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opacsmd:.macro // ax: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d1 + set_cc0 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end + .endm; + +opcsia:.macro // (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opcsd16a:.macro // d16(ax): 1=opieration 2=adress register 3=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opcsd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opcsxx:.macro // indirect: 1=opieration 2=size 3=size adresse +#ifdef halten_opc + halt +#endif + +.ifc \2,l + move.l (a0)+,d0 +.else + .ifc \2,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; diff --git a/BaS_GNU/sources/ii_or.h b/BaS_GNU/sources/ii_or.h new file mode 100644 index 0000000..dfe4450 --- /dev/null +++ b/BaS_GNU/sources/ii_or.h @@ -0,0 +1,442 @@ +//-------------------------------------------------------------------- +// or +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// or.b #im,dx +//-------------------------------------------------------------------- +orbir_macro:.macro +#ifdef halten_or + halt +#endif + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + or.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea,dx +//-------------------------------------------------------------------- +ordd:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +orddd:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or (ea)->dy,dx +//-------------------------------------------------------------------- +ordda:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +orddai:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea->ay,-(ay),dx +//-------------------------------------------------------------------- +orddad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d16(ay),dx +//-------------------------------------------------------------------- +ord16ad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d8(ay,dy),dx +//-------------------------------------------------------------------- +ord8ad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or xxx.w,dx +//-------------------------------------------------------------------- +orxwd:.macro +#ifdef halten_or + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or xxx.l,dx +//-------------------------------------------------------------------- +orxld:.macro +#ifdef halten_or + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d16(pc),dx +//-------------------------------------------------------------------- +ord16pcd:.macro + halt + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d8(pc,dy),dx +//-------------------------------------------------------------------- +ord8pcd:.macro +#ifdef halten_or + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// or dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // or (ea)->dy,dx +//-------------------------------------------------------------------- +oreda:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +oredai:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +oredaid:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +oredad:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +oredadd:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,d16(ay) +//-------------------------------------------------------------------- +ore16ad:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or.w dx,d8(ay,dy) +//-------------------------------------------------------------------- +ore8ad:.macro +#ifdef halten_or + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,xxx.w +//-------------------------------------------------------------------- +orxwe:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,xxx.l +//-------------------------------------------------------------------- +orxle:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // ora.w ea,ax +//-------------------------------------------------------------------- +oraw:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// or.w ea,usp +//-------------------------------------------------------------------- +orawa7:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w usp?,ax +//-------------------------------------------------------------------- +orawu:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w usp?,usp +//-------------------------------------------------------------------- +orawua7:.macro + orawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // ora.w d16(ay),ax +//-------------------------------------------------------------------- +orawd16a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d8(ay,dy),ax +//-------------------------------------------------------------------- +orawd8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w xxx.w,ax +//-------------------------------------------------------------------- +orawxwax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w xxx.l,ax +//-------------------------------------------------------------------- +orawxlax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d16(pc),ax +//-------------------------------------------------------------------- +orawd16pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d8(pc,dy),ax +//-------------------------------------------------------------------- +orawd8pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w #im,ax +//-------------------------------------------------------------------- +orawim:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.l d8(ay,dy),ax +//-------------------------------------------------------------------- +orald8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.l d8(pc,dy),ax +//-------------------------------------------------------------------- +orald8pcax:.macro + jmp ii_error + .endm; +//***************************************************************************************** +// spezial addx subx etc. +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +ordx:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +ordax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_pea.h b/BaS_GNU/sources/ii_pea.h new file mode 100644 index 0000000..69f69d0 --- /dev/null +++ b/BaS_GNU/sources/ii_pea.h @@ -0,0 +1,74 @@ +//-------------------------------------------------------------------- +// pea +//-------------------------------------------------------------------- +.text +ii_pea_lset:.macro + ii_lset_opeag 48,7 + ii_lset 0x487b +.endm +//--------------------------------------------------------------------------------------------- +ii_pea_func:.macro +ii_0x4870: +#ifdef halten_pea + halt +#endif + move.l a0_off(a7),a1 + pea_macro +ii_0x4871: +#ifdef halten_pea + halt +#endif + move.l a1_off(a7),a1 + pea_macro +ii_0x4872: +#ifdef halten_pea + halt +#endif + move.l a2,a1 + pea_macro +ii_0x4873: +#ifdef halten_pea + halt +#endif + move.l a3,a1 + pea_macro +ii_0x4874: +#ifdef halten_pea + halt +#endif + move.l a4,a1 + pea_macro +ii_0x4875: +#ifdef halten_pea + halt +#endif + move.l a5,a1 + pea_macro +ii_0x4876: +#ifdef halten_pea + halt +#endif + move.l a6,a1 + pea_macro +ii_0x4877: +#ifdef halten_pea + halt +#endif + move.l usp,a1 + pea_macro +ii_0x487b: +#ifdef halten_pea + halt +#endif + move.l a0,a1 + pea_macro +.endm +//--------------------------------------------------------------------------------------------- +pea_macro:.macro + jsr ewf + move.l (a1),d0 + move.l usp,a1 + move.l d0,-(a1) + move.l a1,usp + ii_end +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_shd.h b/BaS_GNU/sources/ii_shd.h new file mode 100644 index 0000000..ecace29 --- /dev/null +++ b/BaS_GNU/sources/ii_shd.h @@ -0,0 +1,247 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_lset_shd:.macro + ii_lset_shdx e0 //r d0 + ii_lset_shdx e2 //r d1 + ii_lset_shdx e4 //r d2 + ii_lset_shdx e6 //r d3 + ii_lset_shdx e8 //r d4 + ii_lset_shdx ea //r d5 + ii_lset_shdx ec //r d6 + ii_lset_shdx ee //r d7 + + ii_lset_shdx e1 //l d0 + ii_lset_shdx e3 //l d1 + ii_lset_shdx e4 //l d2 + ii_lset_shdx e5 //l d3 + ii_lset_shdx e9 //l d4 + ii_lset_shdx eb //l d5 + ii_lset_shdx ed //l d6 + ii_lset_shdx ef //l d7 + .endm + +ii_lset_shdx:.macro +//byt + ii_lset_opea \1,0 // as,ls #im,dx + ii_lset_opea \1,1 // rox,ro #im,dx + ii_lset_opea \1,2 // as,ls dy,dx + ii_lset_opea \1,3 // rox,ro dy,dx +//word + ii_lset_opea \1,4 // as,ls #im,dx + ii_lset_opea \1,5 // rox,ro #im,dx + ii_lset_opea \1,6 // as,ls dy,dx + ii_lset_opea \1,7 // rox,ro dy,dx +//long +// ii_lset_opea \1,8 // as,ls #im,dx -> vorhanden + ii_lset_opea \1,9 // rox,ro #im,dx +// ii_lset_opea \1,a // as,ls dy,dx -> vorhanden + ii_lset_opea \1,b // rox,ro dy,dx + .endm +/******************************************************/ +ii_shd:.macro // 1=code 2=operation 3 = normal, direct oder immediat +// byt + opdx \1,\2,b,0,\3 // dx +// word + opdx \1,\2,w,4,\3 // dx +// long + opdx \1,\2,l,8,\3 // dx + .endm +/******************************************************/ +// byt word long routinen +/******************************************************/ +sh_asr: .macro // asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvs.\4 \2,d1 + sh_shal \1,\2,\3,\4 + .endm + +sh_lsr: .macro // asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvz.\4 \2,d1 + sh_shal \1,\2,\3,\4 + .endm + +sh_shal:.macro + move.w \3,d0 + \1.l d0,d1 + set_cc0 + move.\4 d1,\2 + .endm + +sh_all: .macro // asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvz.\4 \2,d1 +.ifc \4,b + byterev.l d1 +.else + swap.w d1 +.endif + sh_asr \1,\2,\3,\4 + .endm + +sh_ror: .macro // ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + move.\4 \2,d1 / + move.w \3,d0 +.ifc \4,b + lsl.l #8,d1 + move.b \2,d1 + and.l #0x7,d0 + lsr.l d0,d1 +.else + .ifc \4,w + swap.w d1 + move.w \2,d1 + and.l #0xf,d0 + lsr.l d0,d1 + .else + and.l #0x1f,d0 + lsr.l d0,d1 + move.l d1,a1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsl.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + move.w ccr,d0 + and.l #1,d1 // ist auch carry bit + or.l d1,d0 + move.b d0,ccr_off(a7) + .endm + +sh_rol: .macro // rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + move.\4 \2,d1 + move.w \3,d0 +.ifc \4,b + lsl.l #8,d1 + move.b \2,d1 + and.l #0x7,d0 + lsl.l d0,d1 + lsr.l #8,d1 + moveq #7,d0 +.else + .ifc \4,w + swap.w d1 + move.w \2,d1 + and.l #0xf,d0 + lsr.l d0,d1 + swap.w d1 + moveq #15,d0 + .else + and.l #0x1f,d0 + lsl.l d0,d1 + move.l d1,a1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsr.l d0,d1 + add.l a1,d1 + moveq #31,d0 + .endif +.endif + move.\4 d1,\2 + lsr.l d0,d1 // carry bit schieben + move.w ccr,d0 + and.l #1,d1 + or.l d1,d0 + move.b d0,ccr_off(a7) + .endm + +sh_roxr: .macro // roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + clr.l d0 + addx.l d0,d0 +ifc \4,b + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + move.b \2,d1 + move.w \3,d0 + and.l #0x7,d0 + lsr.l d0,d1 + set_cc0 +else + .ifc \4,w + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + lsl.l #8,d1 + move.w \2,d1 + move.w \3,d0 + and.l #0xf,d0 + lsr.l d0,d1 + set_cc0 + .else + bitrev.l d0 + move.l \2,d1 + lsr.l #1,d1 + add.l d0,d1 + move.w \3,d0 + subq.l #1,d0 + and.l #0x1f,d0 + lsr.l d0,d1 + move.l d1,a1 + set_cc1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsl.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + .endm + +sh_roxl: .macro // roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + clr.l d0 + addx.l d0,d0 +ifc \4,b + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + move.b \2,d1 + lsl.l #8,d1 + lsl.l #7,d1 + move.w \3,d0 + and.l #0x7,d0 + lsl.l d0,d1 + set_cc0 + byterev.l d1 +else + .ifc \4,w + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + lsl.l #7,d1 + mvz.w \2,d0 + lsr.l #1,d0 + add.l d0,d1 + move.w \3,d0 + and.l #0xf,d0 + lsl.l d0,d1 + set_cc0 + swap.w d1 + .else + move.l \2,d1 + lsl.l #1,d1 + add.l d0,d1 + move.w \3,d0 + subq.l #1,d0 + and.l #0x1f,d0 + lsl.l d0,d1 + move.l d1,a1 + set_cc1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsr.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + .endm + + \ No newline at end of file diff --git a/BaS_GNU/sources/ii_shift.h b/BaS_GNU/sources/ii_shift.h new file mode 100644 index 0000000..f83bfcb --- /dev/null +++ b/BaS_GNU/sources/ii_shift.h @@ -0,0 +1,687 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_shift_lset:.macro +/******************************************************/ +// byt +/******************************************************/ +// asx.b #,dx + ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,01 + ii_lset_dx \1,02 + ii_lset_dx \1,03 + ii_lset_dx \1,04 + ii_lset_dx \1,05 + ii_lset_dx \1,06 + ii_lset_dx \1,07 +// lsx.b #,dx + ii_lset_dxu \1,08 + ii_lset_dxu \1,09 + ii_lset_dxu \1,0a + ii_lset_dxu \1,0b + ii_lset_dxu \1,0c + ii_lset_dxu \1,0d + ii_lset_dxu \1,0e + ii_lset_dxu \1,0f +// roxx.b #,dx + ii_lset_dx \1,10 + ii_lset_dx \1,11 + ii_lset_dx \1,12 + ii_lset_dx \1,13 + ii_lset_dx \1,14 + ii_lset_dx \1,15 + ii_lset_dx \1,16 + ii_lset_dx \1,17 +// rox.b #,dx + ii_lset_dx \1,18 + ii_lset_dx \1,19 + ii_lset_dx \1,1a + ii_lset_dx \1,1b + ii_lset_dx \1,1c + ii_lset_dx \1,1d + ii_lset_dx \1,1e + ii_lset_dx \1,1f +// asx.b dy,dx + ii_lset_dx \1,20 + ii_lset_dx \1,21 + ii_lset_dx \1,22 + ii_lset_dx \1,23 + ii_lset_dx \1,24 + ii_lset_dx \1,25 + ii_lset_dx \1,26 + ii_lset_dx \1,27 +// lsx.b dy,dx + ii_lset_dx \1,28 + ii_lset_dx \1,29 + ii_lset_dx \1,2a + ii_lset_dx \1,2b + ii_lset_dx \1,2c + ii_lset_dx \1,2d + ii_lset_dx \1,2e + ii_lset_dx \1,2f +// roxx.dy,dx + ii_lset_dx \1,30 + ii_lset_dx \1,31 + ii_lset_dx \1,32 + ii_lset_dx \1,33 + ii_lset_dx \1,34 + ii_lset_dx \1,35 + ii_lset_dx \1,36 + ii_lset_dx \1,37 +// rox.b dy,dx + ii_lset_dx \1,38 + ii_lset_dx \1,39 + ii_lset_dx \1,3a + ii_lset_dx \1,3b + ii_lset_dx \1,3c + ii_lset_dx \1,3d + ii_lset_dx \1,3e + ii_lset_dx \1,3f +/******************************************************/ +// word +/******************************************************/ +// asx.w #x,dx + ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,41 + ii_lset_dx \1,42 + ii_lset_dx \1,43 + ii_lset_dx \1,44 + ii_lset_dx \1,45 + ii_lset_dx \1,46 + ii_lset_dx \1,47 +// lsx.w #,dx + ii_lset_dx \1,48 + ii_lset_dx \1,49 + ii_lset_dx \1,4a + ii_lset_dx \1,4b + ii_lset_dx \1,4c + ii_lset_dx \1,4d + ii_lset_dx \1,4e + ii_lset_dx \1,4f +// roxx.w #,dx + ii_lset_dx \1,50 + ii_lset_dx \1,51 + ii_lset_dx \1,52 + ii_lset_dx \1,53 + ii_lset_dx \1,54 + ii_lset_dx \1,55 + ii_lset_dx \1,56 + ii_lset_dx \1,57 +// rox.w #xdx + ii_lset_dx \1,58 + ii_lset_dx \1,59 + ii_lset_dx \1,5a + ii_lset_dx \1,5b + ii_lset_dx \1,5c + ii_lset_dx \1,5d + ii_lset_dx \1,5e + ii_lset_dx \1,5f +// asx.w dy,dx + ii_lset_dx \1,60 + ii_lset_dx \1,61 + ii_lset_dx \1,62 + ii_lset_dx \1,63 + ii_lset_dx \1,64 + ii_lset_dx \1,65 + ii_lset_dx \1,66 + ii_lset_dx \1,67 +// lsx.w dy,dx + ii_lset_dx \1,68 + ii_lset_dx \1,69 + ii_lset_dx \1,6a + ii_lset_dx \1,6b + ii_lset_dx \1,6c + ii_lset_dx \1,6d + ii_lset_dx \1,6e + ii_lset_dx \1,6f +// roxx.w dy,dx + ii_lset_dx \1,70 + ii_lset_dx \1,71 + ii_lset_dx \1,72 + ii_lset_dx \1,73 + ii_lset_dx \1,74 + ii_lset_dx \1,75 + ii_lset_dx \1,76 + ii_lset_dx \1,77 +// rox.w dy,dx + ii_lset_dx \1,78 + ii_lset_dx \1,79 + ii_lset_dx \1,7a + ii_lset_dx \1,7b + ii_lset_dx \1,7c + ii_lset_dx \1,7d + ii_lset_dx \1,7e + ii_lset_dx \1,7f +/******************************************************/ +// long +/******************************************************/ +// roxx.l #,dx + ii_lset_dx \1,90 + ii_lset_dx \1,91 + ii_lset_dx \1,92 + ii_lset_dx \1,93 + ii_lset_dx \1,94 + ii_lset_dx \1,95 + ii_lset_dx \1,96 + ii_lset_dx \1,97 +// rox.l #xdx + ii_lset_dx \1,98 + ii_lset_dx \1,99 + ii_lset_dx \1,9a + ii_lset_dx \1,9b + ii_lset_dx \1,9c + ii_lset_dx \1,9d + ii_lset_dx \1,9e + ii_lset_dx \1,9f +// roxx.l dy,dx + ii_lset_dx \1,b0 + ii_lset_dx \1,b1 + ii_lset_dx \1,b2 + ii_lset_dx \1,b3 + ii_lset_dx \1,b4 + ii_lset_dx \1,b5 + ii_lset_dx \1,b6 + ii_lset_dx \1,b7 +// rox.l dy,dx + ii_lset_dx \1,b8 + ii_lset_dx \1,b9 + ii_lset_dx \1,ba + ii_lset_dx \1,bb + ii_lset_dx \1,bc + ii_lset_dx \1,bd + ii_lset_dx \1,be + ii_lset_dx \1,bf +//-------------------------------------------------------------------- +// asr.w ea + ii_lset_opea \10,d // (ax), (ax)+ + ii_lset_opea \10,e // -(ax),d16(ax) + ii_lset_opeag \10,f // d8(ax,dy) + lea table+0x\10\2f8*4,a0 + move.l #ii_0x\10f8,(a0)+ // xxx.w + move.l #ii_0x\10f9,(a0)+ // xxx.l +// asl.w ea + ii_lset_opea \11,d // (ax), (ax)+ + ii_lset_opea \11,e // -(ax),d16(ax) + ii_lset_opeag \11,f // d8(ax,dy) + lea table+0x\11\2f8*4,a0 + move.l #ii_0x\11f8,(a0)+ // xxx.w + move.l #ii_0x\11f9,(a0)+ // xxx.l +// lsr.w ea + ii_lset_opea \12,d // (ax), (ax)+ + ii_lset_opea \12,e // -(ax),d16(ax) + ii_lset_opeag \12,f // d8(ax,dy) + lea table+0x\12\2f8*4,a0 + move.l #ii_0x\12f8,(a0)+ // xxx.w + move.l #ii_0x\12f9,(a0)+ // xxx.l +// lsr.w ea + ii_lset_opea \13,d // (ax), (ax)+ + ii_lset_opea \13,e // -(ax),d16(ax) + ii_lset_opeag \13,f // d8(ax,dy) + lea table+0x\13\2f8*4,a0 + move.l #ii_0x\13f8,(a0)+ // xxx.w + move.l #ii_0x\13f9,(a0)+ // xxx.l +// roxr.w ea + ii_lset_opea \14,d // (ax), (ax)+ + ii_lset_opea \14,e // -(ax),d16(ax) + ii_lset_opeag \14,f // d8(ax,dy) + lea table+0x\14\2f8*4,a0 + move.l #ii_0x\14f8,(a0)+ // xxx.w + move.l #ii_0x\14f9,(a0)+ // xxx.l +// roxl.w ea + ii_lset_opea \15,e // (ax), (ax)+ + ii_lset_opea \15,e // -(ax),d16(ax) + ii_lset_opeag \15,f // d8(ax,dy) + lea table+0x\15\2f8*4,a0 + move.l #ii_0x\15f8,(a0)+ // xxx.w + move.l #ii_0x\15f9,(a0)+ // xxx.l +// ror.w ea + ii_lset_opea \16,d // (ax), (ax)+ + ii_lset_opea \16,e // -(ax),d16(ax) + ii_lset_opeag \16,f // d8(ax,dy) + lea table+0x\16\2f8*4,a0 + move.l #ii_0x\16f8,(a0)+ // xxx.w + move.l #ii_0x\16f9,(a0)+ // xxx.l +// rol.w ea + ii_lset_opea \17,d // (ax), (ax)+ + ii_lset_opea \17,e // -(ax),d16(ax) + ii_lset_opeag \17,f // d8(ax,dy) + lea table+0x\17\2f8*4,a0 + move.l #ii_0x\17f8,(a0)+ // xxx.w + move.l #ii_0x\17f9,(a0)+ // xxx.l +// ende +.endm; +/******************************************************/ +ii_shift_op:.macro // 1=code +//byt------------------------------- +//asx.b #x,dx + ii_shift_op2agb 0,as,a +//lsx.b #x,dx + ii_shift_op2aub 0,ls,a +//roxx.b #x,dx + ii_shift_op2agb 1,rox,a +//rox.b #x,dx + ii_shift_op2aub 1,ro,a +//asx.b dy,dx + ii_shift_op2agb 2,as,b +//lsx.b dy,dx + ii_shift_op2aub 2,ls,b +//roxx.b dy,dx + ii_shift_op2agb 3,rox,b +//rox.b dy,dx + ii_shift_op2aub 3,ro,b +// word --------------------------------------- +//asx.w #x,dx + ii_shift_op2agw 4,as,a +//lsx.w #x,dx + ii_shift_op2auw 4,ls,a +//roxx.w #x,dx + ii_shift_op2agw 5,rox,a +//rox.w #x,dx + ii_shift_op2auw 5,ro,a +//asx.w dy,dx + ii_shift_op2agw 6,as,b +//lsx.w dy,dx + ii_shift_op2auw 6,ls,b +//roxx.w dy,dx + ii_shift_op2agw 7,rox,b +//rox.w dy,dx + ii_shift_op2auw 7,ro,b +// long --------------------------------------- +//roxx.l #x,dx + ii_shift_op2agw 9,rox,a +//rox.l #x,dx + ii_shift_op2auw 9,ro,a +//roxx.l dy,dx + ii_shift_op2agw b,rox,b +//rox.l dy,dx + ii_shift_op2auw b,ro,b +// ea --------------------------------------- +//asr.w #1,ea + ii_shift_op2ea 0,asr +//asl.w #1,ea + ii_shift_op2ea 1,asl +//lsr.w #1,ea + ii_shift_op2ea 2,lsr, +//lsl.w #1,ea + ii_shift_op2ea 3,lsl +//roxr.w #1,ea + ii_shift_op2ea 4,roxr +//roxl.w #1,ea + ii_shift_op2ea 5,roxl +//ror.w #1,ea + ii_shift_op2ea 6,ror +//rol.w #1,ea + ii_shift_op2ea 7,rol +.endm +//byt ============================================ +ii_shift_op2agb:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3b \1,0,\2,d0_off+3(a7) + ii_shift_op1\3b \1,1,\2,d1_off+3(a7) + ii_shift_op1\3b \1,2,\2,d2 + ii_shift_op1\3b \1,3,\2,d3 + ii_shift_op1\3b \1,4,\2,d4 + ii_shift_op1\3b \1,5,\2,d5 + ii_shift_op1\3b \1,6,\2,d6 + ii_shift_op1\3b \1,7,\2,d7 +.endm + +ii_shift_op2aub:.macro //byt: 1=code 2=operation + ii_shift_op1\3b \1,8,\2,d0_off+3(a7) + ii_shift_op1\3b \1,9,\2,d1_off+3(a7) + ii_shift_op1\3b \1,a,\2,d2 + ii_shift_op1\3b \1,b,\2,d3 + ii_shift_op1\3b \1,c,\2,d4 + ii_shift_op1\3b \1,d,\2,d5 + ii_shift_op1\3b \1,e,\2,d6 + ii_shift_op1\3b \1,f,\2,d7 +.endm + +ii_shift_op1ab:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,b,\3r,#8,\4 + ii_shift_op0 2\1\2,b,\3r,#1,\4 + ii_shift_op0 4\1\2,b,\3r,#2,\4 + ii_shift_op0 6\1\2,b,\3r,#3,\4 + ii_shift_op0 8\1\2,b,\3r,#4,\4 + ii_shift_op0 a\1\2,b,\3r,#5,\4 + ii_shift_op0 c\1\2,b,\3r,#6,\4 + ii_shift_op0 e\1\2,b,\3r,#7,\4 + ii_shift_op0 1\1\2,b,\3l,#8,\4 + ii_shift_op0 3\1\2,b,\3l,#1,\4 + ii_shift_op0 5\1\2,b,\3l,#2,\4 + ii_shift_op0 7\1\2,b,\3l,#3,\4 + ii_shift_op0 9\1\2,b,\3l,#4,\4 + ii_shift_op0 b\1\2,b,\3l,#5,\4 + ii_shift_op0 d\1\2,b,\3l,#6,\4 + ii_shift_op0 f\1\2,b,\3l,#7,\4 +.endm + +ii_shift_op1bb:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,b,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,b,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,b,\3r,d2,\4 + ii_shift_op0 6\1\2,b,\3r,d3,\4 + ii_shift_op0 8\1\2,b,\3r,d4,\4 + ii_shift_op0 a\1\2,b,\3r,d5,\4 + ii_shift_op0 c\1\2,b,\3r,d6,\4 + ii_shift_op0 e\1\2,b,\3r,d7,\4 + ii_shift_op0b 1\1\2,b,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,b,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,b,\3l,d2,\4 + ii_shift_op0 7\1\2,b,\3l,d3,\4 + ii_shift_op0 9\1\2,b,\3l,d4,\4 + ii_shift_op0 b\1\2,b,\3l,d5,\4 + ii_shift_op0 d\1\2,b,\3l,d6,\4 + ii_shift_op0 f\1\2,b,\3l,d7,\4 +.endm +// word --------------------------------------- +ii_shift_op2agw:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3w \1,0,\2,d0_off+2(a7) + ii_shift_op1\3w \1,1,\2,d1_off+2(a7) + ii_shift_op1\3w \1,2,\2,d2 + ii_shift_op1\3w \1,3,\2,d3 + ii_shift_op1\3w \1,4,\2,d4 + ii_shift_op1\3w \1,5,\2,d5 + ii_shift_op1\3w \1,6,\2,d6 + ii_shift_op1\3w \1,7,\2,d7 +.endm + +ii_shift_op2auw:.macro //byt: 1=code 2=operation + ii_shift_op1\3w \1,8,\2,d0_off+2(a7) + ii_shift_op1\3w \1,9,\2,d1_off+2(a7) + ii_shift_op1\3w \1,a,\2,d2 + ii_shift_op1\3w \1,b,\2,d3 + ii_shift_op1\3w \1,c,\2,d4 + ii_shift_op1\3w \1,d,\2,d5 + ii_shift_op1\3w \1,e,\2,d6 + ii_shift_op1\3w \1,f,\2,d7 +.endm + +ii_shift_op1aw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,w,\3r,#8,\4 + ii_shift_op0 2\1\2,w,\3r,#1,\4 + ii_shift_op0 4\1\2,w,\3r,#2,\4 + ii_shift_op0 6\1\2,w,\3r,#3,\4 + ii_shift_op0 8\1\2,w,\3r,#4,\4 + ii_shift_op0 a\1\2,w,\3r,#5,\4 + ii_shift_op0 c\1\2,w,\3r,#6,\4 + ii_shift_op0 e\1\2,w,\3r,#7,\4 + ii_shift_op0 1\1\2,w,\3l,#8,\4 + ii_shift_op0 3\1\2,w,\3l,#1,\4 + ii_shift_op0 5\1\2,w,\3l,#2,\4 + ii_shift_op0 7\1\2,w,\3l,#3,\4 + ii_shift_op0 9\1\2,w,\3l,#4,\4 + ii_shift_op0 b\1\2,w,\3l,#5,\4 + ii_shift_op0 d\1\2,w,\3l,#6,\4 + ii_shift_op0 f\1\2,w,\3l,#7,\4 +.endm + +ii_shift_op1bw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,w,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,w,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,w,\3r,d2,\4 + ii_shift_op0 6\1\2,w,\3r,d3,\4 + ii_shift_op0 8\1\2,w,\3r,d4,\4 + ii_shift_op0 a\1\2,w,\3r,d5,\4 + ii_shift_op0 c\1\2,w,\3r,d6,\4 + ii_shift_op0 e\1\2,w,\3r,d7,\4 + ii_shift_op0b 1\1\2,w,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,w,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,w,\3l,d2,\4 + ii_shift_op0 7\1\2,w,\3l,d3,\4 + ii_shift_op0 9\1\2,w,\3l,d4,\4 + ii_shift_op0 b\1\2,w,\3l,d5,\4 + ii_shift_op0 d\1\2,w,\3l,d6,\4 + ii_shift_op0 f\1\2,w,\3l,d7,\4 +.endm +// long --------------------------------------- +ii_shift_op2agl:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3l \1,0,\2,d0_off(a7) + ii_shift_op1\3l \1,1,\2,d1_off(a7) + ii_shift_op1\3l \1,2,\2,d2 + ii_shift_op1\3l \1,3,\2,d3 + ii_shift_op1\3l \1,4,\2,d4 + ii_shift_op1\3l \1,5,\2,d5 + ii_shift_op1\3l \1,6,\2,d6 + ii_shift_op1\3l \1,7,\2,d7 +.endm + +ii_shift_op2aul:.macro //byt: 1=code 2=operation + ii_shift_op1\3l \1,8,\2,d0_off(a7) + ii_shift_op1\3l \1,9,\2,d1_off(a7) + ii_shift_op1\3l \1,a,\2,d2 + ii_shift_op1\3l \1,b,\2,d3 + ii_shift_op1\3l \1,c,\2,d4 + ii_shift_op1\3l \1,d,\2,d5 + ii_shift_op1\3l \1,e,\2,d6 + ii_shift_op1\3l \1,f,\2,d7 +.endm + +ii_shift_op1al:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,l,\3r,#8,\4 + ii_shift_op0 2\1\2,l,\3r,#1,\4 + ii_shift_op0 4\1\2,l,\3r,#2,\4 + ii_shift_op0 6\1\2,l,\3r,#3,\4 + ii_shift_op0 8\1\2,l,\3r,#4,\4 + ii_shift_op0 a\1\2,l,\3r,#5,\4 + ii_shift_op0 c\1\2,l,\3r,#6,\4 + ii_shift_op0 e\1\2,l,\3r,#7,\4 + ii_shift_op0 1\1\2,l,\3l,#8,\4 + ii_shift_op0 3\1\2,l,\3l,#1,\4 + ii_shift_op0 5\1\2,l,\3l,#2,\4 + ii_shift_op0 7\1\2,l,\3l,#3,\4 + ii_shift_op0 9\1\2,l,\3l,#4,\4 + ii_shift_op0 b\1\2,l,\3l,#5,\4 + ii_shift_op0 d\1\2,l,\3l,#6,\4 + ii_shift_op0 f\1\2,l,\3l,#7,\4 +.endm + +ii_shift_op1bl:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,l,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,l,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,l,\3r,d2,\4 + ii_shift_op0 6\1\2,l,\3r,d3,\4 + ii_shift_op0 8\1\2,l,\3r,d4,\4 + ii_shift_op0 a\1\2,l,\3r,d5,\4 + ii_shift_op0 c\1\2,l,\3r,d6,\4 + ii_shift_op0 e\1\2,l,\3r,d7,\4 + ii_shift_op0b 1\1\2,l,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,l,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,l,\3l,d2,\4 + ii_shift_op0 7\1\2,l,\3l,d3,\4 + ii_shift_op0 9\1\2,l,\3l,d4,\4 + ii_shift_op0 b\1\2,l,\3l,d5,\4 + ii_shift_op0 d\1\2,l,\3l,d6,\4 + ii_shift_op0 f\1\2,l,\3l,d7,\4 +.endm +// .word ea ============================================ +ii_shift_op2ea:.macro //1=code 2.ziffer 2=shiftart +// (a0) bis (a7) ---------------------------- +ii_0xe\1d0: + move.l a0_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d1: + move.l a1_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d2: + ii_shift_typ w,\2,#1,(a2),(a2). +ii_0xe\1d3: + ii_shift_typ w,\2,#1,(a3),(a3). +ii_0xe\1d4: + ii_shift_typ w,\2,#1,(a4),(a4). +ii_0xe\1d5: + ii_shift_typ w,\2,#1,(a5),(a5). +ii_0xe\1d6: + ii_shift_typ w,\2,#1,(a6),(a6). +ii_0xe\1d7: + move.l usp,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// (a0)+ bis (a7)+ ----------------------------- +ii_0xe\1d8: + move.l a0_off(a7),a1 + addq.l #2,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d9: + move.l a1_off(a7),a1 + addq.l #2,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1da: + ii_shift_typ w,\2,#1,(a2),(a2)+. +ii_0xe\1db: + ii_shift_typ w,\2,#1,(a3),(a3)+ +ii_0xe\1dc: + ii_shift_typ w,\2,#1,(a4),(a4)+ +ii_0xe\1dd: + ii_shift_typ w,\2,#1,(a5),(a5)+ +ii_0xe\1de: + ii_shift_typ w,\2,#1,(a6),(a6)+ +ii_0xe\1df: + move.l usp,a1 + addq.l #2,a1 + move.l a1,usp + subq.l #2,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// -(a0) bis -(a7) ----------------------------- +ii_0xe\1e0: + move.l a0_off(a7),a1 + subq.l #2,a1 + move.l a1,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e1: + move.l a1_off(a7),a1 + subq.l #2,a1 + move.l a1,a1_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e2: + ii_shift_typ w,\2,#1,-(a2),(a2). +ii_0xe\1e3: + ii_shift_typ w,\2,#1,-(a3),(a3) +ii_0xe\1e4: + ii_shift_typ w,\2,#1,-(a4),(a4) +ii_0xe\1e5: + ii_shift_typ w,\2,#1,-(a5),(a5) +ii_0xe\1e6: + ii_shift_typ w,\2,#1,-(a6),(a6) +ii_0xe\1e7: + move.l usp,a1 + subq.l #2,a1 + move.l a1,usp + ii_shift_typ w,\2,#1,(a1),(a1). +// d16(a0) bis d16(a7) ----------------------------- +ii_0xe\1e8: + move.w (a0)+,a1 + add.l a0_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e9: + move.w (a0)+,a1 + add.l a1_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1ea: + move.w (a0)+,a1 + add.l a2,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1eb: + move.w (a0)+,a1 + add.l a3,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ec: + move.w (a0)+,a1 + add.l a4,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ed: + move.w (a0)+,a1 + add.l a5,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ee: + move.w (a0)+,a1 + add.l a6,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ef: + mvs.w (a0)+,d0 + move.l usp,a1 + add.l d0,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// d8(a0,dy) bis d8(a7,dy) ----------------------------- +ii_0xe\1f0: + move.l a0_off(a0),a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f1: + move.l a1_off(a0),a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f2: + move.l a2,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f3: + move.l a3,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f4: + move.l a4,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f5: + move.l a5,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f6: + move.l a6,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f7: + move.l usp,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +// xxx.w xxx.l +ii_0xe\1f8: + move.w (a0)+,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f9: + move.l (a0)+,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +.endm +//============================================================================ +//subroutine +//------------------------------ +ii_shift_op0:.macro // shift: 1=code 2=size 3=shift art 4=shift wert 5=ea +ii_0xe\1: + ii_shift_typ \2,\3,\4,\5,\5 +.endm + +ii_shift_op0b:.macro // shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea +ii_0xe\1: + move.l \4,d0 + ii_shift_typ \2,\3,d0,\5,\5 +.endm + +ii_shift_typ:.macro //1=size 2=shift art 3=shift wert 4=source 5=dest +#ifdef halten + halt +#endif +.ifc asr,\2 + mvs.\1 \4,d1 +.else + mvz.\1 \4,d1 +.endif +.ifc roxr,\2 + nop +.else + .ifc roxl,\2 + nop + .else + .ifc ror,\2 + nop + .else + .ifc rol,\2 + nop + .else + \2.l \3,d1 + .endif + .endif + .endif +.endif + set_cc0 + move.\1 d1,\5 + ii_end +.endm diff --git a/BaS_GNU/sources/ii_sub.h b/BaS_GNU/sources/ii_sub.h new file mode 100644 index 0000000..1405e1a --- /dev/null +++ b/BaS_GNU/sources/ii_sub.h @@ -0,0 +1,584 @@ +//-------------------------------------------------------------------- +// sub +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// sub.b #im,dx +//-------------------------------------------------------------------- +subbir_macro:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + sub.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea,dx +//-------------------------------------------------------------------- +subdd:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +subddd:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub (ea)->dy,dx +//-------------------------------------------------------------------- +subdda:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +subddai:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea->ay,-(ay),dx +//-------------------------------------------------------------------- +subddad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d16(ay),dx +//-------------------------------------------------------------------- +subd16ad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d8(ay,dy),dx +//-------------------------------------------------------------------- +subd8ad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub xxx.w,dx +//-------------------------------------------------------------------- +subxwd:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub xxx.l,dx +//-------------------------------------------------------------------- +subxld:.macro +#ifdef halten_sub + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d16(pc),dx +//-------------------------------------------------------------------- +subd16pcd:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d8(pc,dy),dx +//-------------------------------------------------------------------- +subd8pcd:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// sub dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // sub (ea)->dy,dx +//-------------------------------------------------------------------- +subeda:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +subedai:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +subedaid:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +subedad:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +subedadd:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,d16(ay) +//-------------------------------------------------------------------- +sube16ad:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,d8(ay,dy) +//-------------------------------------------------------------------- +sube8ad:.macro +#ifdef halten_sub + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,xxx.w +//-------------------------------------------------------------------- +subxwe:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,xxx.l +//-------------------------------------------------------------------- +subxle:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// // suba.w ea,ax +//-------------------------------------------------------------------- +subaw:.macro +#ifdef halten_sub + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + mvs.w \1,d0 + suba.l d0,\2 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// sub.w ea,usp +//-------------------------------------------------------------------- +subawa7:.macro +#ifdef halten_sub + halt +#endif + mvs.w \1,d0 + move.l usp,a1 + sub.l d0,a1 + move.l a1,usp + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w usp?,ax +//-------------------------------------------------------------------- +subawu:.macro +#ifdef halten_sub + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + move.l a7,_a7_save + move.l usp,a7 + move.l \1,d0 + suba.l d0,\2 + move.l a7,usp + move.l _a7_save,a7 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// // suba.w usp?,usp +//-------------------------------------------------------------------- +subawua7:.macro + subawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // suba.w d16(ay),ax +//-------------------------------------------------------------------- +subawd16a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + adda.l d0,a1 + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d8(ay,dy),ax +//-------------------------------------------------------------------- +subawd8a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w xxx.w,ax +//-------------------------------------------------------------------- +subawxwax:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w xxx.l,ax +//-------------------------------------------------------------------- +subawxlax:.macro +#ifdef halten_sub + halt +#endif + move.l (a0)+,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d16(pc),ax +//-------------------------------------------------------------------- +subawd16pcax:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + adda.l a0,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d8(pc,dy),ax +//-------------------------------------------------------------------- +subawd8pcax:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w #im,ax +//-------------------------------------------------------------------- +subawim:.macro +#ifdef halten_sub + halt +#endif + mvs.w \1,d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.l d8(ay,dy),ax +//-------------------------------------------------------------------- +subald8a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.l d8(pc,dy),ax +//-------------------------------------------------------------------- +subakd8pcax:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//***************************************************************************************** +// subx +//***************************************************************************************** +//-------------------------------------------------------------------- +// // subx dy,dx +//-------------------------------------------------------------------- +subdx:.macro +#ifdef halten_sub + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + mvs.\3 \2,d0 + mvs.\3 \1,d1 + subx.l d0,d1 + set_cc0 + move.\3 d1,\1 + ii_end + .endm; +//-------------------------------------------------------------------- +// // subx -(ay),-(ax) +//-------------------------------------------------------------------- +subdax:.macro +#ifdef halten_sub + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + move.l \1,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d0 +.endif + move.l \2,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d1 +.endif + subx.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/illegal_instruction.s b/BaS_GNU/sources/illegal_instruction.s new file mode 100644 index 0000000..21461b3 --- /dev/null +++ b/BaS_GNU/sources/illegal_instruction.s @@ -0,0 +1,328 @@ +.public _illegal_instruction +.public _illegal_table_make + +.include "startcf.h" +.include "ii_macro.h" +.include "ii_func.h" +.include "ii_op.h" +.include "ii_opc.h" +.include "ii_add.h" +.include "ii_sub.h" +.include "ii_or.h" +.include "ii_and.h" +.include "ii_dbcc.h" +.include "ii_shd.h" +.include "ii_movem.h" +.include "ii_lea.h" +.include "ii_shift.h" +.include "ii_exg.h" +.include "ii_movep.h" +.include "ii_ewf.h" +.include "ii_move.h" + +.extern _ii_shift_vec +.extern ewf + +/*******************************************************/ +.text +ii_error: + nop + halt + nop + nop + +_illegal_instruction: +#ifdef ii_on + move.w #0x2700,sr + lea -ii_ss(a7),a7 + movem.l d0/d1/a0/a1,(a7) + move.l pc_off(a7),a0 // pc + mvz.w (a0)+,d0 // code + lea table,a1 + move.l 0(a1,d0*4),a1 + jmp (a1) +/*************************************************************************************************/ +#endif +_illegal_table_make: +#ifdef ii_on + lea table,a0 + moveq #0,d0 +_itm_loop: + move.l #ii_error,(a0)+ + addq.l #1,d0 + cmp.l #0xF000,d0 + bne _itm_loop +//------------------------------------------------------------------------- + ii_ewf_lset // diverse fehlende adressierungn +//------------------------------------------------------------------------- +// 0x0000 +// ori + ii_lset_op 00 +// andi + ii_lset_op 02 +// subi + ii_lset_op 04 +// addi + ii_lset_op 06 +// eori + ii_lset_op 0a +// cmpi + ii_lset_op 0c +// movep + ii_movep_lset +//------------------------------------------------------------------------- +// 0x1000 move.b +// 0x2000 move.l +// 0x3000 move.w + ii_move_lset +//------------------------------------------------------------------------- +// 0x4000 +//------------------------------------------------------------------------- +// negx + ii_lset_op 40 +// neg + ii_lset_op 44 +// not + ii_lset_op 46 +//--------------------------------------------------------------------------------------------- +// lea d8(ax,dy.w),az; d8(pc,dy.w),az +//------------------------------------------------------------------- + ii_lea_lset +//------------------------------------------------------------------- +// movem +//------------------------------------------------------------------- + ii_movem_lset +//------------------------------------------------------------------------- +// 0x5000 +//------------------------------------------------------------------------- +// addq, subq + ii_lset_op 50 + ii_lset_op 51 + ii_lset_op 52 + ii_lset_op 53 + ii_lset_op 54 + ii_lset_op 55 + ii_lset_op 56 + ii_lset_op 57 + ii_lset_op 58 + ii_lset_op 59 + ii_lset_op 5a + ii_lset_op 5b + ii_lset_op 5c + ii_lset_op 5d + ii_lset_op 5e + ii_lset_op 5f +// dbcc + ii_lset_dbcc +// scc + ii_lset_opc 50 + ii_lset_opc 51 + ii_lset_opc 52 + ii_lset_opc 53 + ii_lset_opc 54 + ii_lset_opc 55 + ii_lset_opc 56 + ii_lset_opc 57 + ii_lset_opc 58 + ii_lset_opc 59 + ii_lset_opc 5a + ii_lset_opc 5b + ii_lset_opc 5c + ii_lset_opc 5d + ii_lset_opc 5e + ii_lset_opc 5f +//------------------------------------------------------------------------- +// 0x8000 or +//------------------------------------------------------------------------- + ii_lset_func 8 +//------------------------------------------------------------------------- +// 0x9000 sub +//------------------------------------------------------------------------- + ii_lset_func 9 +//------------------------------------------------------------------------- +// 0xb000 +//------------------------------------------------------------------------- +// eor + ii_lset_op b1 + ii_lset_op b3 + ii_lset_op b5 + ii_lset_op b7 + ii_lset_op b9 + ii_lset_op bb + ii_lset_op bd + ii_lset_op bf +//------------------------------------------------------------------------- +// 0xc000 +//------------------------------------------------------------------------- +// and + ii_lset_func c +// exg + ii_exg_lset +//------------------------------------------------------------------------- +// 0xd000 add +//------------------------------------------------------------------------- + ii_lset_func d +//------------------------------------------------------------------------- +// 0xe000 +//------------------------------------------------------------------------- +// shift register + ii_shift_lset e +//------------------------------------------------- +// differenz zwischen orginal und gemoved korrigieren + lea ii_error(pc),a1 + move.l a1,d1 + sub.l #ii_error,d1 + lea table,a0 + moveq #0,d0 +_itkorr_loop: + add.l d1,(a0)+ + addq.l #1,d0 + cmp.l #0xF000,d0 + bne _itkorr_loop +#endif + rts +#ifdef ii_on +//***********************************************************************************/ +//------------------------------------------------------------------------- + ii_ewf_func // diverse fehlende adressierungn +//------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x0000 +//-------------------------------------------------------------------- +// ori 00 + ii_op 00,or.l,i +//-------------------------------------------------------------------- +// andi 02 + ii_op 02,and.l,i +//-------------------------------------------------------------------- +// subi 04 + ii_op 04,and.l,i +//-------------------------------------------------------------------- +// addi 06 + ii_op 06,add.l,i +//-------------------------------------------------------------------- +// eori 0a + ii_op 0a,eor.l,i +//-------------------------------------------------------------------- +// cmpi 0c + ii_op 0c,cmp.l,i +//-------------------------------------------------------------------- +// movep + ii_movep_func +///--------------------------------------------------------------------------------------------- +// 0x1000 move.b +// 0x2000 move.l +// 0x3000 move.w + ii_move_op +//--------------------------------------------------------------------------------------------- +// 0x4000 +//--------------------------------------------------------------------------------------------- +// neg 0x40.. + ii_op 40,negx.l,n +//--------------------------------------------------------------------------------------------- +// neg 0x44.. + ii_op 44,neg.l,n +//--------------------------------------------------------------------------------------------- +// not 0x46.. + ii_op 46,not.l,n +//--------------------------------------------------------------------------------------------- +// lea d8(ax,dy.w),az; d8(pc,dy.w),az +//------------------------------------------------------------------- + ii_lea_func +//------------------------------------------------------------------- +// movem +//-------------------------------------------------------------------- +ii_movem_func +//--------------------------------------------------------------------------------------------- +// 0x5000 +//--------------------------------------------------------------------------------------------- +//dbcc + ii_dbcc_func +// addq 0x5... + ii_op 50,addq.l #8,q + ii_op 52,addq.l #1,q + ii_op 54,addq.l #2,q + ii_op 56,addq.l #3,q + ii_op 58,addq.l #4,q + ii_op 5a,addq.l #5,q + ii_op 5c,addq.l #6,q + ii_op 5e,addq.l #7,q +//--------------------------------------------------------------------------------------------- +// subq 0x5... + ii_op 51,subq.l #8,q + ii_op 53,subq.l #1,q + ii_op 55,subq.l #2,q + ii_op 57,subq.l #3,q + ii_op 59,subq.l #4,q + ii_op 5b,subq.l #5,q + ii_op 5d,subq.l #6,q + ii_op 5f,subq.l #7,q +//--------------------------------------------------------------------------------------------- +// 0x5... scc + ii_opc 50,st,c + ii_opc 51,sf,c + ii_opc 52,shi,c + ii_opc 53,sls,c + ii_opc 54,scc,c + ii_opc 55,scs,c + ii_opc 56,sne,c + ii_opc 57,seq,c + ii_opc 58,svc,c + ii_opc 59,svs,c + ii_opc 5a,spl,c + ii_opc 5b,smi,c + ii_opc 5c,sge,c + ii_opc 5d,slt,c + ii_opc 5e,sgt,c + ii_opc 5f,sle,c +//--------------------------------------------------------------------------------------------- +// 0x6000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x7000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x8000 +//--------------------------------------------------------------------------------------------- +// or + ii_func 8,or +//--------------------------------------------------------------------------------------------- +// 0x9000 +//--------------------------------------------------------------------------------------------- +// sub + ii_func 9,sub +//--------------------------------------------------------------------------------------------- +// 0xa000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0xb000 +//--------------------------------------------------------------------------------------------- +// eor + ii_op b1,eor.l d0,q + ii_op b3,eor.l d1,q + ii_op b5,eor.l d2,q + ii_op b7,eor.l d3,q + ii_op b9,eor.l d4,q + ii_op bb,eor.l d5,q + ii_op bd,eor.l d6,q + ii_op bf,eor.l d7,q +//--------------------------------------------------------------------------------------------- +// 0xc000 +//--------------------------------------------------------------------------------------------- +// and + ii_func c,and +// exg + ii_exg_func +//--------------------------------------------------------------------------------------------- +// 0xd000 +//--------------------------------------------------------------------------------------------- +// add + ii_func d,add +//--------------------------------------------------------------------------------------------- +// 0xe000 shift +//-------------------------------------------------------------------- + ii_shift_op +//-------------------------------------------------------------------- +// 0xf000 +//-------------------------------------------------------------------- +#endif \ No newline at end of file diff --git a/BaS_GNU/sources/last.c b/BaS_GNU/sources/last.c new file mode 100644 index 0000000..0cb3a3e --- /dev/null +++ b/BaS_GNU/sources/last.c @@ -0,0 +1,11 @@ +// letztes file der liste +// wichtig als endpunkt des kopierens + +void copy_end(void) +{ + asm + { +copy_end: + nop + } +} \ No newline at end of file diff --git a/BaS_GNU/sources/last.s b/BaS_GNU/sources/last.s new file mode 100644 index 0000000..c9dfe7a --- /dev/null +++ b/BaS_GNU/sources/last.s @@ -0,0 +1,10 @@ +// letztes file der liste +// wichtig als endpunkt des kopierens + +.global copy_end + +.text + nop +copy_end: + nop +.asciz 'ende copy'; \ No newline at end of file diff --git a/BaS_GNU/sources/macro.h b/BaS_GNU/sources/macro.h new file mode 100644 index 0000000..2afa44e --- /dev/null +++ b/BaS_GNU/sources/macro.h @@ -0,0 +1,10 @@ +/*******************************************************/ +// allgemeine macros +/*******************************************************/ +.text +wait_pll: .macro +wait1_pll\@: + tst.w (a1) + bmi wait1_pll\@ + rts +.endm diff --git a/BaS_GNU/sources/mmu.s b/BaS_GNU/sources/mmu.s new file mode 100644 index 0000000..0d3fade --- /dev/null +++ b/BaS_GNU/sources/mmu.s @@ -0,0 +1,196 @@ +/********************************************************************/ + /* INIT ACR und MMU /* +/********************************************************************/ + +.include "startcf.h" + +.extern _rt_vbr +.extern _rt_cacr +.extern _rt_asid +.extern _rt_acr0 +.extern _rt_acr1 +.extern _rt_acr2 +.extern _rt_acr3 +.extern _rt_mmubar +.extern ___MMUBAR +.extern cpusha +.extern _video_tlb +.extern _video_sbt + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + +#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V) +#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) + +.public _mmu_init +.public _mmutr_miss + +.text +_mmu_init: + clr.l d0 + movec d0,ASID // ASID allways 0 + move.l d0,_rt_asid // sichern + movec d0,cacr // cache aus + move.l d0,_rt_cacr // sichern + nop + + move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff + movec d0,ACR0 + move.l d0,_rt_acr0 // sichern + + move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff + movec d0,ACR1 + move.l d0,_rt_acr1 // sichern + + move.l #0xe007C400,d0 // instruction r wt e000'0000-e07f'ffff + movec d0,ACR2 + move.l d0,_rt_acr2 // sichern + + clr.l d0 // acr3 aus + movec d0,ACR3 + move.l d0,_rt_acr3 // sichern + + move.l #___MMUBAR+1,d0 + movec d0,MMUBAR //mmubar setzen + move.l d0,_rt_mmubar // sichern + + nop + + move.l #MCF_MMU_MMUOR_CA,d0 // clear all entries, + move.l d0,MCF_MMU_MMUOR + nop +// 0000'0000 locked + moveq.l #0x00000000|std_mmutr,d0 + moveq.l #0x00000000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + moveq.l #mmuord_d,d2 // MMU update date + moveq.l #mmuord_i,d3 // MMU update instruction + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // MMU update date + move.l d3,MCF_MMU_MMUOR // MMU update instruction + +//--------------------------------------------------------------------------------------- +// 00d0'0000 locked ID=6 +// video ram: read write execute normal write true + move.l #0x00d00000|MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 + move.l #0x60d00000|wt_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // MMU update date + move.l #0x00d00000|std_mmutr,d0 + move.l d3,MCF_MMU_MMUOR // MMU update instruction + + move.l #0x2000,d0 + move.l d0,_video_tlb // setze page als video page + clr.l _video_sbt // zeit löschen +//------------------------------------------------------------------------------------- +// 00e0'0000 locked + move.l #0x00e00000|std_mmutr,d0 + move.l #0x00e00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen read only ?????? noch nicht + move.l d3,MCF_MMU_MMUOR // setzen +// 00f0'0000 locked + move.l #0x00f00000|std_mmutr,d0 + move.l #0xfff00000|nc_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // maped to ffffxxx, precise, + move.l d3,MCF_MMU_MMUOR // maped to ffffxxx, precise, +// 1fe0'0000 locked + move.l #0x1FE00000|std_mmutr,d0 + move.l #0x1FE00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen data + move.l d3,MCF_MMU_MMUOR // setzen instr +// 1ff0'0000 locked + move.l #0x1FF00000|std_mmutr,d0 + move.l #0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen data + move.l d3,MCF_MMU_MMUOR // setzen instr +// instr 0xFFF0'0000 nach 0x1FF0'0000 umleiten -->> short sprung +/* move.l #0xFFF00000|std_mmutr,d0 + move.l #0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d3,MCF_MMU_MMUOR // setzen instr +*/ + move.l #0xa10ca120,d0 + move.l d0,_rt_cacr // sichern + movec d0,cacr + nop + rts + +/********************************************************************/ + /* MMU table search /* +/********************************************************************/ +_mmutr_miss: + bsr cpusha + and.l #0xFFF00000,d0 + or.l #std_mmutr,d0 + move.l d0,MCF_MMU_MMUTR + and.l #0xFFF00000,d0 + or.l #cb_mmudr,d0 + move.l d0,MCF_MMU_MMUDR + moveq.l #mmuord_d,d0 // MMU update data + move.l d0,MCF_MMU_MMUOR // setzen + moveq.l #mmuord_i,d0 // MMU update instruction + move.l d0,MCF_MMU_MMUOR // setzen + move.l (sp)+,d0 + rte diff --git a/BaS_GNU/sources/movem.h b/BaS_GNU/sources/movem.h new file mode 100644 index 0000000..b79349d --- /dev/null +++ b/BaS_GNU/sources/movem.h @@ -0,0 +1,256 @@ +// movem +_ii_movem_lset: .macro +// movem rx,xxx.L + ii_lset 0x48f9 +// movem rx,-(ax) + +// movem (ax)+,rx + ii_lset 0x4cd8 + ii_lset 0x4cd9 + ii_lset 0x4cda + ii_lset 0x4cdb + ii_lset 0x4cdc + ii_lset 0x4cdd + ii_lset 0x4cde + ii_lset 0x4cdf +// movem xxx.L,rx + ii_lset 0x4cf9 +.endm +//***********************************************************************************/ +_ii_movem_func: .macro +//------------------------------------------------------------------- +// movem.l +//-------------------------------------------------------------------- +// movem.l (ax)+,reg +//-------------------------------------------------------------------- +//------------------------------------------------------------------------------- +ii_0x4cd8: // movem.l (a0)+,reglist + mvm_macro 0x4cd0,0x41e8,2 +ii_0x4cd9: // movem.l (a1)+,reglist + mvm_macro 0x4cd1,0x43e9,2 +ii_0x4cda: // movem.l (a2)+,reglist + mvm_macro 0x4cd2,0x45ea,2 +ii_0x4cdb: // movem.l (a3)+,reglist + mvm_macro 0x4cd3,0x47eb,2 +ii_0x4cdc: // movem.l (a4)+,reglist + mvm_macro 0x4cd4,0x49ec,2 +ii_0x4cdd: // movem.l (a5)+,reglist + mvm_macro 0x4cd5,0x4bed,2 +ii_0x4cde: // movem.l (a6)+,reglist + mvm_macro 0x4cd6,0x4dee,2 +ii_0x4cdf: // movem.l (a7)+,reglist + mvm_macro 0x4cd7,0x4fef,2 +//---------------------------------------------------------------------------- +ii_0x48f9: // movem.l reg,xxx.L + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro + ii_end +//--------------------------------------------------------------------------------------------- +ii_0x4cf9: // movem.l xxx.L,reg + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro + ii_end +.endm +//============================================================== +mvm_macro:.macro +halt + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x (ax),reg_list + move.w (a0)+,(a1)+ // register list + move.w #\2,(a1)+ // lea 0(ax),ax + lsl.l #\3,d1 // * anzahl byts pro wert + move.w d1,(a1)+ // offset von lea + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm + .long 0 +az_reg_table: + .byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70 + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0 + .byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0 +//--------------------------------------------------------------------------------- +movemrm_macro:.macro // in d0 register liste, in a1 zieladresse +halt + tst.b d0 // datenregister zu verschieben? + bne mrm_dx // ja-> + lsr.l #8,d0 // sonst zu addressregister + jmp mmrm_nd7 // -> +mrm_dx: + lsr.l #1,d0 + bcc mmrm_nd0 + move.l d0_off(a7),(a1)+ +mmrm_nd0: + lsr.l #1,d0 + bcc mmrm_nd1 + move.l d1_off(a7),(a1)+ +mmrm_nd1: + lsr.l #1,d0 + bcc mmrm_nd2 + move.l d2,(a1)+ +mmrm_nd2: + lsr.l #1,d0 + bcc mmrm_nd3 + move.l d3,(a1)+ +mmrm_nd3: + lsr.l #1,d0 + bcc mmrm_nd4 + move.l d4,(a1)+ +mmrm_nd4: + lsr.l #1,d0 + bcc mmrm_nd5 + move.l d5,(a1)+ +mmrm_nd5: + lsr.l #1,d0 + bcc mmrm_nd6 + move.l d6,(a1)+ +mmrm_nd6: + lsr.l #1,d0 + bcc mmrm_nd7 + move.l d7,(a1)+ +mmrm_nd7: + tst.b d0 // addressregister zu verschieben? + beq mmrm_na7 + lsr.l #1,d0 + bcc mmrm_na0 + move.l a0_off(a7),(a1)+ +mmrm_na0: + lsr.l #1,d0 + bcc mmrm_na1 + move.l a1_off(a7),(a1)+ +mmrm_na1: + lsr.l #1,d0 + bcc mmrm_na2 + move.l a2,(a1)+ +mmrm_na2: + lsr.l #1,d0 + bcc mmrm_na3 + move.l a3,(a1)+ +mmrm_na3: + lsr.l #1,d0 + bcc mmrm_na4 + move.l a4,(a1)+ +mmrm_na4: + lsr.l #1,d0 + bcc mmrm_na5 + move.l a5,(a1)+ +mmrm_na5: + lsr.l #1,d0 + bcc mmrm_na6 + move.l a6,(a1)+ +mmrm_na6: + lsr.l #1,d0 + bcc mmrm_na7 + move.l a0,d1 // sichern + move.l usp,a0 // ist ja usp + move.l a0,(a1)+ // nach a0 + move.l d1,a0 // pc zurück +mmrm_na7: + .endm +//--------------------------------------------------------------------------------------------- +movemmr_macro:.macro // in d0 register liste, in a1 source adr +halt + tst.b d0 // datenregister zu verschieben? + bne mmr_dx // ja-> + lsr.l #8,d0 // sonst zu addressregister + bra mmmr_nd7 // -> +mmr_dx: + lsr.l #1,d0 + bcc mmmr_nd0 + move.l (a1)+,d0_off(a7) +mmmr_nd0: + lsr.l #1,d0 + bcc mmmr_nd1 + move.l (a1)+,d1_off(a7) +mmmr_nd1: + lsr.l #1,d0 + bcc mmmr_nd2 + move.l (a1)+,d2 +mmmr_nd2: + lsr.l #1,d0 + bcc mmmr_nd3 + move.l (a1)+,d3 +mmmr_nd3: + lsr.l #1,d0 + bcc mmmr_nd4 + move.l (a1)+,d4 +mmmr_nd4: + lsr.l #1,d0 + bcc mmmr_nd5 + move.l (a1)+,d5 +mmmr_nd5: + lsr.l #1,d0 + bcc mmmr_nd6 + move.l (a1)+,d6 +mmmr_nd6: + lsr.l #1,d0 + bcc mmmr_nd7 + move.l (a1)+,d7 +mmmr_nd7: + tst.b d0 // addressregister zu verschieben? + beq mmmr_na7 // nein-> + lsr.l #1,d0 + bcc mmmr_na0 + move.l (a1)+,a0_off(a7) +mmmr_na0: + lsr.l #1,d0 + bcc mmmr_na1 + move.l (a1)+,a1_off(a7) +mmmr_na1: + lsr.l #1,d0 + bcc mmmr_na2 + move.l (a1)+,a2 +mmmr_na2: + lsr.l #1,d0 + bcc mmmr_na3 + move.l (a1)+,a3 +mmmr_na3: + lsr.l #1,d0 + bcc mmmr_na4 + move.l (a1)+,a4 +mmmr_na4: + lsr.l #1,d0 + bcc mmmr_na5 + move.l (a1)+,a5 +mmmr_na5: + lsr.l #1,d0 + bcc mmmr_na6 + move.l (a1)+,a6 +mmmr_na6: + lsr.l #1,d0 + bcc mmmr_na7 + move.l a0,d1 // sichern + move.l (a1)+,a0 // nach a0 + move.l a0,usp // war ja usp + move.l d1,a0 // pc zurück +mmmr_na7: + .endm diff --git a/BaS_GNU/sources/sd_card.s b/BaS_GNU/sources/sd_card.s new file mode 100644 index 0000000..c51147c --- /dev/null +++ b/BaS_GNU/sources/sd_card.s @@ -0,0 +1,406 @@ +/********************************************************************/ +// sd card +/********************************************************************/ +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 + +.text +sd_test: + lea MCF_PSC0_PSCTB_8BIT,a6 + move.l #'SD-C',(a6) + move.l #'ard ',(a6) + + move.l #__Bas_base,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) + move.l #0x1fffffff,d0 // normal dspi + move.l d0,MCF_PAD_PAR_DSPI + lea MCF_DSPI_DMCR,a0 + move.l #0x800d3c00,(a0) // 8 bit cs5 on + move.l #0x38558897,d0 + move.l d0,dspi_dtar0(a0) // 400kHz + move.l #0x082000ff,d4 // tx vorbesetzen + mov3q.l #-1,dspi_dsr(a0) + + bsr warte_1ms + move.l #0xc00d3c00,(a0) // 8 bit 4MHz clocken cs off + bsr warte_10ms + move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off + clr.b d4 + bsr sd_com + bsr sd_com + move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on + move.b #0xff,d4 + bsr sd_com + bsr sd_com + move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off + bsr warte_10ms + +// sd idle + move.l #100,d6 // 100 versuche + move.l #10,d3 // 10 versuche +sd_idle: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x40,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + move.b #0xff,d4 // receive byt + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + subq.l #1,d6 + beq sd_not + bra sd_idle +idle_end: +// cdm 8 +read_ic: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x48,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + move.b #0xaa,d4 + bsr sd_com + move.b #0x87,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #5,d5 + beq sd_v1 + cmp.b #1,d5 + bne read_ic + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com + cmp.b #0xaa,d5 + bne sd_testd3 + + move.l #'SDHC',(a6) + move.b #' ',(a6) +sd_v1: + +// cdm 58 +read_ocr: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x7a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + move.l #'Ver1',d6 + cmp.b #5,d5 + beq read_ocr + cmp.b #1,d5 + bne read_ocr + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com + +// acdm 41 + move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen +wait_of_aktiv: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x77,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x05,d5 + beq wait_of_aktiv + +wait_of_aktiv2: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x69,d4 + bsr sd_com + move.b #0x40,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq wait_of_aktiv2 + subq.l #1,d6 + bne wait_of_aktiv +sd_testd3: + subq.l #1,d3 + bne sd_idle + bra sd_error + +sd_init_ok: +// cdm 10 +read_cid: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x4a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + move.l a5,a4 // adresse setzen + bsr sd_rcv_info + +// name ausgeben + lea 1(a5),a4 + moveq #7,d7 +sd_nam_loop: + move.b (a4)+,(a6) + subq.l #1,d7 + bne sd_nam_loop + move.b #' ',(a6) + +// cdm 9 +read_csd: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x49,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + move.l a5,a4 // adresse setzen + bsr sd_rcv_info + + mvz.b (a5),d0 + lsr.l #6,d0 + + bne sd_csd2 // format v2 + move.l 6(a5),d1 + moveq #14,d0 // bit 73..62 c_size + lsr.l d0,d1 // bits extrahieren + and.l #0xfff,d1 // 12 bits + addq.l #1,d1 + mvz.w 9(a5),d0 + lsr.l #7,d0 // bits 49..47 + and.l #0x7,d0 // 3 bits + moveq.l #8,d2 // x256 (dif v1 v2) + sub.l d0,d2 + lsr.l d2,d1 + bra sd_print_size +sd_csd2: + mvz.w 8(a5),d1 + addq.l #1,d1 +sd_print_size: + swap d1 + lsl.l #1,d1 + bcc sd_16G + move.l #'32GB',(a6) + bra sd_ok +sd_16G: + lsl.l #1,d1 + bcc sd_8G + move.l #'16GB',(a6) + bra sd_ok +sd_8G: + lsl.l #1,d1 + bcc sd_4G + move.l #' 8GB',(a6) + bra sd_ok +sd_4G: + lsl.l #1,d1 + bcc sd_2G + move.l #' 4GB',(a6) + bra sd_ok +sd_2G: + lsl.l #1,d1 + bcc sd_1G + move.l #' 2GB',(a6) + bra sd_ok +sd_1G: + lsl.l #1,d1 + bcc sd_512M + move.l #' 1GB',(a6) + bra sd_ok +sd_512M: + lsl.l #1,d1 + bcc sd_256M + move.b #'5',(a6) + move.l #'12MB',(a6) + bra sd_ok +sd_256M: + lsl.l #1,d1 + bcc sd_128M + move.b #'2',(a6) + move.l #'56MB',(a6) + bra sd_ok +sd_128M: + lsl.l #1,d1 + bcc sd_64M + move.b #'1',(a6) + move.l #'28MB',(a6) + bra sd_ok +sd_64M: + lsl.l #1,d1 + bcc sd_32M + move.l #'64MB',(a6) + bra sd_ok +sd_32M: + lsl.l #1,d1 + bcc sd_16M + move.l #'32MB',(a6) + bra sd_ok +sd_16M: + lsl.l #1,d1 + bcc sd_8M + move.l #'16MB',(a6) + bra sd_ok +sd_8M: + move.l #'<9MB',(a6) +sd_ok: + move.l #' OK!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts +// subs ende ------------------------------- +sd_V1: + move.l #'non!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts +sd_error: + move.l #'Erro',(a6) + move.l #'r!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts +sd_not: + move.l #'non!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts + +// status holen ------------------------------- +sd_get_status: + move.b #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_get_status + rts +// byt senden und holen --------------------- +sd_com: + move.l d4,dspi_dtfr(a0) +wait_auf_complett: + btst.b #7,dspi_dsr(a0) + beq wait_auf_complett + move.l dspi_drfr(a0),d5 + mov3q.l #-1,dspi_dsr(a0) // clr status register + rts + +// daten holen ---------------------------- +sd_rcv_info: + moveq #18,d3 // 16 byts + 2 byts crc + move.b #0xff,d4 +sd_rcv_rb_w: + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rcv_rb_w // nein-> +sd_rcv_rd_rb: + bsr sd_com + move.b d5,(a4)+ + subq.l #1,d3 + bne sd_rcv_rd_rb + rts +/******************************************/ diff --git a/BaS_GNU/sources/sd_ide.c b/BaS_GNU/sources/sd_ide.c new file mode 100644 index 0000000..092f95e --- /dev/null +++ b/BaS_GNU/sources/sd_ide.c @@ -0,0 +1,543 @@ + + +#include "MCF5475.h" +#include "startcf.h" + +extern unsigned long far __SP_AFTER_RESET[]; +extern unsigned long far __Bas_base[]; + + /* imported routines */ +//extern int warten_20ms(); +//extern int warten_200us(); +//extern int warten_10us(); + +/********************************************************************/ +void asm sd_test(void) +{ + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} + + +/**************************************************/ +void asm ide_test(void) +{ + lea MCF_PAD_PAR_DSPI,a0 + move.w #0x1fff,(a0) + lea MCF_DSPI_DCTAR0,a0 + move.l #0x38a644e4,(a0) + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) + clr.l MCF_DSPI_DTCR + bsr warten_20ms + lea MCF_DSPI_DTFR,a0 + lea MCF_DSPI_DRFR,a1 + + moveq #10,d0 +sd_reset: + move.l #0x000100ff,(a0) + bsr warten_20ms + and.l (a1),d0 + subq.l #1,d0 + bne sd_reset + + moveq #10,d1 +sd_loop1: + bsr warten_20ms + moveq #-1,d0 +// cmd 0 set to idle + move.l #0x00200040,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200095,(a0) + bsr warten_20ms + and.l (a1),d0 + cmp.w #0x0001,d0 + beq sd_loop2 + subq.l #1,d1 + bne sd_loop1 + moveq #10,d1 + bra sd_test +sd_loop2: + moveq #-1,d0 +// cmd 41 + move.l #0x00200069,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200001,(a0) + bsr warten_20ms + and.l (a1),d0 + tst.w d0 + bne sd_loop2 + + nop + nop +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst.b #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} +/********************************************************************/ diff --git a/BaS_GNU/sources/sd_ide.s b/BaS_GNU/sources/sd_ide.s new file mode 100644 index 0000000..4d31184 --- /dev/null +++ b/BaS_GNU/sources/sd_ide.s @@ -0,0 +1,458 @@ + + +//.include "startcf.h" + +//.extern ___MBAR +//#define MCF_SLT0_SCNT ___MBAR+0x908 + +//.global ide_test + +.text +/* +sd_test: + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +/********************************************************************/ diff --git a/BaS_GNU/sources/startcf.S b/BaS_GNU/sources/startcf.S new file mode 100644 index 0000000..415f103 --- /dev/null +++ b/BaS_GNU/sources/startcf.S @@ -0,0 +1,82 @@ +/* + * CF_Startup.c - Default init/startup/termination routines for + * Embedded Metrowerks C++ + * + * Copyright � 1993-1998 Metrowerks, Inc. All Rights Reserved. + * Copyright � 2005 Freescale semiConductor Inc. All Rights Reserved. + * + * + * THEORY OF OPERATION + * + * This version of thestartup code is intended for linker relocated + * executables. The startup code will assign the stack pointer to + * __SP_INIT, assign the address of the data relative base address + * to a5, initialize the .bss/.sbss sections to zero, call any + * static C++ initializers and then call main. Upon returning from + * main it will call C++ destructors and call exit to terminate. + */ + +#ifdef __cplusplus +#pragma cplusplus off +#endif +#pragma PID off +#pragma PIC off + +#include + + + /* imported data */ + +extern unsigned long far _SP_INIT, _SDA_BASE; +extern unsigned long far _START_BSS, _END_BSS; +extern unsigned long far _START_SBSS, _END_SBSS; +extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END; +extern unsigned long far __Bas_base; + +extern unsigned long far __SUP_SP,__BOOT_FLASH; +extern unsigned long far rt_mbar; + + /* imported routines */ + +extern int BaS(int, char **); + + /* exported routines */ +extern void __initialize_hardware(void); +extern void init_slt(void); + + +void _startup(void) +{ + asm("\n\t" + "bra warmstart\n\t" + "jmp __BOOT_FLASH + 8 // ist zugleich reset vector\n\t" + "/* disable interrupts */\n\t" +"warmstart:\n\t" + "// disable interrupts\n\t" + "move.w #0x2700,sr\n\t" + "// Initialize MBAR\n\t" + "MOVE.L #__MBAR,D0\n\t" + "MOVEC D0,MBAR\n\t" + "MOVE.L D0,rt_mbar\n\t" +"// mmu off\n\t" + "move.l #__MMUBAR+1,d0\n\t" + movec d0,MMUBAR //mmubar setzen + clr.l d0 + move.l d0,MCF_MMU_MMUCR // mmu off + /* Initialize RAMBARs: locate SRAM and validate it */ \ + move.l #__RAMBAR0 + 0x7,d0 // supervisor only + movec d0,RAMBAR0 + move.l #__RAMBAR1 + 0x1,d0 // on for all + movec d0,RAMBAR1 + +// STACKPOINTER AUF ENDE SRAM1 + lea __SUP_SP,a7 + +// instruction cache on + move.l #0x000C8100,d0 + movec d0,cacr + nop +// initialize any hardware specific issues + bra __initialize_hardware +"); +} diff --git a/BaS_GNU/sources/startcf.h b/BaS_GNU/sources/startcf.h new file mode 100644 index 0000000..c538f16 --- /dev/null +++ b/BaS_GNU/sources/startcf.h @@ -0,0 +1,47 @@ +/****************************************************************************** + FILE : startcf.h + PURPOSE : startup code for ColdFire + LANGUAGE: C + + + Notes: + 1) Default entry point is _startup. + . disable interrupts + . the SP is set to __SP_AFTER_RESET + . SP must be initialized to valid memory + in case the memory it points to is not valid using MEMORY_INIT macro + 2) __initialize_hardware is called. Here you can initialize memory and some peripherics + at this point global variables are not initialized yet + 3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform + needed initialisations for the language (clear memory, data rom copy). + 4) void __initialize_system(void); is called + to allow additional hardware initialization (UART, GPIOs, etc...) + 5) Jump to main + +*/ +/********************************************************************************/ + +#define cf_stack + +//#define ii_on +#define halten +#define halten_dbcc +#define halten_and +#define halten_add +#define halten_sub +#define halten_or +#define halten_op +#define halten_opc +#define halten_movem +#define halten_lea +#define halten_shift +#define halten_move +#define halten_exg +#define halten_movep +#define halten_ewf + +#define DIP_SWITCH (*(vuint8 *)(&__MBAR[0xA2C])) +#define DIP_SWITCHa ___MBAR + 0xA2C + +#define sca_page_ID 6 + diff --git a/BaS_GNU/sources/supervisor.s b/BaS_GNU/sources/supervisor.s new file mode 100644 index 0000000..29cd97f --- /dev/null +++ b/BaS_GNU/sources/supervisor.s @@ -0,0 +1,585 @@ +/********************************************************/ +/* user/supervisor handler +/********************************************************/ + +.include "startcf.h" + +.extern _rt_cacr; +.extern _rt_mod; +.extern _rt_ssp; +.extern _rt_usp; +.extern ___MMUBAR + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + +.public _privileg_violation +.public cpusha + +.text +_privileg_violation: + move.w #0x2700,sr + lea -12(a7),a7 + movem.l d0/a0/a5,(a7) +#ifndef cf_stack + lea 0x52f0,a0 + move.l #0x20,(a0) // set auf 68030 +#endif + lea _rt_mod,a0 // zugriff setzen + tst.b (a0) // vom rt_supervisormodus? + bne pv_work // ja-> +// tatsächlich privileg violation + mov3q.l #-1,(a0) // sr_mod setzen + move.l usp,a5 // usp holen + move.l a5,8(a0) // sichern + move.l 4(a0),a5 // rt_ssp holen +#ifdef cf_stack + move.l 16(a7),-(a5) // pc verschieben + move.l 12(a7),-(a5) // sr verschieben + bset #5,2(a5) // auf super setzen +#else + move.w 12(a7),-(a5) // vector nr. + move.l 16(a7),-(a5) // pc verschieben + move.w 14(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif + move.l a5,usp + move.l 12(a0),a5 // rt_vbr + lea 0x18(a5),a5 // vector + move.l (a5),16(a7) // vector privileg violation + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// privileg violation +pv_work: + move.l 16(a7),a5 // fault pc + move.b (a5),d0 // fault code + cmp.b #0x4e,d0 // 1.byt 0x4e + beq pv_4e // ja-> + cmp.b #0x46,d0 // 1.byt 0x46 + beq pv_46 // ja-> + cmp.b #0x40,d0 // 1.byt 0x40 + beq pv_40 // ja-> + cmp.b #0xf4,d0 // 0xf4? + beq pv_f4 + cmp.b #0xf3,d0 // 0xf3? + beq pv_f3 +// hierher sollt man nicht kommen + nop + halt + nop +// code 0x4exx ******************************************** +pv_4e: + move.b 1(a5),d0 + cmp.b #0x73,d0 //rte? + beq pv_rte //ja-> + cmp.b #0x72,d0 //stop? + beq pv_stop //ja-> + cmp.b #0x7B,d0 //movec? + beq pv_movec //ja-> +// move usp + btst #3,d0 // to or from + bne pv_usp_to_ax // usp -> ax +// move ax->usp + cmp.b #0x60,d0 //movec? + beq pv_a0_usp //ja-> + cmp.b #0x61,d0 //movec? + beq pv_a1_usp //ja-> + cmp.b #0x62,d0 //movec? + beq pv_a2_usp //ja-> + cmp.b #0x63,d0 //movec? + beq pv_a3_usp //ja-> + cmp.b #0x64,d0 //movec? + beq pv_a4_usp //ja-> + cmp.b #0x65,d0 //movec? + beq pv_a5_usp //ja-> + cmp.b #0x66,d0 //movec? + beq pv_a6_usp //ja-> + halt + bra pv_a7_usp //ja-> +// move usp->ax +pv_usp_to_ax: + move.l 8(a0),a5 //rt_usp holen + cmp.b #0x68,d0 //movec? + beq pv_usp_a0 //ja-> + cmp.b #0x69,d0 //movec? + beq pv_usp_a1 //ja-> + cmp.b #0x6a,d0 //movec? + beq pv_usp_a2 //ja-> + cmp.b #0x6b,d0 //movec? + beq pv_usp_a3 //ja-> + cmp.b #0x6c,d0 //movec? + beq pv_usp_a4 //ja-> + cmp.b #0x6d,d0 //movec? + beq pv_usp_a5 //ja-> + cmp.b #0x6e,d0 //movec? + beq pv_usp_a6 //ja-> +// usp->a7 + move.l a5,4(a0) // rt usp -> rt ssp + move.l a5,usp // und setzen + bra pv_usp_ax +// a0->usp +pv_a0_usp: move.l 4(a7),a5 + bra pv_ax_usp +// a1->usp +pv_a1_usp: move.l a1,a5 + bra pv_ax_usp +// a2->usp +pv_a2_usp: move.l a2,a5 + bra pv_ax_usp +// a3->usp +pv_a3_usp: move.l a3,a5 + bra pv_ax_usp +// a4->usp +pv_a4_usp: move.l a4,a5 + bra pv_ax_usp +// a5->usp +pv_a5_usp: move.l 8(a7),a5 + bra pv_ax_usp +// a6->usp +pv_a6_usp: move.l a6,a5 + bra pv_ax_usp +// a7->usp +pv_a7_usp: move.l 4(a0),a5 // rt_ssp -> a5 +pv_ax_usp: + move.l a5,8(a0) // usp -> rt_usp + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// usp->a0 +pv_usp_a0: + move.l a5,4(a7) + bra pv_usp_ax +pv_usp_a1: + move.l a5,a1 + bra pv_usp_ax +pv_usp_a2: + move.l a5,a2 + bra pv_usp_ax +pv_usp_a3: + move.l a5,a3 + bra pv_usp_ax +pv_usp_a4: + move.l a5,a4 + bra pv_usp_ax +pv_usp_a5: + move.l a5,8(a7) + bra pv_usp_ax +pv_usp_a6: + move.l a5,a6 +pv_usp_ax: + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// rte +pv_rte: + move.l usp,a5 +#ifdef cf_stack + move.l (a5)+,12(a7) // sr verschieben + move.l (a5)+,16(a7) // pc verschieben +#else + move.w (a5)+,14(a7) // sr verschieben + move.l (a5)+,16(a7) // pc verschieben + move.w (a5)+,12(a7) // vector +#endif + bclr #5,14(a7) // war es von super? + bne pv_rte_sup // ja-> + clr.l (a0) // rt_mod auf user + move.l a5,4(a0) // rt_ssp sichern + move.l 8(a0),a5 // rt_usp holen +pv_rte_sup: + move.l a5,usp // usp setzen + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// stop +pv_stop: + move.b 2(a5),d0 // sr wert + and.l #0x0700,d0 // int mask + cmp.w #0x700,d0 + beq stop7 + cmp.w #0x600,d0 + beq stop6 + cmp.w #0x500,d0 + beq stop5 + cmp.w #0x400,d0 + beq stop4 + cmp.w #0x300,d0 + beq stop3 + cmp.w #0x200,d0 + beq stop2 + cmp.w #0x100,d0 + beq stop1 + stop #0x2000 + bra stop_weiter +stop1: + stop #0x2100 + bra stop_weiter +stop2: + stop #0x2200 + bra stop_weiter +stop3: + stop #0x2300 + bra stop_weiter +stop4: + stop #0x2400 + bra stop_weiter +stop5: + stop #0x2500 + bra stop_weiter +stop6: + stop #0x2600 + bra stop_weiter +stop7: + stop #0x2700 +stop_weiter: + addq.l #4,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// movec ??????? +pv_movec: + move.w 2(a5),d0 // 2.word holen + and.l #0xf000,d0 + btst #15,d0 // addressregister? + bne pv_movec_ax // ja-> + tst.w d0 // d0? + bne pvm_d1 // nein-> + move.l (a7),-(a7) // d0 holen und sichern + bra pvm_me +pvm_d1: + cmp.w #0x1000,d0 // d1? + bne pvm_d2 // nein-> + move.l d1,-(a7) // d1 holen und sichern + bra pvm_me // fertig machen +pvm_d2: + cmp.w #0x2000,d0 // d1? + bne pvm_d3 // nein-> + move.l d2,-(a7) // d2 holen und sichern + bra pvm_me // fertig machen +pvm_d3: + cmp.w #0x3000,d0 // d1? + bne pvm_d4 // nein-> + move.l d3,-(a7) // d3 holen und sichern + bra pvm_me // fertig machen +pvm_d4: + cmp.w #0x4000,d0 // d1? + bne pvm_d5 // nein-> + move.l d4,-(a7) // d4 holen und sichern + bra pvm_me // fertig machen +pvm_d5: + cmp.w #0x5000,d0 // d1? + bne pvm_d6 // nein-> + move.l d5,-(a7) // d5 holen und sichern + bra pvm_me // fertig machen +pvm_d6: + cmp.w #0x6000,d0 // d1? + bne pvm_d7 // nein-> + move.l d6,-(a7) // d6 holen und sichern + bra pvm_me // fertig machen +pvm_d7: + move.l d7,-(a7) // d7 holen und sichern + bra pvm_me // fertig machen +pv_movec_ax: + cmp.w #0x8000,d0 // a0? + bne pvm_a1 // nein-> + move.l 4(a7),-(a7) // a0 holen und sichern + bra pvm_me // fertig machen +pvm_a1: + cmp.w #0x9000,d0 // a0? + bne pvm_a2 // nein-> + move.l a1,-(a7) // a1 holen und sichern + bra pvm_me // fertig machen +pvm_a2: + cmp.w #0xa000,d0 // a0? + bne pvm_a3 // nein-> + move.l a2,-(a7) // a2 holen und sichern + bra pvm_me // fertig machen +pvm_a3: + cmp.w #0xb000,d0 // a0? + bne pvm_a4 // nein-> + move.l a3,-(a7) // a3 holen und sichern + bra pvm_me // fertig machen +pvm_a4: + cmp.w #0xc000,d0 // a0? + bne pvm_a5 // nein-> + move.l a4,-(a7) // a4 holen und sichern + bra pvm_me // fertig machen +pvm_a5: + cmp.w #0xd000,d0 // a0? + bne pvm_a6 // nein-> + move.l 8(a7),-(a7) // a5 holen und sichern + bra pvm_me // fertig machen +pvm_a6: + cmp.w #0xe000,d0 // a0? + bne pvm_a7 // nein-> + move.l a6,-(a7) // a6 holen und sichern + bra pvm_me // fertig machen +pvm_a7: + move.l 4(a7),-(a7) // a7 holen und sichern +pvm_me: + move.w 2(a5),d0 // 2.word holen + andi.l #0xf,d0 // nur letzte 4 bits + move.l (a7)+,8(a0,d0*4) // start bei +8, *4 weil long + jsr cpusha // gesammten cache flushen + rte +// code 0x46xx ***************************************** +pv_46: + move.b 1(a5),d0 + cmp.b #0xfc,d0 //#d16->sr + beq im_sr //ja-> +//move dx->sr (sr und rt_mod ist supervisor sonst wäre es privileg violation + cmp.b #0xc0,d0 //d0->sr? + bne d1_sr //nein-> + move.w 2(a7),d0 //hier ist d0 gesichert + bra d0_sr +d1_sr: + cmp.b #0xc1,d0 //d1->sr? + bne d2_sr //nein-> + move.w d1,d0 + bra d0_sr +d2_sr: + cmp.b #0xc2,d0 //d2->sr? + bne d3_sr + move.w d2,d0 + bra d0_sr +d3_sr: + cmp.b #0xc3,d0 //d3->sr? + bne d4_sr + move.w d3,d0 + bra d0_sr +d4_sr: + cmp.b #0xc4,d0 //d4->sr? + bne d5_sr + move.w d4,d0 + bra d0_sr +d5_sr: + cmp.b #0xc5,d0 //d5->sr? + bne d6_sr + move.w d5,d0 + bra d0_sr +d6_sr: + cmp.b #0xc6,d0 //d6->sr? + bne d7_sr + move.w d6,d0 + bra d0_sr +d7_sr: + move.w d7,d0 // sonst d7->sr +d0_sr: + addq.l #2,16(a7) // next + bra pv_set_sr_end // fertig machen +// move #xxxx,sr +im_sr: + addq.l #4,16(a7) // next + move.w 2(a5),d0 // data +pv_set_sr_end: + bclr #13,d0 // war super? + bne pv_sre2 // ja -> + clr.l (a0) + move.l usp,a5 // usp + move.l a5,4(a0) // rt_ssp speichern + move.l 8(a0),a5 // rt_usp holen + move.l a5,usp // setzen +pv_sre2: + move.w d0,14(a7) // sr setzen + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// code 0x40xx ***************************************** +pv_40: + move.b 1(a5),d0 // 2.byt + cmp.b #0xe7,d0 + beq pv_strldsr +// move sr->dx + move.l 12(a7),a5 // sr holen + tst.b (a0) // super? + beq pv_40_user // nein? + lea 0x2000(a5),a5 // super zuaddieren +pv_40_user: + cmp.b #0xc0,d0 + bne nsr_d1 + move.w a5,2(a7) + bra sr_dx_end +nsr_d1: + cmp.b #0xc1,d0 + bne nsr_d2 + move.w a5,d1 + bra sr_dx_end +nsr_d2: + cmp.b #0xc2,d0 + bne nsr_d3 + move.w a5,d2 + bra sr_dx_end +nsr_d3: + cmp.b #0xc3,d0 + bne nsr_d4 + move.w a5,d3 + bra sr_dx_end +nsr_d4: + cmp.b #0xc4,d0 + bne nsr_d5 + move.w a5,d4 + bra sr_dx_end +nsr_d5: + cmp.b #0xc5,d0 + bne nsr_d6 + move.w a5,d5 + bra sr_dx_end +nsr_d6: + cmp.b #0xc6,d0 + bne nsr_d7 + move.w a5,d6 + bra sr_dx_end +nsr_d7: + move.w a5,d7 + halt +sr_dx_end: + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// strldsr +pv_strldsr: + nop + halt + nop +// code 0xf4xx *********************************** +pv_f4: + addq.l #2,16(a7) // next instr + move.b 1(a5),d0 // 2.byt + bsr pv_ax_a0 // richtiges register + move.b 1(a5),d0 // 2.byt + cmp.b #0x30,d0 // >0xf430 + blo pv_intouch +// cpushl + cpushl bc,(a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +pv_intouch: + intouch (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +// subroutine register ax->a0 +pv_ax_a0: + and.l #0x7,d0 // nur register nummer + subq.l #1,d0 + bmi pv_a0_a0 + subq.l #1,d0 + bmi pv_a1_a0 + subq.l #1,d0 + bmi pv_a2_a0 + subq.l #1,d0 + bmi pv_a3_a0 + subq.l #1,d0 + bmi pv_a4_a0 + subq.l #1,d0 + bmi pv_a5_a0 + subq.l #1,d0 + bmi pv_a6_a0 + move.l a7,a0 + rts +pv_a0_a0: + move.l 8(a7),a0 + rts +pv_a1_a0: + move.l a1,a0 + rts +pv_a2_a0: + move.l a2,a0 + rts +pv_a3_a0: + move.l a3,a0 + rts +pv_a4_a0: + move.l a4,a0 + rts +pv_a5_a0: + move.l 12(a7),a0 + rts +pv_a6_a0: + move.l a6,a0 + rts +// code 0xf4xx *********************************** +pv_f3: + addq.l #2,16(a7) // next instr + move.b 1(a5),d0 // 2. byt + cmp.b #0x40,d0 + bgt pv_frestore +//fsave (ax) oder d16(ax) + jsr pv_ax_a0 // richtiges register holen + move.b 1(a5),d0 + cmp.b #0x20,d0 +// +d16 + blt pv_f3_ax + addq.l #2,16(a7) // next instr + clr.l d0 + move.w 2(a0),d0 // d16 + add.l d0,a0 +pv_f3_ax: + fsave (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +pv_frestore: + cmp.b #0x7a,d0 + beq pv_f_d16pc +// frestore (ax) oder d16(ax) + jsr pv_ax_a0 // richtiges register holen + move.b 1(a5),d0 + cmp.b #0x60,d0 + blt pv_frestore_ax +pv_fend: + addq.l #2,16(a7) // next instr + clr.l d0 + move.w 2(a0),d0 // d16 + add.l d0,a0 +pv_frestore_ax: + frestore (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +// frestore d16(pc) +pv_f_d16pc: + move.l 16(a7),a0 // pc holen + bra pv_fend +//***************************************************** +cpusha: + lea -16(a7),a7 + movem.l d0-d2/a0,(a7) // register sichern + move sr,d2 + nop + move #0x2700,sr // no interrupts + + clr.l d0 + clr.l d1 + move.l d0,a0 +cfa_setloop: + cpushl bc,(a0) // flush + lea 0x10(a0),a0 // index+1 + addq.l #1,d1 // index+1 + cmpi.w #512,d1 // alle sets? + bne cfa_setloop // nein-> + clr.l d1 + addq.l #1,d0 + move.l d0,a0 + cmpi.w #4,d0 // all ways? + bne cfa_setloop // nein-> + nop + move.l _rt_cacr,d0 // holen + movec d0,cacr // setzen + move.w d2,sr // alte interrupt maske + movem.l (a7),d0-d2/a0 // register zurück + lea 16(a7),a7 + + rts +//*******************************************************33 +