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implemented hook_interrupt() in PCI code

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enabled PCI interrupts
ohci seems to damage something in PCI config -> PCI device enumeration 
does not top with latest device
networking in EmuTOS lost (probably a result of PCI interrupt
implementation)
This commit is contained in:
Markus Fröschle
2014-10-05 17:50:15 +00:00
parent 2ee1ddf58d
commit ab7371532f
21 changed files with 1842 additions and 1577 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
include/interrupts.h
View File

@@ -95,14 +95,41 @@
#define FEC1TX_DMA_PRI 4
#define FECTX_DMA_PRI(x) ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)
extern int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void));
#define ISR_DBUG_ISR 0x01
#define ISR_USER_ISR 0x02
#if defined(MACHINE_FIREBEE)
/* Firebee FPGA interrupt controller */
#define FPGA_INTR_CONTROL ((volatile uint32_t *) 0xf0010000)
#define FPGA_INTR_ENABLE ((volatile uint32_t *) 0xf0010004)
#define FPGA_INTR_CLEAR ((volatile uint32_t *) 0xf0010008)
#define FPGA_INTR_PENDING ((volatile uint32_t *) 0xff01000c)
/* register bits for Firebee FPGA-based interrupt controller */
#define FPGA_INTR_PIC (1)
#define FPGA_INTR_ETHERNET (1 << 1)
#define FPGA_INTR_DVI (1 << 2)
#define FPGA_INTR_PCI_INTA (1 << 3)
#define FPGA_INTR_PCI_INTB (1 << 4)
#define FPGA_INTR_PCI_INTC (1 << 5)
#define FPGA_INTR_PCI_INTD (1 << 6)
#define FPGA_INTR_INT_DSP (1 << 7)
#define FPGA_INTR_INT_VSYNC (1 << 8)
#define FPGA_INTR_INT_HSYNC (1 << 9)
#define FPGA_INTR_INT_HSYNC_IRQ2 (1 << 26)
#define FPGA_INTR_INT_CTR0_IRQ3 (1 << 27)
#define FPGA_INTR_INT_VSYNC_IRQ4 (1 << 28)
#define FPGA_INTR_INT_FPGA_IRQ5 (1 << 29)
#define FPGA_INTR_INT_MFP_IRQ6 (1 << 30)
#define FPGA_INTR_INT_IRQ7 (1 << 31)
#endif /* MACHINE_FIREBEE */
extern void isr_init(void);
extern int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg);
extern void isr_remove_handler(int (*handler)(void *, void *));
extern bool isr_execute_handler(int vector);
extern int pic_interrupt_handler(void *arg1, void *arg2);
extern int xlbpci_interrupt_handler(void *arg1, void *arg2);
extern int pciarb_interrupt_handler(void *arg1, void *arg2);
#endif /* _INTERRUPTS_H_ */

10
include/mmu.h
View File

@@ -58,10 +58,10 @@
enum mmu_page_size
{
MMU_PAGE_SIZE_1M = 0,
MMU_PAGE_SIZE_4K = 1,
MMU_PAGE_SIZE_8K = 2,
MMU_PAGE_SIZE_1K = 3
MMU_PAGE_SIZE_1M = 0,
MMU_PAGE_SIZE_4K = 1,
MMU_PAGE_SIZE_8K = 2,
MMU_PAGE_SIZE_1K = 3
};
#define SIZE_1M 0x100000 /* 1 Megabyte */
@@ -100,7 +100,7 @@ extern long video_sbt;
struct page_descriptor;
extern void mmu_init(void);
extern int mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct page_descriptor *flags);
extern int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct page_descriptor *flags);
/*
* API functions for the BaS driver interface

322
include/ohci.h
View File

@@ -6,62 +6,62 @@
*
* usb-ohci.h
*/
#define USB_OHCI_MAX_ROOT_PORTS 4
static int cc_to_error[16] =
{
/* mapping of the OHCI CC status to error codes */
/* No Error */ 0,
/* CRC Error */ USB_ST_CRC_ERR,
/* Bit Stuff */ USB_ST_BIT_ERR,
/* Data Togg */ USB_ST_CRC_ERR,
/* Stall */ USB_ST_STALLED,
/* DevNotResp */ -1,
/* PIDCheck */ USB_ST_BIT_ERR,
/* UnExpPID */ USB_ST_BIT_ERR,
/* DataOver */ USB_ST_BUF_ERR,
/* DataUnder */ USB_ST_BUF_ERR,
/* reservd */ -1,
/* reservd */ -1,
/* BufferOver */ USB_ST_BUF_ERR,
/* BuffUnder */ USB_ST_BUF_ERR,
/* Not Access */ -1,
/* Not Access */ -1
/* No Error */ 0,
/* CRC Error */ USB_ST_CRC_ERR,
/* Bit Stuff */ USB_ST_BIT_ERR,
/* Data Togg */ USB_ST_CRC_ERR,
/* Stall */ USB_ST_STALLED,
/* DevNotResp */ -1,
/* PIDCheck */ USB_ST_BIT_ERR,
/* UnExpPID */ USB_ST_BIT_ERR,
/* DataOver */ USB_ST_BUF_ERR,
/* DataUnder */ USB_ST_BUF_ERR,
/* reservd */ -1,
/* reservd */ -1,
/* BufferOver */ USB_ST_BUF_ERR,
/* BuffUnder */ USB_ST_BUF_ERR,
/* Not Access */ -1,
/* Not Access */ -1
};
static const char *cc_to_string[16] =
{
"No Error",
"CRC: Last data packet from endpoint contained a CRC error.",
"BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation",
"DATATOGGLEMISMATCH:\r\n Last packet from endpoint had data toggle PID\r\n" \
"that did not match the expected value.",
"STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID",
"DEVICENOTRESPONDING:\r\nDevice did not respond to token (IN) or did\r\n" \
"not provide a handshake (OUT)",
"PIDCHECKFAILURE:\r\nCheck bits on PID from endpoint failed on data PID\r\n"\
"(IN) or handshake (OUT)",
"UNEXPECTEDPID:\r\nReceive PID was not valid when encountered or PID\r\n" \
"value is not defined.",
"DATAOVERRUN:\r\nThe amount of data returned by the endpoint exceeded\r\n" \
"either the size of the maximum data packet allowed\r\n" \
"from the endpoint (found in MaximumPacketSize field\r\n" \
"of ED) or the remaining buffer size.",
"DATAUNDERRUN:\r\nThe endpoint returned less than MaximumPacketSize\r\n" \
"and that amount was not sufficient to fill the\r\n" \
"specified buffer",
"reserved1",
"reserved2",
"BUFFEROVERRUN:\r\nDuring an IN, HC received data from endpoint faster\r\n" \
"than it could be written to system memory",
"BUFFERUNDERRUN:\r\nDuring an OUT, HC could not retrieve data from\r\n" \
"system memory fast enough to keep up with data USB data rate.",
"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
"on a list to be processed by the HC.(1)",
"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
"on a list to be processed by the HC.(2)",
"No Error",
"CRC: Last data packet from endpoint contained a CRC error.",
"BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation",
"DATATOGGLEMISMATCH:\r\n Last packet from endpoint had data toggle PID\r\n" \
"that did not match the expected value.",
"STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID",
"DEVICENOTRESPONDING:\r\nDevice did not respond to token (IN) or did\r\n" \
"not provide a handshake (OUT)",
"PIDCHECKFAILURE:\r\nCheck bits on PID from endpoint failed on data PID\r\n"\
"(IN) or handshake (OUT)",
"UNEXPECTEDPID:\r\nReceive PID was not valid when encountered or PID\r\n" \
"value is not defined.",
"DATAOVERRUN:\r\nThe amount of data returned by the endpoint exceeded\r\n" \
"either the size of the maximum data packet allowed\r\n" \
"from the endpoint (found in MaximumPacketSize field\r\n" \
"of ED) or the remaining buffer size.",
"DATAUNDERRUN:\r\nThe endpoint returned less than MaximumPacketSize\r\n" \
"and that amount was not sufficient to fill the\r\n" \
"specified buffer",
"reserved1",
"reserved2",
"BUFFEROVERRUN:\r\nDuring an IN, HC received data from endpoint faster\r\n" \
"than it could be written to system memory",
"BUFFERUNDERRUN:\r\nDuring an OUT, HC could not retrieve data from\r\n" \
"system memory fast enough to keep up with data USB data rate.",
"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
"on a list to be processed by the HC.(1)",
"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
"on a list to be processed by the HC.(2)",
};
/* ED States */
@@ -75,24 +75,24 @@ static const char *cc_to_string[16] =
/* usb_ohci_ed */
struct ed
{
uint32_t hwINFO;
uint32_t hwTailP;
uint32_t hwHeadP;
uint32_t hwNextED;
uint32_t hwINFO;
uint32_t hwTailP;
uint32_t hwHeadP;
uint32_t hwNextED;
struct ed *ed_prev;
uint8_t int_period;
uint8_t int_branch;
uint8_t int_load;
uint8_t int_interval;
uint8_t state;
uint8_t type;
uint16_t last_iso;
struct ed *ed_rm_list;
struct ed *ed_prev;
uint8_t int_period;
uint8_t int_branch;
uint8_t int_load;
uint8_t int_interval;
uint8_t state;
uint8_t type;
uint16_t last_iso;
struct ed *ed_rm_list;
struct usb_device *usb_dev;
void *purb;
uint32_t unused[2];
struct usb_device *usb_dev;
void *purb;
uint32_t unused[2];
} __attribute__((aligned(16)));
typedef struct ed ed_t;
@@ -137,21 +137,21 @@ typedef struct ed ed_t;
struct td
{
uint32_t hwINFO;
uint32_t hwCBP; /* Current Buffer Pointer */
uint32_t hwNextTD; /* Next TD Pointer */
uint32_t hwBE; /* Memory Buffer End Pointer */
uint32_t hwINFO;
uint32_t hwCBP; /* Current Buffer Pointer */
uint32_t hwNextTD; /* Next TD Pointer */
uint32_t hwBE; /* Memory Buffer End Pointer */
uint16_t hwPSW[MAXPSW];
uint8_t unused;
uint8_t index;
struct ed *ed;
struct td *next_dl_td;
struct usb_device *usb_dev;
int transfer_len;
uint32_t data;
uint16_t hwPSW[MAXPSW];
uint8_t unused;
uint8_t index;
struct ed *ed;
struct td *next_dl_td;
struct usb_device *usb_dev;
int transfer_len;
uint32_t data;
uint32_t unused2[2];
uint32_t unused2[2];
} __attribute__((aligned(32)));
typedef struct td td_t;
@@ -166,16 +166,16 @@ typedef struct td td_t;
#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca
{
uint32_t int_table[NUM_INTS]; /* Interrupt ED table */
uint32_t int_table[NUM_INTS]; /* Interrupt ED table */
#if defined(CONFIG_MPC5200)
uint16_t pad1; /* set to 0 on each frame_no change */
uint16_t frame_no; /* current frame number */
uint16_t pad1; /* set to 0 on each frame_no change */
uint16_t frame_no; /* current frame number */
#else
uint16_t frame_no; /* current frame number */
uint16_t pad1; /* set to 0 on each frame_no change */
uint16_t frame_no; /* current frame number */
uint16_t pad1; /* set to 0 on each frame_no change */
#endif
uint32_t done_head; /* info returned for an interrupt */
uint8_t reserved_for_hc[116];
uint32_t done_head; /* info returned for an interrupt */
uint8_t reserved_for_hc[116];
} __attribute__((aligned(256)));
/*
@@ -185,35 +185,35 @@ struct ohci_hcca
*/
struct ohci_regs
{
/* control and status registers */
uint32_t revision;
uint32_t control;
uint32_t cmdstatus;
uint32_t intrstatus;
uint32_t intrenable;
uint32_t intrdisable;
/* memory pointers */
uint32_t hcca;
uint32_t ed_periodcurrent;
uint32_t ed_controlhead;
uint32_t ed_controlcurrent;
uint32_t ed_bulkhead;
uint32_t ed_bulkcurrent;
uint32_t donehead;
/* frame counters */
uint32_t fminterval;
uint32_t fmremaining;
uint32_t fmnumber;
uint32_t periodicstart;
uint32_t lsthresh;
/* Root hub ports */
/* control and status registers */
uint32_t revision;
uint32_t control;
uint32_t cmdstatus;
uint32_t intrstatus;
uint32_t intrenable;
uint32_t intrdisable;
/* memory pointers */
uint32_t hcca;
uint32_t ed_periodcurrent;
uint32_t ed_controlhead;
uint32_t ed_controlcurrent;
uint32_t ed_bulkhead;
uint32_t ed_bulkcurrent;
uint32_t donehead;
/* frame counters */
uint32_t fminterval;
uint32_t fmremaining;
uint32_t fmnumber;
uint32_t periodicstart;
uint32_t lsthresh;
/* Root hub ports */
struct ohci_roothub_regs
{
uint32_t a;
uint32_t b;
uint32_t status;
uint32_t portstatus[USB_OHCI_MAX_ROOT_PORTS];
} roothub;
uint32_t a;
uint32_t b;
uint32_t status;
uint32_t portstatus[USB_OHCI_MAX_ROOT_PORTS];
} roothub;
} __attribute__((aligned(32)));
/* Some EHCI controls */
@@ -270,11 +270,11 @@ struct ohci_regs
/* Virtual Root HUB */
struct virt_root_hub
{
int devnum; /* Address of Root Hub endpoint */
void *dev; /* was urb */
void *int_addr;
int send;
int interval;
int devnum; /* Address of Root Hub endpoint */
void *dev; /* was urb */
void *int_addr;
int send;
int interval;
};
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
@@ -372,18 +372,18 @@ struct virt_root_hub
#define N_URB_TD 48
typedef struct
{
ed_t *ed;
uint16_t length; /* number of tds associated with this request */
uint16_t td_cnt; /* number of tds already serviced */
struct usb_device *dev;
int state;
uint32_t pipe;
void *transfer_buffer;
int transfer_buffer_length;
int interval;
int actual_length;
int finished;
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
ed_t *ed;
uint16_t length; /* number of tds associated with this request */
uint16_t td_cnt; /* number of tds already serviced */
struct usb_device *dev;
int state;
uint32_t pipe;
void *transfer_buffer;
int transfer_buffer_length;
int interval;
int actual_length;
int finished;
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
} urb_priv_t;
#define URB_DEL 1
@@ -391,8 +391,8 @@ typedef struct
struct ohci_device
{
ed_t ed[NUM_EDS];
int ed_cnt;
ed_t ed[NUM_EDS];
int ed_cnt;
};
/*
@@ -404,45 +404,45 @@ struct ohci_device
typedef struct ohci
{
/* ------- common part -------- */
long handle; /* PCI BIOS */
const struct pci_device_id *ent;
int usbnum;
/* ------- common part -------- */
long handle; /* PCI BIOS */
const struct pci_device_id *ent;
int usbnum;
/* ---- end of common part ---- */
int big_endian; /* PCI BIOS */
int controller;
struct ohci_hcca *hcca_unaligned;
struct ohci_hcca *hcca; /* hcca */
td_t *td_unaligned;
struct ohci_device *ohci_dev_unaligned;
/* this allocates EDs for all possible endpoints */
struct ohci_device *ohci_dev;
int big_endian; /* PCI BIOS */
int controller;
struct ohci_hcca *hcca_unaligned;
struct ohci_hcca *hcca; /* hcca */
td_t *td_unaligned;
struct ohci_device *ohci_dev_unaligned;
/* this allocates EDs for all possible endpoints */
struct ohci_device *ohci_dev;
int irq_enabled;
int stat_irq;
int irq;
int disabled; /* e.g. got a UE, we're hung */
int sleeping;
int irq_enabled;
int stat_irq;
int irq;
int disabled; /* e.g. got a UE, we're hung */
int sleeping;
#define OHCI_FLAGS_NEC 0x80000000
uint32_t flags; /* for HC bugs */
uint32_t flags; /* for HC bugs */
uint32_t offset;
uint32_t dma_offset;
struct ohci_regs *regs; /* OHCI controller's memory */
uint32_t offset;
uint32_t dma_offset;
struct ohci_regs *regs; /* OHCI controller's memory */
int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
ed_t *ed_bulktail; /* last endpoint of bulk list */
ed_t *ed_controltail; /* last endpoint of control list */
int intrstatus;
uint32_t hc_control; /* copy of the hc control reg */
uint32_t ndp; /* copy NDP from roothub_a */
struct virt_root_hub rh;
int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
ed_t *ed_bulktail; /* last endpoint of bulk list */
ed_t *ed_controltail; /* last endpoint of control list */
int intrstatus;
uint32_t hc_control; /* copy of the hc control reg */
uint32_t ndp; /* copy NDP from roothub_a */
struct virt_root_hub rh;
const char *slot_name;
const char *slot_name;
/* device which was disconnected */
struct usb_device *devgone;
/* device which was disconnected */
struct usb_device *devgone;
} ohci_t;
/* hcd */
@@ -458,7 +458,7 @@ static ed_t * ep_add_ed(ohci_t * ohci, struct usb_device * usb_dev, uint32_t pip
static inline void ed_free(struct ed *ed)
{
ed->usb_dev = NULL;
ed->usb_dev = NULL;
}

38
include/pci.h
View File

@@ -44,13 +44,13 @@
#define PCIHTR 0x0E /* PCI Header Type Register */
#define PCIBISTR 0x0F /* PCI Build-In Self Test Register */
#define PCIBAR0 0x10 /* PCI Base Address Register for Memory
Accesses to Local, Runtime, and DMA */
Accesses to Local, Runtime, and DMA */
#define PCIBAR1 0x14 /* PCI Base Address Register for I/O
Accesses to Local, Runtime, and DMA */
Accesses to Local, Runtime, and DMA */
#define PCIBAR2 0x18 /* PCI Base Address Register for Memory
Accesses to Local Address Space 0 */
Accesses to Local Address Space 0 */
#define PCIBAR3 0x1C /* PCI Base Address Register for Memory
Accesses to Local Address Space 1 */
Accesses to Local Address Space 1 */
#define PCIBAR4 0x20 /* PCI Base Address Register, reserved */
#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */
#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/
@@ -64,7 +64,7 @@
#define PCIMLR 0x3F /* PCI Max_Lat Register */
#define PMCAPID 0x40 /* Power Management Capability ID */
#define PMNEXT 0x41 /* Power Management Next Capability
Pointer */
Pointer */
#define PMC 0x42 /* Power Management Capabilities */
#define PMCSR 0x44 /* Power Management Control/Status */
#define PMCSR_BSE 0x46 /* PMCSR Bridge Support Extensions */
@@ -74,7 +74,7 @@
#define HS_CSR 0x4A /* Hot Swap Control/Status */
#define PVPDCNTL 0x4C /* PCI Vital Product Data Control */
#define PVPD_NEXT 0x4D /* PCI Vital Product Data Next
Capability Pointer */
Capability Pointer */
#define PVPDAD 0x4E /* PCI Vital Product Data Address */
#define PVPDATA 0x50 /* PCI VPD Data */
@@ -128,18 +128,18 @@
struct pci_rd /* structure of resource descriptor */
{
unsigned short next; /* length of the following structure */
unsigned short flags; /* type of resource and misc. flags */
unsigned long start; /* start-address of resource */
unsigned long length; /* length of resource */
unsigned long offset; /* offset PCI to phys. CPU Address */
unsigned long dmaoffset; /* offset for DMA-transfers */
unsigned short next; /* length of the following structure */
unsigned short flags; /* type of resource and misc. flags */
unsigned long start; /* start-address of resource */
unsigned long length; /* length of resource */
unsigned long offset; /* offset PCI to phys. CPU Address */
unsigned long dmaoffset; /* offset for DMA-transfers */
} __attribute__ ((packed));
typedef struct /* structure of address conversion */
{
unsigned long adr; /* calculated address (CPU<->PCI) */
unsigned long len; /* length of memory range */
unsigned long adr; /* calculated address (CPU<->PCI) */
unsigned long len; /* length of memory range */
} PCI_CONV_ADR;
/******************************************************************************/
@@ -227,10 +227,14 @@ typedef struct /* structure of address conversion */
extern void init_eport(void);
extern void init_xlbus_arbiter(void);
extern void init_pci(void);
extern int pci_handle2index(int32_t handle);
extern int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index);
extern int32_t pci_find_classcode(uint32_t classcode, int index);
extern int32_t pci_get_interrupt_cause(void);
extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data);
/*
* match bits for pci_find_classcode()
*/
@@ -337,9 +341,9 @@ extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \
((bus) << 16) | \
((device << 8) | \
(function))
((bus) << 16) | \
((device << 8) | \
(function))
#define PCI_HANDLE(bus, slot, function) (0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
#define PCI_BUS_FROM_HANDLE(h) (((h) & 0xff00) >> 10)

20
include/pci_ids.h
View File

@@ -598,8 +598,10 @@
#define PCI_DEVICE_ID_NEC_VL 0x0016 /* PCI-VL Bridge */
#define PCI_DEVICE_ID_NEC_STARALPHA2 0x002c /* STAR ALPHA2 */
#define PCI_DEVICE_ID_NEC_CBUS_2 0x002d /* PCI-Cbus Bridge */
#define PCI_DEVICE_ID_NEC_USB_A 0x0031
#define PCI_DEVICE_ID_NEC_USB 0x0035 /* PCI-USB Host */
#define PCI_DEVICE_ID_NEC_USB_2 0x00e0 /* PCI-USB 2 Host */
#define PCI_DEVICE_ID_NEC_USB_3 0x00f0
#define PCI_DEVICE_ID_NEC_CBUS_3 0x003b
#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e
#define PCI_DEVICE_ID_NEC_PCX2 0x0046 /* PowerVR */
@@ -798,7 +800,7 @@
#define PCI_VENDOR_ID_ANIGMA 0x1051
#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100
#define PCI_VENDOR_ID_EFAR 0x1055
#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130
#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
@@ -1507,7 +1509,7 @@
#define PCI_VENDOR_ID_ZIATECH 0x1138
#define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550
#define PCI_VENDOR_ID_CYCLONE 0x113c
#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001
@@ -1707,8 +1709,8 @@
#define PCI_DEVICE_ID_RP8OCTA 0x0005
#define PCI_DEVICE_ID_RP8J 0x0006
#define PCI_DEVICE_ID_RP4J 0x0007
#define PCI_DEVICE_ID_RP8SNI 0x0008
#define PCI_DEVICE_ID_RP16SNI 0x0009
#define PCI_DEVICE_ID_RP8SNI 0x0008
#define PCI_DEVICE_ID_RP16SNI 0x0009
#define PCI_DEVICE_ID_RPP4 0x000A
#define PCI_DEVICE_ID_RPP8 0x000B
#define PCI_DEVICE_ID_RP8M 0x000C
@@ -1719,9 +1721,9 @@
#define PCI_DEVICE_ID_URP8INTF 0x0802
#define PCI_DEVICE_ID_URP16INTF 0x0803
#define PCI_DEVICE_ID_URP8OCTA 0x0805
#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C
#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C
#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D
#define PCI_DEVICE_ID_CRP16INTF 0x0903
#define PCI_DEVICE_ID_CRP16INTF 0x0903
#define PCI_VENDOR_ID_CYCLADES 0x120e
#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100
@@ -2143,7 +2145,7 @@
#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000
#define PCI_VENDOR_ID_ZOLTRIX 0x15b0
#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0
#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0
#define PCI_VENDOR_ID_MELLANOX 0x15b3
#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44
@@ -2288,8 +2290,8 @@
#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221
#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222
#define PCI_DEVICE_ID_INTEL_7116 0x1223
#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
#define PCI_DEVICE_ID_INTEL_7505_1 0x2552
#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
#define PCI_DEVICE_ID_INTEL_7505_1 0x2552
#define PCI_DEVICE_ID_INTEL_7205_0 0x255d
#define PCI_DEVICE_ID_INTEL_82596 0x1226
#define PCI_DEVICE_ID_INTEL_82865 0x1227

2
include/wait.h
View File

@@ -44,6 +44,8 @@
typedef bool (*checker_func)(void);
extern void wait(uint32_t);
extern void wait_us(uint32_t); /* this is just an alias to the above */
inline static void udelay(long us)
{
wait((uint32_t) us);