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fix failed alignment of pci_errata_xxx() functions which caused the code

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to hang when compiled with m68k-atari-mint-gcc
This commit is contained in:
Markus Fröschle
2016-04-04 09:31:25 +00:00
parent e73333d893
commit a409f40593
7 changed files with 741 additions and 717 deletions
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1226
BaS_gcc.files
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File diff suppressed because it is too large Load Diff

90
BaS_gcc.includes
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@@ -1,44 +1,46 @@
include
tos/jtagwait/include
tos/pci_test/include
/usr/m68k-atari-mint/include
dma
m54455
sys
pci
tos/pci_test
tos/jtagwait/m5475/mshort
m5484lite
tos/pci_test/include
tos/bascook
tos/vmem_test/m5475/mshort
i2c
fs
tos/vmem_test/m5475
tos/pci_test/m5475
spi
if
tos/jtagwait/m5475
util
kbd
flash_scripts
video
usb
exe
tos/vmem_test/sources
tos
nutil
tos/jtagwait/sources
x86emu
flash
tos/vmem_test/include
tos/bascook/sources
tos/pci_test/m5475/mshort
.
radeon
net
xhdi
tos/vmem_test
tos/pci_test/sources
firebee
tos/jtagwait
include
tos/jtagwait/include
tos/pci_test/include
/usr/m68k-atari-mint/include
/opt/cross-mint/m68k-atari-mint/include
/opt/gygwin/opt/cross-mint/m68k-atari-mint/include
dma
m54455
sys
pci
tos/pci_test
tos/jtagwait/m5475/mshort
m5484lite
tos/pci_test/include
tos/bascook
tos/vmem_test/m5475/mshort
i2c
fs
tos/vmem_test/m5475
tos/pci_test/m5475
spi
if
tos/jtagwait/m5475
util
kbd
flash_scripts
video
usb
exe
tos/vmem_test/sources
tos
nutil
tos/jtagwait/sources
x86emu
flash
tos/vmem_test/include
tos/bascook/sources
tos/pci_test/m5475/mshort
.
radeon
net
xhdi
tos/vmem_test
tos/pci_test/sources
firebee
tos/jtagwait

5
Makefile
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@@ -10,7 +10,7 @@
# can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint
# toolchain
COMPILE_ELF=Y
COMPILE_ELF=N
ifeq (Y,$(COMPILE_ELF))
TCPREFIX=m68k-elf-
@@ -52,7 +52,7 @@ CFLAGS_OPTIMIZED = -mcpu=5474 \
-Wa,--register-prefix-optional
LDFLAGS=
TRGTDIRS= ./firebee ./m5484lite
TRGTDIRS= ./firebee ./m54455 ./m5484lite
OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
TOOLDIR=util
@@ -93,6 +93,7 @@ CSRCS= \
xhdi_sd.c \
xhdi_interface.c \
pci.c \
pci_errata.c \
dspi.c \
driver_vec.c \
driver_mem.c \

2
bas.lk.in
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@@ -49,6 +49,8 @@ SECTIONS
OBJDIR/BaS.o(.text)
OBJDIR/pci.o(.text)
. = ALIGN(16);
OBJDIR/pci_errata.o(.text)
OBJDIR/pci_wrappers.o(.text)
OBJDIR/usb.o(.text)
OBJDIR/driver_mem.o(.text)

11
include/pci_errata.h Executable file
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@@ -0,0 +1,11 @@
#ifndef PCI_ERRATA_H
#define PCI_ERRATA_H
#include <stdint.h>
extern void chip_errata_135(void);
extern void chip_errata_055(int32_t handle);
#endif // PCI_ERRATA_H

60
pci/pci.c
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@@ -98,65 +98,6 @@ struct pci_interrupt
#define MAX_INTERRUPTS (NUM_CARDS * 3)
static struct pci_interrupt interrupts[MAX_INTERRUPTS];
static inline __attribute__((aligned(16))) void chip_errata_135(void)
{
/*
* Errata type: Silicon
* Affected component: PCI
* Description: When core PCI transactions that involve writes to configuration or I/O space
* are followed by a core line access to line addresses 0x4 and 0xC, core access
* to the XL bus can hang.
* Workaround: Prevent PCI configuration and I/O writes from being followed by the described
* line access by the core by generating a known good XL bus transaction after
* the PCI transaction.
* Create a dummy function which is called immediately after each of the affected
* transactions. There are three requirements for this dummy function.
* 1. The function must be aligned to a 16-byte boundary.
* 2. The function must contain a dummy write to a location on the XL bus,
* preferably one with no side effects.
* 3. The function must be longer than 32 bytes. If it is not, the function should
* be padded with 16- or 48-bit TPF instructions placed after the end of
* the function (after the RTS instruction) such that the length is longer
* than 32 bytes.
*/
__asm__ __volatile(
" .extern __MBAR \n\t"
" clr.l d0 \n\t"
" move.l d0,__MBAR+0xF0C \n\t" /* Must use direct addressing. write to EPORT module */
/* xlbus -> slavebus -> eport, writing '0' to register */
/* has no effect */
" rts \n\t"
" tpf.l #0x0 \n\t"
" tpf.l #0x0 \n\t"
" tpf.l #0x0 \n\t"
" tpf.l #0x0 \n\t"
" tpf.l #0x0 \n\t"
::: "d0", "memory");
}
static inline void chip_errata_055(int32_t handle)
{
uint32_t dummy;
return; /* test */
/* initiate PCI configuration access to device */
MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */
MCF_PCI_PCICAR_BUSNUM(3) | /* note: invalid bus number */
MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */
MCF_PCI_PCICAR_DWORD(0);
/* issue a dummy read to an unsupported bus number (will fail) */
dummy = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
/* silently clear the PCI errors we produced just now */
MCF_PCI_PCIISR = 0xffffffff; /* clear all errors */
MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE;
(void) dummy;
}
/*
* Although this pragma stuff should work according to the GCC docs, it doesn't seem to
@@ -472,6 +413,7 @@ int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value)
return PCI_SUCCESSFUL;
}
/*
* pci_get_resource
*

64
pci/pci_errata.c Executable file
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@@ -0,0 +1,64 @@
#include "pci_errata.h"
#include "pci.h"
#include <MCF5475.h>
__attribute__((aligned(16))) void chip_errata_135(void)
{
/*
* Errata type: Silicon
* Affected component: PCI
* Description: When core PCI transactions that involve writes to configuration or I/O space
* are followed by a core line access to line addresses 0x4 and 0xC, core access
* to the XL bus can hang.
* Workaround: Prevent PCI configuration and I/O writes from being followed by the described
* line access by the core by generating a known good XL bus transaction after
* the PCI transaction.
* Create a dummy function which is called immediately after each of the affected
* transactions. There are three requirements for this dummy function.
* 1. The function must be aligned to a 16-byte boundary.
* 2. The function must contain a dummy write to a location on the XL bus,
* preferably one with no side effects.
* 3. The function must be longer than 32 bytes. If it is not, the function should
* be padded with 16- or 48-bit TPF instructions placed after the end of
* the function (after the RTS instruction) such that the length is longer
* than 32 bytes.
*/
__asm__ __volatile(
" .extern __MBAR \n\t"
" clr.l d0 \n\t"
" move.l d0,__MBAR+0xF0C \n\t" /* Must use direct addressing. write to EPORT module */
/* xlbus -> slavebus -> eport, writing '0' to register */
/* has no effect */
" rts \n\t"
" tpf.l #0x0 \n\t"
" tpf.l #0x0 \n\t"
" tpf.l #0x0 \n\t"
" tpf.l #0x0 \n\t"
" tpf.l #0x0 \n\t"
::: "d0", "memory");
}
void chip_errata_055(int32_t handle)
{
uint32_t dummy;
return; /* test */
/* initiate PCI configuration access to device */
MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */
MCF_PCI_PCICAR_BUSNUM(3) | /* note: invalid bus number */
MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */
MCF_PCI_PCICAR_DWORD(0);
/* issue a dummy read to an unsupported bus number (will fail) */
dummy = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
/* silently clear the PCI errors we produced just now */
MCF_PCI_PCIISR = 0xffffffff; /* clear all errors */
MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE;
(void) dummy;
}