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modified PCI configuration, RADEON card does not configure correctly

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This commit is contained in:
Markus Fröschle
2015-02-22 19:46:16 +00:00
parent efc3a775ee
commit 9d78f96c13
12 changed files with 2529 additions and 2467 deletions
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9
BaS_gcc/BaS_gcc.files
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@@ -207,3 +207,12 @@ util/setjmp.S
include/x86emu_regs.h include/x86emu_regs.h
x86emu/x86emu_util.c x86emu/x86emu_util.c
include/setjmp.h include/setjmp.h
video/video.c
video/fbmem.c
video/fbmodedb.c
video/fbmon.c
video/fnt_st_8x16.c
video/offscreen.c
video/vdi_fill.c
video/videl.c
video/video.c

3
BaS_gcc/Makefile
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@@ -47,6 +47,9 @@ CFLAGS=-mcpu=5474 \
CFLAGS_OPTIMIZED = -mcpu=5474 \ CFLAGS_OPTIMIZED = -mcpu=5474 \
-Wall \ -Wall \
-O2 \ -O2 \
-ffixed-a3 \
-ffixed-a4 \
-ffixed-a5 \
-g \ -g \
-fomit-frame-pointer \ -fomit-frame-pointer \
-ffreestanding \ -ffreestanding \

4
BaS_gcc/include/pci.h
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@@ -194,8 +194,8 @@ typedef struct /* structure of address conversion */
#define PCI_COMMAND(i) (((i) >> 16) & 0xffff) #define PCI_COMMAND(i) (((i) >> 16) & 0xffff)
/* register 0x08 macros */ /* register 0x08 macros */
#define PCI_CLASS_CODE(i) ((swpl((i)) & 0xffff0000) >> 16) #define PCI_CLASS_CODE(i) ((swpl((i)) & 0xff000000) >> 24)
#define PCI_SUBCLASS(i) ((swpl((i)) & 0xffffff00) >> 8) #define PCI_SUBCLASS(i) ((swpl((i)) & 0xffff0000) >> 16)
#define PCI_PROG_IF(i) ((swpl((i)) & 0x0000ff00) >> 8) #define PCI_PROG_IF(i) ((swpl((i)) & 0x0000ff00) >> 8)
#define PCI_REVISION_ID(i) ((swpl((i)) & 0x000000ff)) #define PCI_REVISION_ID(i) ((swpl((i)) & 0x000000ff))

28
BaS_gcc/pci/pci.c
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@@ -33,7 +33,7 @@
#include "interrupts.h" #include "interrupts.h"
#include "wait.h" #include "wait.h"
//#define DEBUG_PCI #define DEBUG_PCI
#ifdef DEBUG_PCI #ifdef DEBUG_PCI
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else #else
@@ -333,7 +333,7 @@ uint32_t pci_read_config_longword(int32_t handle, int offset)
/* finish PCI configuration access special cycle (allow regular PCI accesses) */ /* finish PCI configuration access special cycle (allow regular PCI accesses) */
MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E; MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
pci_check_status(); //pci_check_status();
return value; return value;
} }
@@ -593,6 +593,11 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
{ {
value = pci_read_config_longword(handle, PCICCR); value = pci_read_config_longword(handle, PCICCR);
dbg("classcode to search for=%x\r\n", classcode);
dbg("PCI_CLASSCODE found=%x\r\n", PCI_CLASS_CODE(value));
dbg("PCI_SUBCLASS found=%x\r\n", PCI_SUBCLASS(value));
dbg("PCI_PROG_IF found=%x\r\n", PCI_PROG_IF(value));
if ((classcode & (1 << 26) ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) && if ((classcode & (1 << 26) ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
(classcode & (1 << 25) ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) && (classcode & (1 << 25) ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
(classcode & (1 << 24) ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true)) (classcode & (1 << 24) ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true))
@@ -930,7 +935,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
/* fill resource descriptor */ /* fill resource descriptor */
rd->next = sizeof(struct pci_rd); rd->next = sizeof(struct pci_rd);
rd->flags = 0 | FLG_32BIT | FLG_16BIT | FLG_8BIT | 2; /* little endian, lane swapped */ rd->flags = 0 | FLG_32BIT | FLG_16BIT | FLG_8BIT | ORD_INTEL_LS; /* little endian, lane swapped */
rd->start = address; rd->start = address;
rd->length = size; rd->length = size;
rd->offset = 0; rd->offset = 0;
@@ -1222,15 +1227,21 @@ void init_pci(void)
/* Configure Initiator Windows */ /* Configure Initiator Windows */
/* initiator window 0 base / translation adress register */ /*
MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET | (((PCI_MEMORY_SIZE - 1) >> 8) & 0xffff0000)) * initiator window 0 base / translation adress register
| ((PCI_MEMORY_OFFSET >> 16) & 0xff00); * used for PCI memory access
*/
MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8))
+ (PCI_MEMORY_OFFSET >> 16);
NOP(); NOP();
dbg("PCIIW0BTAR=0x%08x\r\n", MCF_PCI_PCIIW0BTAR); dbg("PCIIW0BTAR=0x%08x\r\n", MCF_PCI_PCIIW0BTAR);
/* initiator window 1 base / translation adress register */ /*
MCF_PCI_PCIIW1BTAR = (PCI_IO_OFFSET | ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000; * initiator window 1 base / translation adress register
* used for PCI I/O access
*/
MCF_PCI_PCIIW1BTAR = (PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000;
NOP(); NOP();
/* initiator window 2 base / translation address register */ /* initiator window 2 base / translation address register */
MCF_PCI_PCIIW2BTAR = 0L; /* not used */ MCF_PCI_PCIIW2BTAR = 0L; /* not used */
@@ -1241,6 +1252,7 @@ void init_pci(void)
MCF_PCI_PCIIWCR_WINCTRL0_E | MCF_PCI_PCIIWCR_WINCTRL0_E |
MCF_PCI_PCIIWCR_WINCTRL1_E; MCF_PCI_PCIIWCR_WINCTRL1_E;
NOP(); NOP();
/* /*
* Initialize target control register. * Initialize target control register.
* Used when an external bus master accesses the Coldfire PCI as target * Used when an external bus master accesses the Coldfire PCI as target

203
BaS_gcc/radeon/radeon_base.c
View File

@@ -59,14 +59,16 @@
#include "ati_ids.h" #include "ati_ids.h"
#include "driver_mem.h" #include "driver_mem.h"
#include "bas_printf.h" #include "bas_printf.h"
#include "bas_string.h"
#include "exceptions.h" /* for set_ipl() */ #include "exceptions.h" /* for set_ipl() */
#define DBG_RADEON #define DBG_RADEON
#ifdef DBG_RADEON #ifdef DBG_RADEON
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0) #define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
#else #else
#define dbg(format, arg...) do {;} while (0) #define dbg(format, arg...) do {;} while (0)
#endif /* DBG_RADEON */ #endif /* DBG_RADEON */
#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0)
extern void run_bios(struct radeonfb_info *rinfo); extern void run_bios(struct radeonfb_info *rinfo);
@@ -239,7 +241,8 @@ extern struct fb_info *info_fb;
#define rinfo ((struct radeonfb_info *) info_fb->par) #define rinfo ((struct radeonfb_info *) info_fb->par)
static uint32_t inreg(uint32_t addr) static uint32_t inreg(uint32_t addr)
{ {
return INREG(addr); return swpl(*(uint32_t *)(rinfo->mmio_base + addr));
//return INREG(addr);
} }
static void outreg(uint32_t addr, uint32_t val) static void outreg(uint32_t addr, uint32_t val)
@@ -360,7 +363,13 @@ static int radeon_map_ROM(struct radeonfb_info *rinfo)
uint32_t temp; uint32_t temp;
temp = INREG(MPP_TB_CONFIG); dbg("mmio_base=%p\r\n", rinfo->mmio_base);
dbg("bios_seg=%p\r\n", rinfo->bios_seg);
dbg("bios_seg_phys=%p\r\n", rinfo->bios_seg_phys);
temp = inreg(MPP_TB_CONFIG);
dbg("temp=%d\r\n", temp);
temp &= 0x00ffffffu; temp &= 0x00ffffffu;
temp |= 0x04 << 24; temp |= 0x04 << 24;
OUTREG(MPP_TB_CONFIG, temp); OUTREG(MPP_TB_CONFIG, temp);
@@ -368,21 +377,22 @@ static int radeon_map_ROM(struct radeonfb_info *rinfo)
if (rinfo->bios_seg == NULL) if (rinfo->bios_seg == NULL)
{ {
dbg("%s: ROM failed to map\r\n", __FUNCTION__); dbg("ROM failed to map\r\n");
return -1; return -1;
} }
/* Very simple test to make sure it appeared */ /* Very simple test to make sure it appeared */
if (BIOS_IN16(0) != 0xaa55) if (BIOS_IN16(0) != 0xaa55)
{ {
dbg("%s: Invalid ROM signature", __FUNCTION__); dbg("Invalid ROM signature");
goto failed; goto failed;
} }
/* Look for the PCI data to check the ROM type */ /* Look for the PCI data to check the ROM type */
dptr = BIOS_IN16(0x18); dptr = BIOS_IN16(0x18);
/* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM /*
* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
* for now, until I've verified this works everywhere. The goal here is more * for now, until I've verified this works everywhere. The goal here is more
* to phase out Open Firmware images. * to phase out Open Firmware images.
* *
@@ -408,35 +418,35 @@ static int radeon_map_ROM(struct radeonfb_info *rinfo)
*/ */
if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P'))
{ {
dbg("%s: PCI DATA signature in ROM incorrect: %p\r\n", __FUNCTION__, BIOS_IN32(dptr)); dbg("PCI DATA signature in ROM incorrect: %p\r\n", BIOS_IN32(dptr));
goto anyway; goto anyway;
} }
rom_type = BIOS_IN8(dptr + 0x14); rom_type = BIOS_IN8(dptr + 0x14);
switch(rom_type) switch(rom_type)
{ {
case 0: case 0:
dbg("%s: Found Intel x86 BIOS ROM Image\r\n", __FUNCTION__); dbg("Found Intel x86 BIOS ROM Image\r\n");
break; break;
case 1: case 1:
dbg("%s: Found Open Firmware ROM Image\r\n", __FUNCTION__); dbg("Found Open Firmware ROM Image\r\n");
goto failed; goto failed;
case 2: case 2:
dbg("%s: Found HP PA-RISC ROM Image\r\n", __FUNCTION__); dbg("Found HP PA-RISC ROM Image\r\n");
goto failed; goto failed;
default: default:
dbg("%s: Found unknown type %d ROM Image\r\n", rom_type, __FUNCTION__); dbg("Found unknown type %d ROM Image\r\n", rom_type);
goto failed; goto failed;
} }
anyway: anyway:
/* Locate the flat panel infos, do some sanity checking !!! */ /* Locate the flat panel infos, do some sanity checking !!! */
rinfo->fp_bios_start = BIOS_IN16(0x48); rinfo->fp_bios_start = BIOS_IN16(0x48);
dbg("%s: BIOS start offset: %p\r\n", __FUNCTION__, BIOS_IN16(0x48)); dbg("BIOS start offset: %p\r\n", BIOS_IN16(0x48));
/* Save BIOS PLL informations */ /* Save BIOS PLL informations */
{ {
uint16_t pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); uint16_t pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
dbg("%s: BIOS PLL info block offset: %p\r\n", __FUNCTION__, BIOS_IN16(rinfo->fp_bios_start + 0x30)); dbg("BIOS PLL info block offset: %p\r\n", BIOS_IN16(rinfo->fp_bios_start + 0x30));
rinfo->bios_pll.sclk = BIOS_IN16(pll_info_block + 0x08); rinfo->bios_pll.sclk = BIOS_IN16(pll_info_block + 0x08);
rinfo->bios_pll.mclk = BIOS_IN16(pll_info_block + 0x0a); rinfo->bios_pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
rinfo->bios_pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); rinfo->bios_pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
@@ -470,7 +480,7 @@ static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
* Ugh, we cut interrupts, bad bad bad, but we want some precision * Ugh, we cut interrupts, bad bad bad, but we want some precision
* here, so... --BenH * here, so... --BenH
*/ */
dbg("%s: radeon_probe_pll_params\r\n", __FUNCTION__); dbg("radeon_probe_pll_params\r\n");
/* Flush PCI buffers ? */ /* Flush PCI buffers ? */
tmp = INREG16(DEVICE_ID); tmp = INREG16(DEVICE_ID);
@@ -515,15 +525,15 @@ static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
set_ipl(ipl); set_ipl(ipl);
hz = US_TO_TIMER(1000000.0) / (double)(stop_tv - start_tv); hz = US_TO_TIMER(1000000.0) / (double)(stop_tv - start_tv);
dbg("%s:hz %d\r\n", __FUNCTION__, (int32_t) hz); dbg("hz %d\r\n", (int32_t) hz);
hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1); vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
dbg("%s:hTotal=%d\r\n", __FUNCTION__, hTotal); dbg("hTotal=%d\r\n", hTotal);
dbg("%s:vTotal=%d\r\n", __FUNCTION__, vTotal); dbg("vTotal=%d\r\n", vTotal);
vclk = (double) hTotal * (double) vTotal * hz; vclk = (double) hTotal * (double) vTotal * hz;
dbg("%s:vclk=%d\r\n", __FUNCTION__, (int) vclk); dbg("vclk=%d\r\n", (int) vclk);
switch ((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) switch ((INPLL(PPLL_REF_DIV) & 0x30000) >> 16)
{ {
@@ -595,7 +605,7 @@ static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
xtal = 2950; xtal = 2950;
else else
{ {
dbg("%s: xtal calculation failed: %d\r\n", __FUNCTION__, xtal); dbg("xtal calculation failed: %d\r\n", xtal);
return -1; /* error */ return -1; /* error */
} }
@@ -628,7 +638,7 @@ static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
* incomplete, however. It does provide ppll_max and _min values * incomplete, however. It does provide ppll_max and _min values
* even for most other methods, however. * even for most other methods, however.
*/ */
dbg("%s:\r\n", __FUNCTION__); dbg("\r\n");
switch(rinfo->chipset) switch(rinfo->chipset)
{ {
@@ -701,7 +711,7 @@ static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
rinfo->pll.ref_div = rinfo->bios_pll.ref_div; rinfo->pll.ref_div = rinfo->bios_pll.ref_div;
rinfo->pll.ppll_min = rinfo->bios_pll.ppll_min; rinfo->pll.ppll_min = rinfo->bios_pll.ppll_min;
rinfo->pll.ppll_max = rinfo->bios_pll.ppll_max; rinfo->pll.ppll_max = rinfo->bios_pll.ppll_max;
dbg("%s: Retreived PLL infos from BIOS\r\n", __FUNCTION__); dbg("Retreived PLL infos from BIOS\r\n");
goto found; goto found;
} }
@@ -712,14 +722,14 @@ static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
*/ */
if (radeon_probe_pll_params(rinfo) == 0) if (radeon_probe_pll_params(rinfo) == 0)
{ {
dbg("%s: Retreived PLL infos from registers\r\n", __FUNCTION__); dbg("Retreived PLL infos from registers\r\n");
goto found; goto found;
} }
/* /*
* Fall back to already-set defaults... * Fall back to already-set defaults...
*/ */
dbg("%s: Used default PLL infos\r\n", __FUNCTION__); dbg("Used default PLL infos\r\n");
found: found:
/* /*
@@ -732,9 +742,9 @@ found:
if (rinfo->pll.sclk == 0) if (rinfo->pll.sclk == 0)
rinfo->pll.sclk = 20000; rinfo->pll.sclk = 20000;
dbg("%s: Reference=%d MHz (RefDiv=0x%x) Memory=%d MHz\r\n", __FUNCTION__, dbg("Reference=%d MHz (RefDiv=0x%x) Memory=%d MHz\r\n",
rinfo->pll.ref_clk / 100, rinfo->pll.ref_div, rinfo->pll.mclk / 100); rinfo->pll.ref_clk / 100, rinfo->pll.ref_div, rinfo->pll.mclk / 100);
dbg("%s: System=%d MHz PLL min %d, max %d\r\n", __FUNCTION__, dbg("System=%d MHz PLL min %d, max %d\r\n",
rinfo->pll.sclk / 100, rinfo->pll.ppll_min, rinfo->pll.ppll_max); rinfo->pll.sclk / 100, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
} }
@@ -753,13 +763,13 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
int nom, den; int nom, den;
uint32_t pitch; uint32_t pitch;
dbg("%s:\r\n", __FUNCTION__); dbg("\r\n");
/* clocks over 135 MHz have heat isues with DVI on RV100 */ /* clocks over 135 MHz have heat isues with DVI on RV100 */
if ((rinfo->mon1_type == MT_DFP) && (rinfo->family == CHIP_FAMILY_RV100) && ((100000000 / var->pixclock) > 13500)) if ((rinfo->mon1_type == MT_DFP) && (rinfo->family == CHIP_FAMILY_RV100) && ((100000000 / var->pixclock) > 13500))
{ {
dbg("%s: mode %d x %d x %d", __FUNCTION__, var->xres, var->yres, var->bits_per_pixel); dbg("mode %d x %d x %d", var->xres, var->yres, var->bits_per_pixel);
dbg("%s: rejected, RV100 DVI clock over 135 MHz\r\n", __FUNCTION__); dbg("rejected, RV100 DVI clock over 135 MHz\r\n");
return -1; //-EINVAL; return -1; //-EINVAL;
} }
@@ -862,7 +872,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
if (((v.xres_virtual * v.yres_virtual * nom) / den) > info->screen_size) if (((v.xres_virtual * v.yres_virtual * nom) / den) > info->screen_size)
{ {
dbg("%s: mode %d x %d rejected (screen size too small)\r\n", __FUNCTION__, v.xres_virtual, v.yres_virtual); dbg("mode %d x %d rejected (screen size too small)\r\n", v.xres_virtual, v.yres_virtual);
return -1; //-EINVAL; return -1; //-EINVAL;
} }
@@ -884,7 +894,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
v.red.msb_right = v.green.msb_right = v.blue.msb_right = 0; v.red.msb_right = v.green.msb_right = v.blue.msb_right = 0;
v.transp.offset = v.transp.length = v.transp.msb_right = 0; v.transp.offset = v.transp.length = v.transp.msb_right = 0;
dbg("%s: using mode %d x %d \r\n", __FUNCTION__, v.xres, v.yres); dbg("using mode %d x %d \r\n", v.xres, v.yres);
memcpy(var, &v, sizeof(v)); memcpy(var, &v, sizeof(v));
@@ -1986,8 +1996,8 @@ static int radeon_set_fbinfo(struct radeonfb_info *rinfo)
else if (info->screen_size > MIN_MAPPED_VRAM) else if (info->screen_size > MIN_MAPPED_VRAM)
info->screen_size = MIN_MAPPED_VRAM; info->screen_size = MIN_MAPPED_VRAM;
dbg("%s: ram_base %p\r\n", __FUNCTION__, info->screen_base); dbg("ram_base %p\r\n", info->screen_base);
dbg("%s: ram_size %p\r\n", __FUNCTION__, info->ram_size); dbg("ram_size %p\r\n", info->ram_size);
/* Fill fix common fields */ /* Fill fix common fields */
memcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); memcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
@@ -2089,24 +2099,24 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
*/ */
switch(rinfo->family) switch(rinfo->family)
{ {
case CHIP_FAMILY_LEGACY: dbg("%s chip type: %s\r\n", __FUNCTION__, "LEGACY"); break; case CHIP_FAMILY_LEGACY: dbg("chip type: %s\r\n", "LEGACY"); break;
case CHIP_FAMILY_RADEON: dbg("%s chip type: %s\r\n", __FUNCTION__, "RADEON"); break; case CHIP_FAMILY_RADEON: dbg("chip type: %s\r\n", "RADEON"); break;
case CHIP_FAMILY_RV100: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV100"); break; case CHIP_FAMILY_RV100: dbg("chip type: %s\r\n", "RV100"); break;
case CHIP_FAMILY_RS100: dbg("%s chip type: %s\r\n", __FUNCTION__, "RS100"); break; case CHIP_FAMILY_RS100: dbg("chip type: %s\r\n", "RS100"); break;
case CHIP_FAMILY_RV200: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV200"); break; case CHIP_FAMILY_RV200: dbg("chip type: %s\r\n", "RV200"); break;
case CHIP_FAMILY_RS200: dbg("%s chip type: %s\r\n", __FUNCTION__, "RS200"); break; case CHIP_FAMILY_RS200: dbg("chip type: %s\r\n", "RS200"); break;
case CHIP_FAMILY_R200: dbg("%s chip type: %s\r\n", __FUNCTION__, "R200"); break; case CHIP_FAMILY_R200: dbg("chip type: %s\r\n", "R200"); break;
case CHIP_FAMILY_RV250: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV250"); break; case CHIP_FAMILY_RV250: dbg("chip type: %s\r\n", "RV250"); break;
case CHIP_FAMILY_RS300: dbg("%s chip type: %s\r\n", __FUNCTION__, "RS300"); break; case CHIP_FAMILY_RS300: dbg("chip type: %s\r\n", "RS300"); break;
case CHIP_FAMILY_RV280: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV280"); break; case CHIP_FAMILY_RV280: dbg("chip type: %s\r\n", "RV280"); break;
case CHIP_FAMILY_R300: dbg("%s chip type: %s\r\n", __FUNCTION__, "R300"); break; case CHIP_FAMILY_R300: dbg("chip type: %s\r\n", "R300"); break;
case CHIP_FAMILY_R350: dbg("%s chip type: %s\r\n", __FUNCTION__, "R350"); break; case CHIP_FAMILY_R350: dbg("chip type: %s\r\n", "R350"); break;
case CHIP_FAMILY_RV350: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV350"); break; case CHIP_FAMILY_RV350: dbg("chip type: %s\r\n", "RV350"); break;
case CHIP_FAMILY_RV380: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV380"); break; case CHIP_FAMILY_RV380: dbg("chip type: %s\r\n", "RV380"); break;
case CHIP_FAMILY_R420: dbg("%s chip type: %s\r\n", __FUNCTION__, "R420"); break; case CHIP_FAMILY_R420: dbg("chip type: %s\r\n", "R420"); break;
default: dbg("%s chip type: %s\r\n", "UNKNOW"); break; default: dbg("chip type: %s\r\n", "UNKNOW"); break;
} }
dbg("%s: found %d KB of %d bits wide %s video RAM\r\n", __FUNCTION__, rinfo->video_ram / 1024, dbg("found %d KB of %d bits wide %s video RAM\r\n", rinfo->video_ram / 1024,
rinfo->vram_width, rinfo->vram_ddr ? "DDR " : "SDRAM "); rinfo->vram_width, rinfo->vram_ddr ? "DDR " : "SDRAM ");
} }
@@ -2116,11 +2126,11 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
struct radeonfb_info *rinfo; struct radeonfb_info *rinfo;
struct pci_rd *pci_rsc_desc; struct pci_rd *pci_rsc_desc;
dbg("%s:\r\n", __FUNCTION__); dbg("\r\n");
info = framebuffer_alloc(sizeof(struct radeonfb_info)); info = framebuffer_alloc(sizeof(struct radeonfb_info));
if (!info) if (!info)
{ {
dbg("%s: could not allocate frame buffer\r\n", __FUNCTION__); dbg("could not allocate frame buffer\r\n");
return -1; // -ENOMEM; return -1; // -ENOMEM;
} }
@@ -2128,8 +2138,11 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
rinfo->info = info; rinfo->info = info;
rinfo->handle = handle; rinfo->handle = handle;
strcpy((char *) rinfo->name, "ATI Radeon XX ");
rinfo->name[11] = (char) (ent->device >> 8); rinfo->name[11] = (char) (ent->device >> 8);
rinfo->name[12] = (char) ent->device; rinfo->name[12] = (char) ent->device;
rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
rinfo->chipset = ent->device; rinfo->chipset = ent->device;
rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
@@ -2137,7 +2150,7 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
/* Set base addrs */ /* Set base addrs */
dbg("%s: Set base addrs\r\n", __FUNCTION__); dbg("Set base addrs\r\n");
rinfo->fb_base_phys = rinfo->mmio_base_phys = rinfo->io_base_phys = 0xFFFFFFFF; rinfo->fb_base_phys = rinfo->mmio_base_phys = rinfo->io_base_phys = 0xFFFFFFFF;
rinfo->mapped_vram = 0; rinfo->mapped_vram = 0;
rinfo->mmio_base = rinfo->io_base = NULL; rinfo->mmio_base = rinfo->io_base = NULL;
@@ -2149,10 +2162,10 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
uint16_t flags; uint16_t flags;
do do
{ {
dbg("%s: flags %p\r\n", __FUNCTION__, pci_rsc_desc->flags); dbg("flags %p\r\n", pci_rsc_desc->flags);
dbg("%s: start %p\r\n", __FUNCTION__, pci_rsc_desc->start); dbg(" start %p\r\n", pci_rsc_desc->start);
dbg("%s: offset 0x%x\r\n", __FUNCTION__, pci_rsc_desc->offset); dbg(" offset 0x%x\r\n", pci_rsc_desc->offset);
dbg("%s: length 0x%x\r\n", __FUNCTION__, pci_rsc_desc->length); dbg(" length 0x%x\r\n", pci_rsc_desc->length);
if (!(pci_rsc_desc->flags & FLG_IO)) if (!(pci_rsc_desc->flags & FLG_IO))
{ {
@@ -2165,30 +2178,44 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
if ((pci_rsc_desc->flags & FLG_ENDMASK) == ORD_MOTOROLA) if ((pci_rsc_desc->flags & FLG_ENDMASK) == ORD_MOTOROLA)
{ {
rinfo->big_endian = 0; /* host bridge make swapping intel -> motorola */ rinfo->big_endian = 0; /* host bridge make swapping intel -> motorola */
dbg("%s: host bridge is big endian\r\n", __FUNCTION__); dbg("host bridge is big endian\r\n");
} }
else else
{ {
rinfo->big_endian = 1; /* radeon make swapping intel -> motorola */ rinfo->big_endian = 1; /* radeon make swapping intel -> motorola */
dbg("%s: host bridge is little endian\r\n", __FUNCTION__); dbg("host bridge is little endian\r\n");
} }
xprintf("framebuffer dump:\r\n");
hexdump((uint8_t *) rinfo->fb_base_phys, 0x10);
xprintf("change framebuffer contents\r\n");
* (uint32_t *) rinfo->fb_base_phys = 0x01234567;
* (uint32_t *) (rinfo->fb_base_phys + 8) = 0x89abcdef;
hexdump((uint8_t *) rinfo->fb_base_phys, 0x10);
} }
else if ((pci_rsc_desc->length >= RADEON_REGSIZE) && (pci_rsc_desc->length < 0x100000)) else if ((pci_rsc_desc->length >= RADEON_REGSIZE) && (pci_rsc_desc->length < 0x100000))
{ {
if (pci_rsc_desc->flags & FLG_ROM) if (pci_rsc_desc->flags & FLG_ROM)
{ {
dbg("%s: FLG_ROM resource descriptor found\r\n", __FUNCTION__); dbg("FLG_ROM resource descriptor found\r\n");
dbg("%s: start = %p, size = 0x%x\r\n", __FUNCTION__, pci_rsc_desc->start, pci_rsc_desc->length); dbg(" start = %p, size = 0x%x\r\n", pci_rsc_desc->start, pci_rsc_desc->length);
dbg("%s: bios_seg = %p\r\n", __FUNCTION__, rinfo->bios_seg); dbg(" bios_seg = %p\r\n", rinfo->bios_seg);
if (rinfo->bios_seg == NULL) if (rinfo->bios_seg == NULL)
{ {
rinfo->bios_seg_phys = pci_rsc_desc->start; rinfo->bios_seg_phys = pci_rsc_desc->start;
if (BIOS_IN16(0) == 0xaa55) if (BIOS_IN16(0) == 0xaa55)
{
rinfo->bios_seg = (void *) (pci_rsc_desc->offset + pci_rsc_desc->start); rinfo->bios_seg = (void *) (pci_rsc_desc->offset + pci_rsc_desc->start);
}
else else
{ {
dbg("%s: BIOS_IN16(0) was %x (expected 0xaa55)\r\n", __FUNCTION__, BIOS_IN16(0)); dbg("rinfo->bios_seg[0] (%p) was %x (expected 0xaa55)\r\n",
rinfo->bios_seg_phys, * (uint16_t *) rinfo->bios_seg_phys);
xprintf("bios_seg_phys dump:\r\n");
hexdump((uint8_t *) rinfo->bios_seg_phys, 0x100);
rinfo->bios_seg_phys = 0; rinfo->bios_seg_phys = 0;
} }
} }
@@ -2199,6 +2226,9 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
{ {
rinfo->mmio_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start); rinfo->mmio_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start);
rinfo->mmio_base_phys = pci_rsc_desc->start; rinfo->mmio_base_phys = pci_rsc_desc->start;
xprintf("mmio_base dump:\r\n");
hexdump((uint8_t *) rinfo->mmio_base_phys, 0x100);
} }
} }
} }
@@ -2209,6 +2239,9 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
{ {
rinfo->io_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start); rinfo->io_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start);
rinfo->io_base_phys = pci_rsc_desc->start; rinfo->io_base_phys = pci_rsc_desc->start;
xprintf("io_base dump:\r\n");
hexdump((uint8_t *) rinfo->io_base_phys, 0x100);
} }
} }
flags = pci_rsc_desc->flags; flags = pci_rsc_desc->flags;
@@ -2216,24 +2249,24 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
} while (!(flags & FLG_LAST)); } while (!(flags & FLG_LAST));
} }
else else
dbg("%s: get_resource error\r\n", __FUNCTION__); dbg("get_resource error\r\n");
/* map the regions */ /* map the regions */
dbg("%s: map memory regions\r\n", __FUNCTION__); dbg("map memory regions\r\n");
if (rinfo->mmio_base == NULL) if (rinfo->mmio_base == NULL)
{ {
dbg("%s: cannot map MMIO\r\n", __FUNCTION__); dbg("cannot map MMIO\r\n");
framebuffer_release(info); framebuffer_release(info);
return -2; //(-EIO); return -2; //(-EIO);
} }
dbg("%s: mmio_base_phys %p, mmio_base %p\r\n", __FUNCTION__, rinfo->mmio_base_phys, rinfo->mmio_base); dbg("mmio_base_phys %p, mmio_base %p\r\n", rinfo->mmio_base_phys, rinfo->mmio_base);
dbg("%s: io_base_phys %p, io_base %p\r\n", __FUNCTION__, rinfo->io_base_phys, rinfo->io_base); dbg("io_base_phys %p, io_base %p\r\n", rinfo->io_base_phys, rinfo->io_base);
dbg("%s: fb_base_phys %p, fb_base %p\r\n", __FUNCTION__, rinfo->fb_base_phys, rinfo->fb_base); dbg("fb_base_phys %p, fb_base %p\r\n", rinfo->fb_base_phys, rinfo->fb_base);
/* /*
* Check for errata * Check for errata
*/ */
dbg("%s: check for errata\r\n", __FUNCTION__); dbg("check for errata\r\n");
rinfo->errata = 0; rinfo->errata = 0;
if (rinfo->family == CHIP_FAMILY_R300 if (rinfo->family == CHIP_FAMILY_R300
&& (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) == CFG_ATI_REV_A11) && (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) == CFG_ATI_REV_A11)
@@ -2249,22 +2282,22 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
* Map the BIOS ROM if any and retreive PLL parameters from * Map the BIOS ROM if any and retreive PLL parameters from
* the BIOS. * the BIOS.
*/ */
dbg("%s: bios_seg_phys %p\r\n", __FUNCTION__, rinfo->bios_seg_phys); dbg("bios_seg_phys %p\r\n", rinfo->bios_seg_phys);
dbg("%s: map the BIOS ROM\r\n", __FUNCTION__); dbg("map the BIOS ROM\r\n");
radeon_map_ROM(rinfo); radeon_map_ROM(rinfo);
/* Run VGA BIOS */ /* Run VGA BIOS */
if ((rinfo->bios_seg != NULL)) if ((rinfo->bios_seg != NULL))
{ {
dbg("%s: run VGA BIOS\r\n", __FUNCTION__); dbg("run VGA BIOS\r\n");
run_bios(rinfo); run_bios(rinfo);
} }
else else
{ {
dbg("%s: could not run VGA bios - rinfo->bios_seg is NULL\r\n", __FUNCTION__); dbg("could not run VGA bios - rinfo->bios_seg is NULL\r\n");
} }
dbg("%s: fixup display base address \r\n", __FUNCTION__); dbg("fixup display base address \r\n");
OUTREG(MC_FB_LOCATION, 0x7fff0000); OUTREG(MC_FB_LOCATION, 0x7fff0000);
rinfo->fb_local_base = 0; rinfo->fb_local_base = 0;
@@ -2279,52 +2312,52 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
OUTREG(OV0_BASE_ADDR, 0); OUTREG(OV0_BASE_ADDR, 0);
/* Get VRAM size and type */ /* Get VRAM size and type */
dbg("%s: get VRAM size\r\n", __FUNCTION__); dbg("get VRAM size\r\n");
radeon_identify_vram(rinfo); radeon_identify_vram(rinfo);
if ((rinfo->fb_base == NULL) if ((rinfo->fb_base == NULL)
|| ((rinfo->video_ram > rinfo->mapped_vram) && (rinfo->mapped_vram < MIN_MAPPED_VRAM * 2))) || ((rinfo->video_ram > rinfo->mapped_vram) && (rinfo->mapped_vram < MIN_MAPPED_VRAM * 2)))
{ {
dbg("%s: cannot map FB, video ram: %d KB\r\n", __FUNCTION__, rinfo->mapped_vram / 1024); dbg("cannot map FB, video ram: %d KB\r\n", rinfo->mapped_vram / 1024);
framebuffer_release(info); framebuffer_release(info);
return -2; //(-EIO); return -2; //(-EIO);
} }
else else
{ {
dbg("%s: %d KB of VRAM mapped to %p\r\n", __FUNCTION__, rinfo->mapped_vram / 1024, rinfo->fb_base); dbg("%d KB of VRAM mapped to %p\r\n", rinfo->mapped_vram / 1024, rinfo->fb_base);
} }
/* Get informations about the board's PLL */ /* Get informations about the board's PLL */
dbg("%s: get informations about the board's PLL\r\n", __FUNCTION__); dbg("get informations about the board's PLL\r\n");
radeon_get_pllinfo(rinfo); radeon_get_pllinfo(rinfo);
#ifdef CONFIG_FB_RADEON_I2C #ifdef CONFIG_FB_RADEON_I2C
/* Register I2C bus */ /* Register I2C bus */
dbg("%s: register I2C bus\r\n", __FUNCTION__); dbg("register I2C bus\r\n");
radeon_create_i2c_busses(rinfo); radeon_create_i2c_busses(rinfo);
#endif /* CONFIG_FB_RADEON_I2C */ #endif /* CONFIG_FB_RADEON_I2C */
/* set all the vital stuff */ /* set all the vital stuff */
dbg("%s: set all the vital stuff\r\n", __FUNCTION__); dbg("set all the vital stuff\r\n");
radeon_set_fbinfo(rinfo); radeon_set_fbinfo(rinfo);
/* set offscreen memory descriptor */ /* set offscreen memory descriptor */
dbg("%s: set offscreen memory descriptor\r\n", __FUNCTION__); dbg("set offscreen memory descriptor\r\n");
offscreen_init(info); offscreen_init(info);
/* Probe screen types */ /* Probe screen types */
dbg("%s: probe screen types, monitor_layout: 0x%x\r\n", __FUNCTION__, monitor_layout); dbg("probe screen types, monitor_layout: 0x%x\r\n", monitor_layout);
radeon_probe_screens(rinfo, monitor_layout, (int) ignore_edid); radeon_probe_screens(rinfo, monitor_layout, (int) ignore_edid);
/* Build mode list, check out panel native model */ /* Build mode list, check out panel native model */
dbg("%s: build mode list\r\n", __FUNCTION__); dbg("build mode list\r\n");
radeon_check_modes(rinfo, &resolution); radeon_check_modes(rinfo, &resolution);
/* /*
* save current mode regs before we switch into the new one * save current mode regs before we switch into the new one
* so we can restore this upon exit * so we can restore this upon exit
*/ */
dbg("%s: save current mode\r\n", __FUNCTION__); dbg("save current mode\r\n");
radeon_save_state(rinfo, &rinfo->init_state); radeon_save_state(rinfo, &rinfo->init_state);
memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
@@ -2332,7 +2365,7 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
// DPRINT("radeonfb: radeonfb_pci_register: setup power management\r\n"); // DPRINT("radeonfb: radeonfb_pci_register: setup power management\r\n");
// radeonfb_pm_init(rinfo, (int)default_dynclk); // radeonfb_pm_init(rinfo, (int)default_dynclk);
dbg("%s: install VBL timer\r\n", __FUNCTION__); dbg("install VBL timer\r\n");
rinfo->lvds_timer = 0; rinfo->lvds_timer = 0;
#ifndef DRIVER_IN_ROM #ifndef DRIVER_IN_ROM
install_vbl_timer(radeon_timer_func, 1); /* remove old vector */ install_vbl_timer(radeon_timer_func, 1); /* remove old vector */

2
BaS_gcc/sys/BaS.c
View File

@@ -465,7 +465,7 @@ void BaS(void)
fec_irq_enable(0, 5, 1); fec_irq_enable(0, 5, 1);
init_pci(); init_pci();
// video_init(); video_init();
/* initialize USB devices */ /* initialize USB devices */
//init_usb(); //init_usb();

5
BaS_gcc/sys/mmu.c
View File

@@ -1,6 +1,7 @@
#include "mmu.h" #include "mmu.h"
#include "acia.h" #include "acia.h"
#include "exceptions.h" #include "exceptions.h"
#include "pci.h"
#if defined(MACHINE_FIREBEE) #if defined(MACHINE_FIREBEE)
#include "firebee.h" #include "firebee.h"
@@ -626,7 +627,7 @@ void mmu_init(void)
ACR_BA(0x80000000)); /* (equals area from 3 to 4 GB */ ACR_BA(0x80000000)); /* (equals area from 3 to 4 GB */
#elif defined(MACHINE_M5484LITE) #elif defined(MACHINE_M5484LITE)
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */ ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
ACR_BA(0x80000000)); ACR_BA(PCI_MEMORY_OFFSET));
#elif defined(MACHINE_M54455) #elif defined(MACHINE_M54455)
ACR_ADMSK(0x7f) | ACR_ADMSK(0x7f) |
ACR_BA(0x80000000)); /* FIXME: not determined yet */ ACR_BA(0x80000000)); /* FIXME: not determined yet */
@@ -634,8 +635,6 @@ void mmu_init(void)
#error unknown machine! #error unknown machine!
#endif /* MACHINE_FIREBEE */ #endif /* MACHINE_FIREBEE */
// set_acr1(0x601fc000);
/* data access attributes for BaS in flash */ /* data access attributes for BaS in flash */
set_acr1(ACR_W(0) | set_acr1(ACR_W(0) |

2
BaS_gcc/sys/sysinit.c
View File

@@ -425,7 +425,7 @@ void init_fbcs()
MCF_FBCS2_CSAR = MCF_FBCS_CSAR_BA(0xF0000000); /* Firebee new I/O address range */ MCF_FBCS2_CSAR = MCF_FBCS_CSAR_BA(0xF0000000); /* Firebee new I/O address range */
MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 /* 32BIT PORT */ MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 /* 32BIT PORT */
| MCF_FBCS_CSCR_WS(8) /* DEFAULT 4WS */ | MCF_FBCS_CSCR_WS(4) /* DEFAULT 4WS */
| MCF_FBCS_CSCR_AA; /* AA */ | MCF_FBCS_CSCR_AA; /* AA */
MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M /* F000'0000-F7FF'FFFF */ MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M /* F000'0000-F7FF'FFFF */
| MCF_FBCS_CSMR_V); | MCF_FBCS_CSMR_V);

2
BaS_gcc/util/bas_printf.c
View File

@@ -426,7 +426,7 @@ void hexdump(uint8_t buffer[], int size)
while (bp < buffer + size) { while (bp < buffer + size) {
uint8_t *lbp = bp; uint8_t *lbp = bp;
xprintf("%08x ", line); xprintf("%08x ", bp);
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
if (bp + i > buffer + size) { if (bp + i > buffer + size) {

24
BaS_gcc/video/video.c
View File

@@ -7,12 +7,13 @@
#include "fb.h" #include "fb.h"
#include "radeonfb.h" #include "radeonfb.h"
//#define DBG_VIDEO #define DBG_VIDEO
#ifdef DBG_VIDEO #ifdef DBG_VIDEO
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0) #define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
#else #else
#define dbg(format, arg...) do {;} while (0) #define dbg(format, arg...) do {;} while (0)
#endif /* DBG_VIDEO */ #endif /* DBG_VIDEO */
#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0)
#ifdef _USE_VIDEL_ #ifdef _USE_VIDEL_
#define MON_ALL -1 /* code used in VMODE_ENTRY for match on mode only */ #define MON_ALL -1 /* code used in VMODE_ENTRY for match on mode only */
@@ -293,7 +294,7 @@ int16_t force_measure_pll;
void install_vbl_timer(void *func, int remove) void install_vbl_timer(void *func, int remove)
{ {
dbg("%s: not implemented\r\n", __FUNCTION__); dbg("not implemented\r\n");
} }
/* /*
@@ -311,38 +312,43 @@ void video_init(void)
int32_t id; int32_t id;
bool radeon_found = false; bool radeon_found = false;
dbg("%s\r\n", __FUNCTION__); dbg("\r\n");
/* FIXME: we currently just return here because the PCI configuration of ATI cards does not (yet) work */
return;
do do
{ {
/* /*
* scan PCI bus for graphics cards * scan PCI bus for graphics cards
*/ */
handle = pci_find_classcode(PCI_BASE_CLASS_DISPLAY | PCI_FIND_BASE_CLASS, index); handle = pci_find_classcode(PCI_BASE_CLASS_DISPLAY | PCI_FIND_BASE_CLASS, index);
dbg("handle=%d\r\n", handle);
if (handle > 0) /* found a display device */ if (handle > 0) /* found a display device */
{ {
dbg("%s: handle = 0x%x\r\n", __FUNCTION__, handle); dbg("handle = 0x%x\r\n", handle);
id = swpl(pci_read_config_longword(handle, PCIIDR)); /* get vendor + device id */ id = swpl(pci_read_config_longword(handle, PCIIDR)); /* get vendor + device id */
dbg("%s: PCIIDR=0x%x\r\n", __FUNCTION__, id); dbg("PCIIDR=0x%x\r\n", id);
board = &radeonfb_pci_table[0]; board = &radeonfb_pci_table[0];
do do
{ {
/* check it against elements of table */ /* check it against elements of table */
dbg("%s: check %x %x against %08x\r\n", __FUNCTION__, board->device, board->vendor, id); dbg("check %x %x against %08x\r\n", board->device, board->vendor, id);
if ((board->device == (id >> 16)) && (board->vendor == (id & 0xffff))) if ((board->device == (id >> 16)) && (board->vendor == (id & 0xffff)))
{ {
radeon_found = true; radeon_found = true;
dbg("%s: matched\r\n", __FUNCTION__); dbg("matched\r\n");
if (radeonfb_pci_register(handle, board) >= 0) if (radeonfb_pci_register(handle, board) >= 0)
{ {
xprintf("RADEON video card found and registered\r\n"); xprintf("RADEON video card found and registered\r\n");
} }
else else
{ {
dbg("%s: failed to register RADEON PCI video card\r\n", __FUNCTION__); dbg("failed to register RADEON PCI video card\r\n");
} }
return; return;
} }