From 920e5e6490f825dc92e1c22dc2558f63c8ffbc7f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Mon, 12 Aug 2013 17:38:39 +0000
Subject: [PATCH] added CACR define bits, added functions to set and retrieve
 current cache value and removed PC-relative compilation of cache.c

---
 Makefile        |  2 +-
 include/cache.h | 30 ++++++++++++++++++++++++++++++
 sources/cache.c | 18 ++++++++++++++++++
 3 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 0d99240..17df250 100644
--- a/Makefile
+++ b/Makefile
@@ -155,7 +155,7 @@ $(LIBBAS): $(OBJS)
 # compile printf pc-relative so it can be used as well before and after copy of BaS
 #$(OBJDIR)/bas_printf.o:	CFLAGS += -mpcrel
 # the same for flush_and_invalidate_cache()
-$(OBJDIR)/cache.o: CFLAGS += -mpcrel
+#$(OBJDIR)/cache.o: CFLAGS += -mpcrel
 
 $(OBJDIR)/%.o:$(SRCDIR)/%.c
 	$(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@
diff --git a/include/cache.h b/include/cache.h
index 52e90ed..2839ae9 100644
--- a/include/cache.h
+++ b/include/cache.h
@@ -27,6 +27,36 @@
 
 #include <stdint.h>
 
+/*
+ * CACR Cache Control Register
+ */
+#define CF_CACR_DEC         (0x80000000) /* Data Cache Enable                */
+#define CF_CACR_DW          (0x40000000) /* Data default Write-protect       */
+#define CF_CACR_DESB        (0x20000000) /* Data Enable Store Buffer         */
+#define CF_CACR_DPI         (0x10000000) /* Data Disable CPUSHL Invalidate   */
+#define CF_CACR_DHLCK       (0x08000000) /* 1/2 Data Cache Lock Mode         */
+#define CF_CACR_DDCM_00     (0x00000000) /* Cacheable writethrough imprecise */
+#define CF_CACR_DDCM_01     (0x02000000) /* Cacheable copyback               */
+#define CF_CACR_DDCM_10     (0x04000000) /* Noncacheable precise             */
+#define CF_CACR_DDCM_11     (0x06000000) /* Noncacheable imprecise           */
+#define CF_CACR_DCINVA      (0x01000000) /* Data Cache Invalidate All        */
+#define CF_CACR_DDSP        (0x00800000) /* Data default supervisor-protect  */
+#define CF_CACR_IVO         (0x00100000) /* Invalidate only                  */
+#define CF_CACR_BEC         (0x00080000) /* Branch Cache Enable              */
+#define CF_CACR_BCINVA      (0x00040000) /* Branch Cache Invalidate All      */
+#define CF_CACR_IEC         (0x00008000) /* Instruction Cache Enable         */
+#define CF_CACR_SPA         (0x00004000) /* Search by Physical Address       */
+#define CF_CACR_DNFB        (0x00002000) /* Default cache-inhibited fill buf */
+#define CF_CACR_IDPI        (0x00001000) /* Instr Disable CPUSHL Invalidate  */
+#define CF_CACR_IHLCK       (0x00000800) /* 1/2 Instruction Cache Lock Mode  */
+#define CF_CACR_IDCM        (0x00000400) /* Noncacheable Instr default mode  */
+#define CF_CACR_ICINVA      (0x00000100) /* Instr Cache Invalidate All       */
+#define CF_CACR_IDSP        (0x00000080) /* Ins default supervisor-protect   */
+#define CF_CACR_EUSP        (0x00000020) /* Switch stacks in user mode       */
+
 extern void flush_and_invalidate_caches(void);
+extern uint32_t cacr_get(void);
+extern void cacr_set(uint32_t);
+
 
 #endif /* _CACHE_H_ */
diff --git a/sources/cache.c b/sources/cache.c
index b462348..d44c46c 100644
--- a/sources/cache.c
+++ b/sources/cache.c
@@ -24,6 +24,24 @@
 
 #include "cache.h"
 
+void cacr_set(uint32_t value)
+{
+	extern uint32_t rt_cacr[];
+
+	rt_cacr[0] = value;
+	__asm__ __volatile__("movec	%0, cacr\n\t"
+						 : /* output */
+						 : "r" (rt_cacr[0])
+						 : /* clobbers */);
+}
+
+uint32_t cacr_get(void)
+{
+	extern uint32_t rt_cacr[];
+
+	return rt_cacr[0];
+}
+
 void flush_and_invalidate_caches(void)
 {
 	__asm__ (