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fixed errornous deactivation of FPGA load

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This commit is contained in:
Markus Fröschle
2014-12-26 07:26:10 +00:00
parent 5163fd5813
commit 88c1bd2373
2 changed files with 108 additions and 100 deletions
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2
bas.lk.in
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@@ -236,6 +236,8 @@ SECTIONS
* and shouldn't be overwritten on boot * and shouldn't be overwritten on boot
*/ */
__FPGA_JTAG_LOADED = __RAMBAR1; __FPGA_JTAG_LOADED = __RAMBAR1;
__FPGA_JTAG_VALID = __FPGA_JTAG_LOADED + 4;
/* system variables */ /* system variables */
/* RAMBAR0 0 to 0x7FF -> exception vectors */ /* RAMBAR0 0 to 0x7FF -> exception vectors */

14
sys/init_fpga.c
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@@ -40,9 +40,12 @@ extern uint8_t _FPGA_CONFIG_SIZE[];
/* /*
* flag located in processor SRAM1 that indicates that the FPGA configuration has * flag located in processor SRAM1 that indicates that the FPGA configuration has
* been loaded through JTAG. init_fpga() will honour this and not overwrite config. * been loaded through the onboard JTAG interface.
* init_fpga() will honour this and not overwrite config.
*/ */
extern int32_t _FPGA_JTAG_LOADED; extern int32_t _FPGA_JTAG_LOADED;
extern int32_t _FPGA_JTAG_VALID;
#define VALID_JTAG 0xaffeaffe
void config_gpio_for_fpga_config(void) void config_gpio_for_fpga_config(void)
{ {
@@ -84,13 +87,14 @@ bool init_fpga(void)
volatile int32_t time, start, end; volatile int32_t time, start, end;
int i; int i;
xprintf("FPGA load config (_FPGA_JTAG_LOADED = %x)...", _FPGA_JTAG_LOADED); xprintf("FPGA load config (_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
if (_FPGA_JTAG_LOADED == 1) if (_FPGA_JTAG_LOADED == 1 && _FPGA_JTAG_VALID == VALID_JTAG)
{ {
xprintf("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n"); xprintf("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
/* reset the flag so that next boot will load config again from flash */ /* reset the flag so that next boot will load config again from flash */
_FPGA_JTAG_LOADED = 0; _FPGA_JTAG_LOADED = 0;
return true; return true;
} }
start = MCF_SLT0_SCNT; start = MCF_SLT0_SCNT;
@@ -105,7 +109,8 @@ bool init_fpga(void)
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */ MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS)); /* wait until status becomes high */ while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS))
; /* wait until status becomes high */
/* /*
* excerpt from an Altera configuration manual: * excerpt from an Altera configuration manual:
@@ -171,5 +176,6 @@ bool init_fpga(void)
} }
xprintf("FAILED!\r\n"); xprintf("FAILED!\r\n");
config_gpio_for_jtag_config(); config_gpio_for_jtag_config();
return false; return false;
} }