diff --git a/bas.lk.in b/bas.lk.in index 64b8c9c..4f6c271 100644 --- a/bas.lk.in +++ b/bas.lk.in @@ -23,7 +23,7 @@ MEMORY */ bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00200000, LENGTH = 0x00100000 /* - * driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory + * driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory */ driver_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000 } @@ -44,8 +44,8 @@ SECTIONS OBJDIR/exceptions.o(.text) OBJDIR/driver_vec.o(.text) OBJDIR/interrupts.o(.text) - OBJDIR/mmu.o(.text) - + OBJDIR/mmu.o(.text) + OBJDIR/BaS.o(.text) OBJDIR/pci.o(.text) OBJDIR/usb.o(.text) @@ -108,7 +108,7 @@ SECTIONS OBJDIR/xhdi_sd.o(.text) OBJDIR/xhdi_interface.o(.text) OBJDIR/xhdi_vec.o(.text) - + #ifdef COMPILE_RAM /* * if we compile to RAM anyway, there is no need to copy anything @@ -118,7 +118,7 @@ SECTIONS *(.data) __BAS_DATA_END = .; __BAS_BSS_START = .; - *(.bss) + *(.bss) __BAS_BSS_END = .; #endif /* COMPILE_RAM */ @@ -140,7 +140,7 @@ SECTIONS *(.data) __BAS_DATA_END = .; __BAS_BSS_START = .; - *(.bss) + *(.bss) __BAS_BSS_END = .; . = ALIGN(16); @@ -153,16 +153,16 @@ SECTIONS _driver_mem_buffer = .; //. = . + DRIVER_MEM_BUFFER_SIZE; } > driver_ram - + /* * Global memory map */ /* SDRAM Initialization */ - ___SDRAM = SDRAM_START; - ___SDRAM_SIZE = SDRAM_SIZE; + ___SDRAM = SDRAM_START; + ___SDRAM_SIZE = SDRAM_SIZE; _SDRAM_VECTOR_TABLE = ___SDRAM; - + /* ST-RAM */ __STRAM = ___SDRAM; __STRAM_END = __TOS; @@ -173,7 +173,7 @@ SECTIONS /* FastRAM */ __FASTRAM = 0x10000000; __TARGET_ADDRESS = TARGET_ADDRESS; - + #if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS __FASTRAM_END = __BAS_IN_RAM; #else @@ -183,7 +183,7 @@ SECTIONS /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */ ___BOOT_FLASH = BOOTFLASH_BASE_ADDRESS; - ___BOOT_FLASH_SIZE = BOOTFLASH_SIZE; + ___BOOT_FLASH_SIZE = BOOTFLASH_SIZE; #if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS /* BaS */ @@ -203,35 +203,40 @@ SECTIONS __EMUTOS_SIZE = 0x00100000; /* where FPGA data lives in flash */ - __FPGA_FLASH_DATA = 0xe0700000; - __FPGA_FLASH_DATA_SIZE = 0x100000; + __FPGA_CONFIG = 0xe0700000; + __FPGA_CONFIG_SIZE = 0x100000; /* VIDEO RAM BASIS */ __VRAM = 0x60000000; /* Memory mapped registers */ - __MBAR = 0xFF000000; - + __MBAR = 0xFF000000; + /* 32KB on-chip System SRAM */ - __SYS_SRAM = __MBAR + 0x10000; + __SYS_SRAM = __MBAR + 0x10000; __SYS_SRAM_SIZE = 0x00008000; /* MMU memory mapped registers */ - __MMUBAR = 0xFF040000; + __MMUBAR = 0xFF040000; /* - * 4KB on-chip Core SRAM0: -> exception table + * 4KB on-chip Core SRAM0: -> exception table */ - __RAMBAR0 = 0xFF100000; - __RAMBAR0_SIZE = 0x00001000; + __RAMBAR0 = 0xFF100000; + __RAMBAR0_SIZE = 0x00001000; /* 4KB on-chip Core SRAM1 */ - __RAMBAR1 = 0xFF101000; - __RAMBAR1_SIZE = 0x00001000; - __SUP_SP = __RAMBAR0 + __RAMBAR0_SIZE - 4; + __RAMBAR1 = 0xFF101000; + __RAMBAR1_SIZE = 0x00001000; + __SUP_SP = __RAMBAR1 + __RAMBAR1_SIZE - 4; + /* + * this flag (if 1) indicates that FPGA configuration has been loaded through JTAG + * and shouldn't be overwritten on boot + */ + __FPGA_JTAG_LOADED = __RAMBAR1; /* system variables */ - + /* RAMBAR0 0 to 0x7FF -> exception vectors */ _rt_mod = __RAMBAR0 + 0x800; _rt_ssp = __RAMBAR0 + 0x804; diff --git a/dma/dma.c b/dma/dma.c index 96e5c32..35c8e3c 100644 --- a/dma/dma.c +++ b/dma/dma.c @@ -39,7 +39,7 @@ #error "unknown machine!" #endif /* MACHINE_FIREBEE */ -#define DBG_DMA +// #define DBG_DMA #ifdef DBG_DMA #define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0) #else @@ -58,13 +58,13 @@ struct dma_channel static char used_reqs[32] = { DMA_ALWAYS, DMA_DSPI_RXFIFO, DMA_DSPI_TXFIFO, DMA_DREQ0, - DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0, DMA_USB_EP1, - DMA_USB_EP2, DMA_USB_EP3, DMA_PCI_TX, DMA_PCI_RX, - DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 + DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0, DMA_USB_EP1, + DMA_USB_EP2, DMA_USB_EP3, DMA_PCI_TX, DMA_PCI_RX, + DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 }; static struct dma_channel dma_channel[NCHANNELS] = @@ -225,7 +225,7 @@ int dma_set_initiator(int initiator) else /* No empty slots */ { dbg("%s: no free slot\r\n", __FUNCTION__); - + return 1; } break; @@ -530,7 +530,7 @@ int dma_get_channel(int requestor) } /* - * Remove the channel being initiated by the given requestor from + * Remove the channel being initiated by the given requestor from * the active list * * Parameters: @@ -551,8 +551,8 @@ void dma_free_channel(int requestor) } } -/* - * This is the catch-all interrupt handler for the mult-channel DMA +/* + * This is the catch-all interrupt handler for the mult-channel DMA */ int dma_interrupt_handler(void *arg1, void *arg2) { @@ -560,8 +560,8 @@ int dma_interrupt_handler(void *arg1, void *arg2) (void) set_ipl(7); - /* - * Determine which interrupt(s) triggered by AND'ing the + /* + * Determine which interrupt(s) triggered by AND'ing the * pending interrupts with those that aren't masked. */ interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR; @@ -598,9 +598,9 @@ void *dma_memcpy(void *dst, void *src, size_t n) int ret; #ifdef DBG_DMA - int32_t time; - int32_t start; - int32_t end; + int32_t time; + int32_t start; + int32_t end; start = MCF_SLT0_SCNT; #endif /* DBG_DMA */ diff --git a/flash_scripts/flash_firebee_bas.bdm b/flash_scripts/flash_firebee_bas.bdm index 813c7e0..ca0b487 100755 --- a/flash_scripts/flash_firebee_bas.bdm +++ b/flash_scripts/flash_firebee_bas.bdm @@ -1,4 +1,4 @@ -#!/usr/local/bin/bdmctrl +#!/usr/local/bin/bdmctrl -D2 # # firebee board initialization for bdmctrl # @@ -21,32 +21,32 @@ write 0xFF000508 0x00001180 4 write 0xFF000504 0x007F0001 4 # SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes -write 0xFF000004 0x000002AA 4 # SDRAMDS configuration -write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) -write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) -write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) -write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) -write 0xFF000108 0x73622830 4 # SDCFG1 -write 0xFF00010C 0x46770000 4 # SDCFG2 +#write 0xFF000004 0x000002AA 4 # SDRAMDS configuration +#write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +#write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +#write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +#write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +#write 0xFF000108 0x73622830 4 # SDCFG1 +#write 0xFF00010C 0x46770000 4 # SDCFG2 -write 0xFF000104 0xE10D0002 4 # SDCR + IPALL -write 0xFF000100 0x40010000 4 # SDMR (write to LEMR) -write 0xFF000100 0x048D0000 4 # SDMR (write to LMR) -sleep 100 -write 0xFF000104 0xE10D0002 4 # SDCR + IPALL -write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) -write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) -write 0xFF000100 0x008D0000 4 # SDMR (write to LMR) -write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh) -sleep 10 +#write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +#write 0xFF000100 0x40010000 4 # SDMR (write to LEMR) +#write 0xFF000100 0x048D0000 4 # SDMR (write to LMR) +#sleep 100 +#write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +#write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +#write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +#write 0xFF000100 0x008D0000 4 # SDMR (write to LMR) +#write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh) +#sleep 10 # use system sdram as flashlib scratch area. # TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet. # This seems to be related to large flash buffers and PC-relative adressing of the plugin -flash-plugin 0x1000 0xf000 flash29.plugin +#flash-plugin 0x1000 0xf000 flash29-5475.plugin # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29 -flash 0xE0000000 +flash 0xe0000000 # Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for BaS) # @@ -55,17 +55,44 @@ flash 0xE0000000 # # contrary to documentation, it seems we need to erase-wait after each sector -erase 0xE0000000 0 -erase 0xE0000000 1 -erase 0xE0000000 2 -erase 0xE0000000 3 -erase 0xE0000000 4 -erase 0xE0000000 5 -erase 0xE0000000 7 -erase 0xE0000000 8 -erase 0xE0000000 9 -erase 0xE0000000 10 -erase-wait 0xE0000000 +erase 0xe0000000 0 +erase-wait 0xe0000000 +erase 0xe0000000 0x1000 +erase-wait 0xe0000000 +erase 0xe0000000 0x2000 +erase-wait 0xe0000000 +erase 0xe0000000 0x3000 +erase-wait 0xe0000000 +erase 0xe0000000 0x4000 +erase-wait 0xe0000000 +erase 0xe0000000 0x5000 +erase-wait 0xe0000000 +erase 0xe0000000 0x6000 +erase-wait 0xe0000000 +erase 0xe0000000 0x7000 +erase-wait 0xe0000000 +erase 0xe0000000 0x8000 +erase-wait 0xe0000000 +erase 0xe0000000 0x10000 +erase-wait 0xe0000000 +erase 0xe0000000 0x18000 +erase-wait 0xe0000000 +erase 0xe0000000 0x20000 +erase-wait 0xe0000000 +erase 0xe0000000 0x28000 +erase-wait 0xe0000000 +erase 0xe0000000 0x30000 +erase-wait 0xe0000000 +erase 0xe0000000 0x38000 +erase-wait 0xe0000000 +erase 0xe0000000 0x40000 +erase-wait 0xe0000000 +erase 0xe0000000 0x48000 +erase-wait 0xe0000000 +erase 0xe0000000 0x50000 +erase-wait 0xe0000000 +erase 0xe0000000 0x58000 +erase-wait 0xe0000000 load -v ../firebee/bas.elf wait diff --git a/net/fec.c b/net/fec.c index 08a8d03..85430fb 100644 --- a/net/fec.c +++ b/net/fec.c @@ -32,7 +32,7 @@ #error Unknown machine! #endif -#define DBG_FEC +// #define DBG_FEC #ifdef DBG_FEC #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) #else @@ -237,33 +237,33 @@ void fec_log_init(uint8_t ch) */ void fec_log_dump(uint8_t ch) { - dbg("\r\n FEC%d Log\r\n", __FUNCTION__, ch); - dbg(" ---------------\r\n", __FUNCTION__); - dbg(" Total: %4d\r\n", fec_log[ch].total); - dbg(" hberr: %4d\r\n", fec_log[ch].hberr); - dbg(" babr: %4d\r\n", fec_log[ch].babr); - dbg(" babt: %4d\r\n", fec_log[ch].babt); - dbg(" gra: %4d\r\n", fec_log[ch].gra); - dbg(" txf: %4d\r\n", fec_log[ch].txf); - dbg(" mii: %4d\r\n", fec_log[ch].mii); - dbg(" lc: %4d\r\n", fec_log[ch].lc); - dbg(" rl: %4d\r\n", fec_log[ch].rl); - dbg(" xfun: %4d\r\n", fec_log[ch].xfun); - dbg(" xferr: %4d\r\n", fec_log[ch].xferr); - dbg(" rferr: %4d\r\n", fec_log[ch].rferr); - dbg(" dtxf: %4d\r\n", fec_log[ch].dtxf); - dbg(" drxf: %4d\r\n", fec_log[ch].drxf); - dbg(" \r\nRFSW:\r\n"); - dbg(" inv: %4d\r\n", fec_log[ch].rfsw_inv); - dbg(" m: %4d\r\n", fec_log[ch].rfsw_m); - dbg(" bc: %4d\r\n", fec_log[ch].rfsw_bc); - dbg(" mc: %4d\r\n", fec_log[ch].rfsw_mc); - dbg(" lg: %4d\r\n", fec_log[ch].rfsw_lg); - dbg(" no: %4d\r\n", fec_log[ch].rfsw_no); - dbg(" cr: %4d\r\n", fec_log[ch].rfsw_cr); - dbg(" ov: %4d\r\n", fec_log[ch].rfsw_ov); - dbg(" tr: %4d\r\n", fec_log[ch].rfsw_tr); - dbg(" ---------------\r\n\r\n"); + dbg("\r\n FEC%d Log\r\n", __FUNCTION__, ch); + dbg(" ---------------\r\n", __FUNCTION__); + dbg(" Total: %4d\r\n", fec_log[ch].total); + dbg(" hberr: %4d\r\n", fec_log[ch].hberr); + dbg(" babr: %4d\r\n", fec_log[ch].babr); + dbg(" babt: %4d\r\n", fec_log[ch].babt); + dbg(" gra: %4d\r\n", fec_log[ch].gra); + dbg(" txf: %4d\r\n", fec_log[ch].txf); + dbg(" mii: %4d\r\n", fec_log[ch].mii); + dbg(" lc: %4d\r\n", fec_log[ch].lc); + dbg(" rl: %4d\r\n", fec_log[ch].rl); + dbg(" xfun: %4d\r\n", fec_log[ch].xfun); + dbg(" xferr: %4d\r\n", fec_log[ch].xferr); + dbg(" rferr: %4d\r\n", fec_log[ch].rferr); + dbg(" dtxf: %4d\r\n", fec_log[ch].dtxf); + dbg(" drxf: %4d\r\n", fec_log[ch].drxf); + dbg(" \r\nRFSW:\r\n"); + dbg(" inv: %4d\r\n", fec_log[ch].rfsw_inv); + dbg(" m: %4d\r\n", fec_log[ch].rfsw_m); + dbg(" bc: %4d\r\n", fec_log[ch].rfsw_bc); + dbg(" mc: %4d\r\n", fec_log[ch].rfsw_mc); + dbg(" lg: %4d\r\n", fec_log[ch].rfsw_lg); + dbg(" no: %4d\r\n", fec_log[ch].rfsw_no); + dbg(" cr: %4d\r\n", fec_log[ch].rfsw_cr); + dbg(" ov: %4d\r\n", fec_log[ch].rfsw_ov); + dbg(" tr: %4d\r\n", fec_log[ch].rfsw_tr); + dbg(" ---------------\r\n\r\n"); } /* @@ -544,13 +544,13 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd) * Make the initiator assignment */ res = dma_set_initiator(DMA_FEC_RX(ch)); - dbg("dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", ch, res); + dbg("dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", ch, res); /* * Grab the initiator number */ initiator = dma_get_initiator(DMA_FEC_RX(ch)); - dbg("dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", ch, initiator); + dbg("dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", ch, initiator); /* * Determine the DMA channel running the task for the @@ -558,7 +558,7 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd) */ channel = dma_set_channel(DMA_FEC_RX(ch), (ch == 0) ? fec0_rx_frame : fec1_rx_frame); - dbg("DMA channel for FEC%1d: %d\r\n", ch, channel); + dbg("DMA channel for FEC%1d: %d\r\n", ch, channel); /* * Start the Rx DMA task @@ -572,18 +572,18 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd) 0, initiator, FECRX_DMA_PRI(ch), - 0 - | MCD_FECRX_DMA + 0 + | MCD_FECRX_DMA | MCD_INTERRUPT - | MCD_TT_FLAGS_CW + | MCD_TT_FLAGS_CW | MCD_TT_FLAGS_RL | MCD_TT_FLAGS_SP , - 0 + 0 | MCD_NO_CSUM | MCD_NO_BYTE_SWAP ); - dbg("Rx DMA task for FEC%1d started\r\n", ch); + dbg("Rx DMA task for FEC%1d started\r\n", ch); } /* @@ -607,13 +607,13 @@ void fec_rx_continue(uint8_t ch) */ channel = dma_get_channel(DMA_FEC_RX(ch)); - dbg("RX DMA channel for FEC%1d is %d\r\n", ch, channel); + dbg("RX DMA channel for FEC%1d is %d\r\n", ch, channel); /* * Continue/restart the DMA task */ MCD_continDma(channel); - dbg("RX dma on channel %d continued\r\n", channel); + dbg("RX dma on channel %d continued\r\n", channel); } /* @@ -642,9 +642,9 @@ void fec_rx_stop (uint8_t ch) /* Kill the FEC Rx DMA task */ MCD_killDma(channel); - /* - * Free up the FEC requestor from the software maintained - * initiator list + /* + * Free up the FEC requestor from the software maintained + * initiator list */ dma_free_initiator(DMA_FEC_RX(ch)); @@ -656,7 +656,7 @@ void fec_rx_stop (uint8_t ch) } /* - * Receive Frame interrupt handler - this handler is called by the + * Receive Frame interrupt handler - this handler is called by the * DMA interrupt handler indicating that a packet was successfully * transferred out of the Rx FIFO. * @@ -671,7 +671,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif) NBUF *cur_nbuf, *new_nbuf; int keep; - dbg("started\r\n"); + dbg("started\r\n"); while ((pRxBD = fecbd_rx_alloc(ch)) != NULL) { @@ -684,7 +684,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif) * - No undefined bits should be set * - The upper 5 bits of the length should be cleared */ - if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608) + if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608) || (pRxBD->length & 0xF800)) { keep = false; @@ -716,8 +716,8 @@ void fec_rx_frame(uint8_t ch, NIF *nif) if (keep) { - /* - * Pull the network buffer off the Rx ring queue + /* + * Pull the network buffer off the Rx ring queue */ cur_nbuf = nbuf_remove(NBUF_RX_RING); @@ -733,7 +733,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif) new_nbuf = nbuf_alloc(); if (new_nbuf == NULL) { - dbg("nbuf_alloc() failed\n"); + dbg("nbuf_alloc() failed\n"); /* * Can't allocate a new network buffer, so we @@ -767,7 +767,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif) /* - * Let the DMA know that there is a new Rx BD (in case the + * Let the DMA know that there is a new Rx BD (in case the * ring was full and the DMA was waiting for an empty one) */ fec_rx_continue(ch); @@ -778,7 +778,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif) eth_hdr = (ETH_HDR *) cur_nbuf->data; /* - * Pass the received packet up the network stack if the + * Pass the received packet up the network stack if the * protocol is supported in our network interface (NIF) */ if (nif_protocol_exist(nif, eth_hdr->type)) @@ -789,12 +789,12 @@ void fec_rx_frame(uint8_t ch, NIF *nif) else { nbuf_free(cur_nbuf); - dbg("got unsupported packet %d, trashed it\r\n", eth_hdr->type); + dbg("got unsupported packet %d, trashed it\r\n", eth_hdr->type); } } - else + else { - /* + /* * This frame isn't a keeper * Reset the status and length, but don't need to get another * buffer since we are trashing the data in the current one @@ -804,7 +804,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif) pRxBD->status |= RX_BD_E; /* - * Move the current buffer from the beginning to the end of the + * Move the current buffer from the beginning to the end of the * Rx ring queue */ cur_nbuf = nbuf_remove(NBUF_RX_RING); @@ -853,13 +853,13 @@ void fec_tx_start(uint8_t ch, int8_t *txbd) * Make the initiator assignment */ res = dma_set_initiator(DMA_FEC_TX(ch)); - dbg("dma_set_initiator(%d) = %d\r\n", ch, res); + dbg("dma_set_initiator(%d) = %d\r\n", ch, res); /* * Grab the initiator number */ initiator = dma_get_initiator(DMA_FEC_TX(ch)); - dbg("dma_get_initiator(%d) = %d\r\n", ch, initiator); + dbg("dma_get_initiator(%d) = %d\r\n", ch, initiator); /* @@ -868,7 +868,7 @@ void fec_tx_start(uint8_t ch, int8_t *txbd) */ channel = dma_set_channel(DMA_FEC_TX(ch), (ch == 0) ? fec0_tx_frame : fec1_tx_frame); - dbg("dma_set_channel(%d, ...) = %d\r\n", ch, channel); + dbg("dma_set_channel(%d, ...) = %d\r\n", ch, channel); /* * Start the Tx DMA task @@ -882,18 +882,18 @@ void fec_tx_start(uint8_t ch, int8_t *txbd) 0, initiator, FECTX_DMA_PRI(ch), - 0 - | MCD_FECTX_DMA + 0 + | MCD_FECTX_DMA | MCD_INTERRUPT - | MCD_TT_FLAGS_CW + | MCD_TT_FLAGS_CW | MCD_TT_FLAGS_RL | MCD_TT_FLAGS_SP , - 0 + 0 | MCD_NO_CSUM | MCD_NO_BYTE_SWAP ); - dbg("DMA tx task started\r\n"); + dbg("DMA tx task started\r\n"); } /* @@ -916,13 +916,13 @@ void fec_tx_continue(uint8_t ch) * selected FEC */ channel = dma_get_channel(DMA_FEC_TX(ch)); - dbg("dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n", ch, channel); + dbg("dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n", ch, channel); /* * Continue/restart the DMA task */ MCD_continDma(channel); - dbg("DMA TX task continue\r\n"); + dbg("DMA TX task continue\r\n"); } /* @@ -969,9 +969,9 @@ void fec_tx_stop(uint8_t ch) /* Kill the FEC Tx DMA task */ MCD_killDma(channel); - /* - * Free up the FEC requestor from the software maintained - * initiator list + /* + * Free up the FEC requestor from the software maintained + * initiator list */ dma_free_initiator(DMA_FEC_TX(ch)); @@ -983,7 +983,7 @@ void fec_tx_stop(uint8_t ch) } /* - * Trasmit Frame interrupt handler - this handler is called by the + * Trasmit Frame interrupt handler - this handler is called by the * DMA interrupt handler indicating that a packet was successfully * transferred to the Tx FIFO. * @@ -996,7 +996,7 @@ void fec_tx_frame(uint8_t ch) NBUF *pNbuf; bool is_empty = true; - dbg("\r\n"); + dbg("\r\n"); while ((pTxBD = fecbd_tx_free(ch)) != NULL) { fec_log[ch].dtxf++; @@ -1010,7 +1010,7 @@ void fec_tx_frame(uint8_t ch) * Free up the network buffer that was just transmitted */ nbuf_free(pNbuf); - dbg("free buffer %p from TX ring\r\n", pNbuf); + dbg("free buffer %p from TX ring\r\n", pNbuf); /* * Re-initialize the Tx BD @@ -1019,9 +1019,9 @@ void fec_tx_frame(uint8_t ch) pTxBD->length = 0; is_empty = false; - } + } if (is_empty) - dbg("transmit queue was empty!\r\n"); + dbg("transmit queue was empty!\r\n"); } void fec0_tx_frame(void) @@ -1044,7 +1044,7 @@ void fec1_tx_frame(void) * dst Destination MAC Address * src Source MAC Address * type Ethernet Frame Type - * length Number of bytes to be transmitted (doesn't include type, + * length Number of bytes to be transmitted (doesn't include type, * src, or dest byte count) * pkt Pointer packet network buffer * @@ -1059,14 +1059,14 @@ int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NB /* Check the length */ if ((nbuf->length + ETH_HDR_LEN) > ETH_MTU) { - dbg("nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n", - nbuf->length, ETH_HDR_LEN, ETH_MTU); + dbg("nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n", + nbuf->length, ETH_HDR_LEN, ETH_MTU); return 0; } - /* - * Copy the destination address, source address, and Ethernet - * type into the packet + /* + * Copy the destination address, source address, and Ethernet + * type into the packet */ memcpy(&nbuf->data[0], dst, 6); memcpy(&nbuf->data[6], src, 6); @@ -1082,7 +1082,7 @@ int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NB */ nbuf_add(NBUF_TX_RING, nbuf); - /* + /* * Setup the buffer descriptor for transmission */ pTxBD->data = nbuf->data; @@ -1192,7 +1192,7 @@ static void fec_irq_handler(uint8_t ch) event = eir & MCF_FEC_EIMR(ch); if (event != eir) - dbg("pending but not enabled: 0x%08x\r\n", (event ^ eir)); + dbg("pending but not enabled: 0x%08x\r\n", (event ^ eir)); /* * Clear the event(s) in the EIR immediately @@ -1203,8 +1203,8 @@ static void fec_irq_handler(uint8_t ch) { fec_log[ch].total++; fec_log[ch].rferr++; - dbg("RFERR\r\n"); - dbg("FECRFSR%d = 0x%08x\r\n", ch, MCF_FEC_FECRFSR(ch)); + dbg("RFERR\r\n"); + dbg("FECRFSR%d = 0x%08x\r\n", ch, MCF_FEC_FECRFSR(ch)); //fec_eth_stop(ch); } @@ -1212,14 +1212,14 @@ static void fec_irq_handler(uint8_t ch) { fec_log[ch].total++; fec_log[ch].xferr++; - dbg("XFERR\r\n"); + dbg("XFERR\r\n"); } if (event & MCF_FEC_EIR_XFUN) { fec_log[ch].total++; fec_log[ch].xfun++; - dbg("XFUN\r\n"); + dbg("XFUN\r\n"); //fec_eth_stop(ch); } @@ -1227,54 +1227,54 @@ static void fec_irq_handler(uint8_t ch) { fec_log[ch].total++; fec_log[ch].rl++; - dbg("RL\r\n"); + dbg("RL\r\n"); } if (event & MCF_FEC_EIR_LC) { fec_log[ch].total++; fec_log[ch].lc++; - dbg("LC\r\n"); + dbg("LC\r\n"); } if (event & MCF_FEC_EIR_MII) { fec_log[ch].mii++; - dbg("MII\r\n"); + dbg("MII\r\n"); } if (event & MCF_FEC_EIR_TXF) { fec_log[ch].txf++; - dbg("TXF\r\n"); + dbg("TXF\r\n"); fec_log_dump(0); } if (event & MCF_FEC_EIR_GRA) { fec_log[ch].gra++; - dbg("GRA\r\n"); + dbg("GRA\r\n"); } if (event & MCF_FEC_EIR_BABT) { fec_log[ch].total++; fec_log[ch].babt++; - dbg("BABT\r\n"); + dbg("BABT\r\n"); } if (event & MCF_FEC_EIR_BABR) { fec_log[ch].total++; fec_log[ch].babr++; - dbg("BABR\r\n"); + dbg("BABR\r\n"); } if (event & MCF_FEC_EIR_HBERR) { fec_log[ch].total++; fec_log[ch].hberr++; - dbg("HBERR\r\n"); + dbg("HBERR\r\n"); } } @@ -1344,9 +1344,9 @@ void fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, con */ #if defined(MACHINE_FIREBEE) if (am79c874_init(0, 0, speed, duplex)) - dbg("PHY init completed\r\n"); + dbg("PHY init completed\r\n"); else - dbg("PHY init failed\r\n"); + dbg("PHY init failed\r\n"); #elif defined(MACHINE_M548X) bcm_5222_init(0, 0, speed, duplex); #else @@ -1399,7 +1399,7 @@ void fec_eth_stop(uint8_t ch) */ level = set_ipl(7); - dbg("fec %d stopped\r\n", ch); + dbg("fec %d stopped\r\n", ch); /* * Gracefully disable the receiver and transmitter */ @@ -1421,12 +1421,12 @@ void fec_eth_stop(uint8_t ch) fec_log_dump(ch); #endif - /* + /* * Flush the network buffers */ nbuf_flush(); - /* + /* * Restore interrupt level */ set_ipl(level); diff --git a/sys/init_fpga.c b/sys/init_fpga.c index 01240f3..f9cc33c 100644 --- a/sys/init_fpga.c +++ b/sys/init_fpga.c @@ -33,10 +33,16 @@ #define FPGA_DATA0 (1 << 3) #define FPGA_CONF_DONE (1 << 5) -extern uint8_t _FPGA_FLASH_DATA[]; -#define FPGA_FLASH_DATA &_FPGA_FLASH_DATA[0] -extern uint8_t _FPGA_FLASH_DATA_SIZE[]; -#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_FLASH_DATA_SIZE[0]) +extern uint8_t _FPGA_CONFIG[]; +#define FPGA_FLASH_DATA &_FPGA_CONFIG[0] +extern uint8_t _FPGA_CONFIG_SIZE[]; +#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_CONFIG_SIZE[0]) + +/* + * flag located in processor SRAM1 that indicates that the FPGA configuration has + * been loaded through JTAG. init_fpga() will honour this and not overwrite config. + */ +extern int32_t _FPGA_JTAG_LOADED; void config_gpio_for_fpga_config(void) { @@ -78,7 +84,15 @@ bool init_fpga(void) volatile int32_t time, start, end; int i; - xprintf("FPGA load config... "); + xprintf("FPGA load config (_FPGA_JTAG_LOADED = %x)...", _FPGA_JTAG_LOADED); + if (_FPGA_JTAG_LOADED == 1) + { + xprintf("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n"); + + /* reset the flag so that next boot will load config again from flash */ + _FPGA_JTAG_LOADED = 0; + return true; + } start = MCF_SLT0_SCNT; config_gpio_for_fpga_config();