fix __MBAR and __RAMBAR for MCF54455
This commit is contained in:
@@ -18,20 +18,22 @@ _rom_header:
|
||||
* We replace it by bra.s to allow running the ROM from the first byte.
|
||||
* Then we add a fake jmp instruction for pretty disassembly.
|
||||
*/
|
||||
bra.s _rom_entry // Short jump to the real entry point
|
||||
.short 0x4ef9 // Fake jmp instruction
|
||||
bra.s _rom_entry // Short jump to the real entry point
|
||||
.short 0x4ef9 // Fake jmp instruction
|
||||
/* The second long is the initial PC */
|
||||
.long _rom_entry // Real entry point
|
||||
.long _rom_entry // Real entry point
|
||||
|
||||
/* ROM entry point */
|
||||
_rom_entry:
|
||||
/* disable interrupts */
|
||||
move.w #0x2700,sr
|
||||
|
||||
#if !defined(MACHINE_M54455) // MCF54455 does not have the MBAR register
|
||||
/* Initialize MBAR */
|
||||
move.l #__MBAR,d0
|
||||
movec d0,MBAR
|
||||
move.l d0,_rt_mbar
|
||||
#endif
|
||||
|
||||
/* mmu off */
|
||||
move.l #__MMUBAR+1,d0
|
||||
@@ -40,11 +42,17 @@ _rom_entry:
|
||||
clr.l d0
|
||||
move.l d0,MCF_MMU_MMUCR
|
||||
|
||||
#if !defined(MACHINE_M54455) // MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
|
||||
|
||||
/* Initialize RAMBARs: locate SRAM and validate it */
|
||||
move.l #__RAMBAR0 + 0x7,d0 /* supervisor only */
|
||||
move.l #__RAMBAR0 + 0x7,d0 // supervisor only
|
||||
movec d0,RAMBAR0
|
||||
move.l #__RAMBAR1 + 0x1,d0
|
||||
movec d0,RAMBAR1
|
||||
#else
|
||||
move.l #__RAMBAR0 + 0x7,d0
|
||||
movec d0,RAMBAR
|
||||
#endif
|
||||
|
||||
/* set stack pointer to end of SRAM */
|
||||
lea __SUP_SP,a7
|
||||
|
||||
Reference in New Issue
Block a user