integrated printf routines. Only tested yet for "before copy"-case (which is more difficult than afterwards).

mcf5474.bdm

@@ -11,41 +11,55 @@ reset
 
 # set VBR
 write-ctrl 0x0801 0x00000000
-
+sleep 10
 # Turn on MBAR at 0xFF00_0000
 write-ctrl 0x0C0F 0xFF000000
-
+sleep 10
 # Turn on MMUBAR at 0xFF04_0000
 #write-ctrl 0x0008	0xFF000001
 #write 0xFF000008 0x00000000 4
 
 # Turn on RAMBAR0 at address FF10_0000 
 write-ctrl 0x0C04 0xFF100007
-
+sleep 10
 # Turn on RAMBAR1 at address FF10_1000 
 write-ctrl 0x0C05 0xFF101001
-
+sleep 10
 # Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
 write 0xFF000500 0xE0000000 4
 write 0xFF000508 0x00001180 4  # 16-bit port
 write 0xFF000504 0x007F0001 4
-
+sleep 10
 # SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
 write 0xFF000004 0x000002AA 4	# SDRAMDS configuration
+sleep 10
 write 0xFF000020 0x0000001A 4	# SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+sleep 10
 write 0xFF000024 0x0800001A 4	# SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+sleep 10
 write 0xFF000028 0x1000001A 4	# SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
+sleep 10
 write 0xFF00002C 0x1800001A 4	# SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+sleep 10
 write 0xFF000108 0x73622830 4	# SDCFG1
+sleep 10
 write 0xFF00010C 0x46770000 4	# SDCFG2
+sleep 10
 
 write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
+sleep 10
 write 0xFF000100 0x40010000 4	# SDMR (write to LEMR)
+sleep 10
 write 0xFF000100 0x048D0000 4	# SDMR (write to LMR)
+sleep 10
 write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
+sleep 10
 write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
+sleep 10
 write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
+sleep 10
 write 0xFF000100 0x008D0000 4	# SDMR (write to LMR)
+sleep 10
 write 0xFF000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
 
 load -v ram.s19.elf