sorted sources per functionality in different subdirs
This commit is contained in:
Markus Fröschle
406
sys/mmu.c
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406
sys/mmu.c
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@@ -0,0 +1,406 @@
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#include "mmu.h"
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#include "acia.h"
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/*
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* mmu.c
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* derived from original assembler sources:
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2013 M. Froeschle
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*/
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#define ACR_BA(x) ((x) & 0xffff0000)
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#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
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#define ACR_E(x) (((x) & 1) << 15)
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#define ACR_S(x) (((x) & 3) << 13)
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#define ACR_S_USERMODE 0
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#define ACR_S_SUPERVISOR_MODE 1
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#define ACR_S_ALL 2
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#define ACR_AMM(x) (((x) & 1) << 10)
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#define ACR_CM(x) (((x) & 3) << 5)
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#define ACR_CM_CACHEABLE_WT 0x0
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#define ACR_CM_CACHEABLE_CB 0x1
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#define ACR_CM_CACHE_INH_PRECISE 0x2
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#define ACR_CM_CACHE_INH_IMPRECISE 0x3
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#define ACR_SP(x) (((x) & 1) << 3)
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#define ACR_W(x) (((x) & 1) << 2)
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#include <stdint.h>
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#include "bas_printf.h"
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#include "bas_types.h"
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#include "MCF5475.h"
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#include "pci.h"
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#include "cache.h"
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#if MACHINE_FIREBEE
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#include "firebee.h"
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#elif MACHINE_M5484LITE
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#include "m5484l.h"
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#endif /* MACHINE_FIREBEE */
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#define DEBUG_MMU
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#ifdef DEBUG_MMU
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#define dbg_mmu(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg);} while(0)
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#else
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#define dbg_mmu(format, arg...) do {;} while (0)
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#endif /* DEBUG_MMU */
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/*
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* set ASID register
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* saves new value to rt_asid and returns former value
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*/
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inline uint32_t set_asid(uint32_t value)
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{
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extern long rt_asid;
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uint32_t ret = rt_asid;
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__asm__ __volatile__(
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"movec %[value],ASID\n\t"
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: /* no output */
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: [value] "r" (value)
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:
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);
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rt_asid = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr0(uint32_t value)
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{
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extern uint32_t rt_acr0;
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uint32_t ret = rt_acr0;
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__asm__ __volatile__(
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"movec %[value],ACR0\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr0 = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr1(uint32_t value)
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{
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extern uint32_t rt_acr1;
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uint32_t ret = rt_acr1;
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__asm__ __volatile__(
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"movec %[value],ACR1\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr1 = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr2(uint32_t value)
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{
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extern uint32_t rt_acr2;
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uint32_t ret = rt_acr2;
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__asm__ __volatile__(
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"movec %[value],ACR2\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr2 = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr3(uint32_t value)
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{
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extern uint32_t rt_acr3;
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uint32_t ret = rt_acr3;
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__asm__ __volatile__(
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"movec %[value],ACR3\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr3 = value;
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return ret;
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}
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inline uint32_t set_mmubar(uint32_t value)
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{
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extern uint32_t rt_mmubar;
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uint32_t ret = rt_mmubar;
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__asm__ __volatile__(
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"movec %[value],MMUBAR\n\t"
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: /* no output */
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: [value] "r" (value)
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: /* no clobber */
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);
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rt_mmubar = value;
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return ret;
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}
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void mmu_init(void)
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{
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extern uint8_t _MMUBAR[];
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uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
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extern uint8_t _TOS[];
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uint32_t TOS = (uint32_t) &_TOS[0];
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set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */
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/* set data access attributes in ACR0 and ACR1 */
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set_acr0(ACR_W(0) | /* read and write accesses permitted */
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ACR_SP(0) | /* supervisor and user mode access permitted */
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ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
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ACR_AMM(0) | /* control region > 16 MB */
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ACR_S(ACR_S_ALL) | /* match addresses in user and supervisor mode */
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ACR_E(1) | /* enable ACR */
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#if MACHINE_FIREBEE
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ACR_ADMSK(0x3f) | /* cover 1GB area from 0xc0000000 to 0xffffffff */
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ACR_BA(0xc0000000)); /* (equals area from 3 to 4 GB */
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#elif MACHINE_M5484LITE
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ACR_ADMSK(0xff) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
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ACR_BA(0x80000000));
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#endif /* MACHINE_FIREBEE */
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// set_acr1(0x601fc000);
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set_acr1(ACR_W(0) |
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ACR_SP(0) |
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ACR_CM(0) |
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#if MACHINE_FIREBEE
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ACR_CM(ACR_CM_CACHEABLE_WT) | /* video RAM on the Firebee */
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#elif MACHINE_M5484LITE
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ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* Compact Flash on the M548xLITE */
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#endif /* MACHINE_FIREBEE */
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ACR_AMM(0) |
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ACR_S(ACR_S_ALL) |
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ACR_E(1) |
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ACR_ADMSK(0x1f) |
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ACR_BA(0x60000000));
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/* set instruction access attributes in ACR2 and ACR3 */
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//set_acr2(0xe007c400);
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set_acr2(ACR_W(0) |
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ACR_SP(0) |
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ACR_CM(0) |
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ACR_CM(ACR_CM_CACHEABLE_WT) |
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ACR_AMM(1) |
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ACR_S(ACR_S_ALL) |
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ACR_E(1) |
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ACR_ADMSK(0x7) |
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ACR_BA(0xe0000000));
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/* disable ACR3 */
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set_acr3(0x0);
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set_mmubar(MMUBAR | 1); /* set and enable MMUBAR */
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/* clear all MMU TLB entries */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA;
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/* create locked TLB entries */
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/*
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* 0x0000'0000 - 0x000F'FFFF (first MB of physical memory) locked virtual = physical
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*/
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MCF_MMU_MMUTR = 0x0 | /* virtual address */
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MCF_MMU_MMUTR_SG | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = 0x0 | /* physical address */
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MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
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MCF_MMU_MMUDR_CM(0x1) | /* cacheable, copyback */
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MCF_MMU_MMUDR_R | /* read access enable */
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MCF_MMU_MMUDR_W | /* write access enable */
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MCF_MMU_MMUDR_X | /* execute access enable */
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MCF_MMU_MMUDR_LK; /* lock entry */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
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MCF_MMU_MMUOR_ACC | /* access TLB */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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#if MACHINE_FIREBEE /* map FPGA video memory for FireBee only */
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/*
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* 0x00d0'0000 - 0x00df'ffff (last megabyte of ST RAM = Falcon video memory) locked ID = 6
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* mapped to physical address 0x60d0'0000 (FPGA video memory)
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* video RAM: read write execute normal write true
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*/
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MCF_MMU_MMUTR = 0x00d00000 | /* virtual address */
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MCF_MMU_MMUTR_ID(SCA_PAGE_ID) |
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MCF_MMU_MMUTR_SG | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = 0x60d00000 | /* physical address */
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MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
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MCF_MMU_MMUDR_CM(0x0) | /* cachable writethrough */
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MCF_MMU_MMUDR_SP | /* supervisor protect */
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MCF_MMU_MMUDR_R | /* read access enable */
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MCF_MMU_MMUDR_W | /* write access enable */
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MCF_MMU_MMUDR_X | /* execute access enable */
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MCF_MMU_MMUDR_LK; /* lock entry */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
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MCF_MMU_MMUOR_ACC | /* access TLB */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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video_tlb = 0x2000; /* set page as video page */
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video_sbt = 0x0; /* clear time */
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#endif /* MACHINE_FIREBEE */
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/*
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* Make the TOS (in SDRAM) read-only
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* This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
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*/
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MCF_MMU_MMUTR = TOS | /* virtual address */
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MCF_MMU_MMUTR_SG | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = TOS | /* physical address */
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MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
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MCF_MMU_MMUDR_CM(0x1) | /* cachable copyback */
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MCF_MMU_MMUDR_R | /* read access enable */
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MCF_MMU_MMUDR_W | /* write access enable (FIXME: for now) */
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MCF_MMU_MMUDR_X | /* execute access enable */
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MCF_MMU_MMUDR_LK; /* lock entry */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
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MCF_MMU_MMUOR_ACC | /* access TLB */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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#if MACHINE_FIREBEE
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/*
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* Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O
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* area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee
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*/
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MCF_MMU_MMUTR = 0x00f00000 | /* virtual address */
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MCF_MMU_MMUTR_SG | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = 0xfff00000 | /* physical address */
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MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
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MCF_MMU_MMUDR_CM(0x2) | /* nocache precise */
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MCF_MMU_MMUDR_SP | /* supervisor protect */
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MCF_MMU_MMUDR_R | /* read access enable */
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MCF_MMU_MMUDR_W | /* write access enable */
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MCF_MMU_MMUDR_X | /* execute access enable */
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MCF_MMU_MMUDR_LK; /* lock entry */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
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MCF_MMU_MMUOR_ACC | /* access TLB */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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#endif /* MACHINE_FIREBEE */
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/*
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* Map (locked) the last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
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* virtual address. This is also used when BaS is in RAM
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*/
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MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00100000) | /* virtual address */
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MCF_MMU_MMUTR_SG | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00100000) | /* physical address */
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MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
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MCF_MMU_MMUDR_CM(0x0) | /* cacheable writethrough */
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MCF_MMU_MMUDR_SP | /* supervisor protect */
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MCF_MMU_MMUDR_R | /* read access enable */
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MCF_MMU_MMUDR_W | /* write access enable */
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MCF_MMU_MMUDR_X | /* execute access enable */
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MCF_MMU_MMUDR_LK; /* lock entry */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
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MCF_MMU_MMUOR_ACC | /* access TLB */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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}
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void mmutr_miss(void)
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{
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register uint32_t address asm("d0");
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dbg_mmu("MMU TLB MISS at 0x%08x\r\n", address);
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flush_and_invalidate_caches();
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switch (address)
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{
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case keyctl:
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case keybd:
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/* do something to emulate the IKBD access */
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dbg_mmu("IKBD access\r\n");
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break;
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case midictl:
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case midi:
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/* do something to emulate MIDI access */
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dbg_mmu("MIDI ACIA access\r\n");
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break;
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default:
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/* add missed page to TLB */
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MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */
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MCF_MMU_MMUTR_SG | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = (address & 0xfff00000) | /* physical aligned to 1M */
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MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
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MCF_MMU_MMUDR_CM(0x1) | /* cacheable copyback */
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MCF_MMU_MMUDR_R | /* read access enable */
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MCF_MMU_MMUDR_W | /* write access enable */
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MCF_MMU_MMUDR_X; /* execute access enable */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
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MCF_MMU_MMUOR_ACC | /* access TLB */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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}
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}
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