From 6880e4c3a01fce332777fa4d5dfdbea75d3a286a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Sun, 20 Nov 2016 19:25:18 +0000
Subject: [PATCH] change PCI area cache mode to CACHE_NOCACHE_PRECISE

---
 BaS_gcc/radeon/radeon_accel.c | 4 ++--
 BaS_gcc/sys/mmu.c             | 6 ++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/BaS_gcc/radeon/radeon_accel.c b/BaS_gcc/radeon/radeon_accel.c
index 6b1a0bb..0dc80a2 100644
--- a/BaS_gcc/radeon/radeon_accel.c
+++ b/BaS_gcc/radeon/radeon_accel.c
@@ -595,8 +595,8 @@ void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_i
 #else
     BEGIN_ACCEL(4);
 #endif
-    OUT_ACCEL_REG(SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff));
-    OUT_ACCEL_REG(SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff));
+    OUT_ACCEL_REG(SC_TOP_LEFT, (y << 16) | ((x + skipleft) & 0xffff));
+    OUT_ACCEL_REG(SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x + w) & 0xffff));
     OUT_ACCEL_REG(DST_Y_X, (y << 16) | (x & 0xffff));
     /* Have to pad the width here and use clipping engine */
     OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | ((w + 31) & ~31));
diff --git a/BaS_gcc/sys/mmu.c b/BaS_gcc/sys/mmu.c
index ae2659e..15a7574 100644
--- a/BaS_gcc/sys/mmu.c
+++ b/BaS_gcc/sys/mmu.c
@@ -297,7 +297,7 @@ int mmu_map_instruction_page(uint32_t virt, uint8_t asid)
 
 struct mmu_page_descriptor_ram pci_descriptor =
 {
-    .cache_mode = CACHE_COPYBACK,
+    .cache_mode = CACHE_NOCACHE_PRECISE,
     .supervisor_protect = 0,
     .read = 1,
     .write = 1,
@@ -327,7 +327,9 @@ int mmu_map_data_page(uint32_t virt, uint8_t asid)
     {
         phys = virt;
         page = &pci_descriptor;
-    };
+    }
+    else
+        return 0;