From 6378f345408905c6a0d4238c60e535ea756fcfe6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 4 Jan 2014 09:23:32 +0000 Subject: [PATCH] removed unused code --- BaS_gcc/x86emu/x86biosemu.c | 260 +----------------------------------- 1 file changed, 5 insertions(+), 255 deletions(-) diff --git a/BaS_gcc/x86emu/x86biosemu.c b/BaS_gcc/x86emu/x86biosemu.c index 19d633f..7a226c3 100644 --- a/BaS_gcc/x86emu/x86biosemu.c +++ b/BaS_gcc/x86emu/x86biosemu.c @@ -244,106 +244,6 @@ void do_int(int num) ret = run_bios_int(num); } -#if 0 - -void reset_int_vect(void) -{ - /* - * This table is normally located at 0xF000:0xF0A4. However, int 0x42, - * function 0 (Mode Set) expects it (or a copy) somewhere in the bottom - * 64kB. Note that because this data doesn't survive POST, int 0x42 should - * only be used during EGA/VGA BIOS initialisation. - */ - static const uint8_t VideoParms[] = { - /* Timing for modes 0x00 & 0x01 */ - 0x38, 0x28, 0x2d, 0x0a, 0x1f, 0x06, 0x19, 0x1c, - 0x02, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, - /* Timing for modes 0x02 & 0x03 */ - 0x71, 0x50, 0x5a, 0x0a, 0x1f, 0x06, 0x19, 0x1c, - 0x02, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, - /* Timing for modes 0x04, 0x05 & 0x06 */ - 0x38, 0x28, 0x2d, 0x0a, 0x7f, 0x06, 0x64, 0x70, - 0x02, 0x01, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, - /* Timing for mode 0x07 */ - 0x61, 0x50, 0x52, 0x0f, 0x19, 0x06, 0x19, 0x19, - 0x02, 0x0d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00, - /* Display page lengths in little endian order */ - 0x00, 0x08, /* Modes 0x00 and 0x01 */ - 0x00, 0x10, /* Modes 0x02 and 0x03 */ - 0x00, 0x40, /* Modes 0x04 and 0x05 */ - 0x00, 0x40, /* Modes 0x06 and 0x07 */ - /* Number of columns for each mode */ - 40, 40, 80, 80, 40, 40, 80, 80, - /* CGA Mode register value for each mode */ - 0x2c, 0x28, 0x2d, 0x29, 0x2a, 0x2e, 0x1e, 0x29, - /* Padding */ - 0x00, 0x00, 0x00, 0x00 - }; - int i; - - for(i = 0; i < sizeof(VideoParms); i++) - MEM_WB(i + (0x1000 - sizeof(VideoParms)), VideoParms[i]); - MEM_WW(0x1d << 2, 0x1000 - sizeof(VideoParms)); - MEM_WW((0x1d << 2) + 2, 0); - - DPRINT("SETUP INT\r\n"); - MEM_WW(0x10 << 2, 0xf065); - MEM_WW((0x10 << 2) + 2, SYS_BIOS >> 4); - MEM_WW(0x42 << 2, 0xf065); - MEM_WW((0x42 << 2) + 2, SYS_BIOS >> 4); - MEM_WW(0x6D << 2, 0xf065); - MEM_WW((0x6D << 2) + 2, SYS_BIOS >> 4); -} - -/* - * here we are really paranoid about faking a "real" - * BIOS. Most of this information was pulled from - * dosemu. - */ -void setup_int_vect(void) -{ - int i; - - /* let the int vects point to the SYS_BIOS seg */ - for(i = 0; i < 0x80; i++) - { - MEM_WW(i << 2, 0); - MEM_WW((i << 2) + 2, SYS_BIOS >> 4); - } - - reset_int_vect(); - - /* font tables default location (int 1F) */ - MEM_WW(0x1f << 2, 0xfa6e); - /* int 11 default location (Get Equipment Configuration) */ - MEM_WW(0x11 << 2, 0xf84d); - /* int 12 default location (Get Conventional Memory Size) */ - MEM_WW(0x12 << 2, 0xf841); - /* int 15 default location (I/O System Extensions) */ - MEM_WW(0x15 << 2, 0xf859); - /* int 1A default location (RTC, PCI and others) */ - MEM_WW(0x1a << 2, 0xff6e); - /* int 05 default location (Bound Exceeded) */ - MEM_WW(0x05 << 2, 0xff54); - /* int 08 default location (Double Fault) */ - MEM_WW(0x08 << 2, 0xfea5); - /* int 13 default location (Disk) */ - MEM_WW(0x13 << 2, 0xec59); - /* int 0E default location (Page Fault) */ - MEM_WW(0x0e << 2, 0xef57); - /* int 17 default location (Parallel Port) */ - MEM_WW(0x17 << 2, 0xefd2); - /* fdd table default location (int 1e) */ - MEM_WW(0x1e << 2, 0xefc7); - - /* Set Equipment flag to VGA */ - i = MEM_RB(0x0410) & 0xCF; - MEM_WB(0x0410, i); - /* XXX Perhaps setup more of the BDA here. See also int42(0x00). */ -} - -#endif - static int setup_system_bios(void *base_addr) { char *base = (char *) base_addr; @@ -358,159 +258,6 @@ static int setup_system_bios(void *base_addr) return(1); } -#if 0 - -static void memsetw(uint32_t addr, uint16_t value, uint16_t count) -{ - while(--count) - { - wrw(addr, value); - addr += 2; - } -} - -static uint8_t find_vga_entry(uint8_t mode) -{ - uint8_t i,line=0xFF; - for(i=0;i<=MODE_MAX;i++) - { - if (vga_modes[i].svgamode==mode) - { - line=i; - break; - } - } return(line); -} - -void biosfn_set_video_mode(uint8_t mode) -{ - uint8_t line,mmask,*palette=0,vpti; - uint16_t i,twidth,theightm1,cheight; - uint8_t modeset_ctl=0; - uint16_t crtc_addr; - // find the entry in the video modes - line=find_vga_entry(mode); - if (line==0xFF) - return; - vpti=line_to_vpti[line]; - twidth=video_param_table[vpti].twidth; - theightm1=video_param_table[vpti].theightm1; - cheight=video_param_table[vpti].cheight; - // if palette loading (bit 3 of modeset ctl = 0) - if ((modeset_ctl&0x08)==0) - { - // Set the PEL mask - outb(vga_modes[line].pelmask,VGAREG_PEL_MASK); - // Set the whole dac always, from 0 - outb(0x00,VGAREG_DAC_WRITE_ADDRESS); - // From which palette - switch(vga_modes[line].dacmodel) - { - case 0: palette=palette0; break; - case 1: palette=palette1; break; - case 2: palette=palette2; break; - case 3: palette=palette3; break; - } - // Always 256*3 values - for(i=0;i<0x0100;i++) - { - if (i<=dac_regs[vga_modes[line].dacmodel]) - { - outb(palette[(i*3)+0],VGAREG_DAC_DATA); - outb(palette[(i*3)+1],VGAREG_DAC_DATA); - outb(palette[(i*3)+2],VGAREG_DAC_DATA); - } - else - { - outb(0,VGAREG_DAC_DATA); - outb(0,VGAREG_DAC_DATA); - outb(0,VGAREG_DAC_DATA); - } - } - if ((modeset_ctl&0x02)==0x02) - { - uint8_t r,g,b; - uint16_t i; - uint16_t index,start=0; - inb(VGAREG_ACTL_RESET); - outb(0x00,VGAREG_ACTL_ADDRESS); - for(index = 0; index < 0x100; index++) - { - // set read address and switch to read mode - outb(start,VGAREG_DAC_READ_ADDRESS); - // get 6-bit wide RGB data values - r=inb(VGAREG_DAC_DATA); - g=inb(VGAREG_DAC_DATA); - b=inb(VGAREG_DAC_DATA); - // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue ) - i = ((77*r + 151*g + 28*b) + 0x80) >> 8; - if (i>0x3f) - i=0x3f; - // set write address and switch to write mode - outb(start,VGAREG_DAC_WRITE_ADDRESS); - // write new intensity value - outb(i & 0xff,VGAREG_DAC_DATA); - outb(i & 0xff,VGAREG_DAC_DATA); - outb(i & 0xff,VGAREG_DAC_DATA); - start++; - } - inb(VGAREG_ACTL_RESET); - outb(0x20,VGAREG_ACTL_ADDRESS); - } - } - // Reset Attribute Ctl flip-flop - inb(VGAREG_ACTL_RESET); - // Set Attribute Ctl - for(i=0;i<=0x13;i++) - { - outb(i,VGAREG_ACTL_ADDRESS); - outb(video_param_table[vpti].actl_regs[i],VGAREG_ACTL_WRITE_DATA); - } - outb(0x14,VGAREG_ACTL_ADDRESS); - outb(0x00,VGAREG_ACTL_WRITE_DATA); - // Set Sequencer Ctl - outb(0,VGAREG_SEQU_ADDRESS); - outb(0x03,VGAREG_SEQU_DATA); - for(i=1;i<=4;i++) - { - outb(i,VGAREG_SEQU_ADDRESS); - outb(video_param_table[vpti].sequ_regs[i - 1],VGAREG_SEQU_DATA); - } - // Set Grafx Ctl - for(i=0;i<=8;i++) - { - outb(i,VGAREG_GRDC_ADDRESS); - outb(video_param_table[vpti].grdc_regs[i],VGAREG_GRDC_DATA); - } - // Set CRTC address VGA - crtc_addr=VGAREG_VGA_CRTC_ADDRESS; - // Disable CRTC write protection - outw(crtc_addr,0x0011); - // Set CRTC regs - for(i=0;i<=0x18;i++) - { - outb(i,crtc_addr); - outb(video_param_table[vpti].crtc_regs[i],crtc_addr+1); - } - // Set the misc register - outb(video_param_table[vpti].miscreg,VGAREG_WRITE_MISC_OUTPUT); - // Enable video - outb(0x20,VGAREG_ACTL_ADDRESS); - inb(VGAREG_ACTL_RESET); - if (mode<0x0d) - memsetw(vga_modes[line].sstart,0x0000,0x4000); // 32k - else - { - outb(0x02, VGAREG_SEQU_ADDRESS); - mmask = inb(VGAREG_SEQU_DATA); - outb(0x0f, VGAREG_SEQU_DATA); // all planes - memsetw(vga_modes[line].sstart, 0x0000, 0x8000); // 64k - outb(mmask, VGAREG_SEQU_DATA); - } -} - -#endif - void run_bios(struct radeonfb_info *rinfo) { long i, j; @@ -528,15 +275,18 @@ void run_bios(struct radeonfb_info *rinfo) if ((rinfo->mmio_base == NULL) || (rinfo->io_base == NULL)) { - dbg("%s: rinfo->mmio_base = %p, rinfo->io_base = %p\r\n", __FUNCTION__, rinfo->mmio_base, rinfo->io_base); + dbg("%s: rinfo->mmio_base = %p, rinfo->io_base = %p\r\n", + __FUNCTION__, rinfo->mmio_base, rinfo->io_base); return; } + rinfo_biosemu = rinfo; config_address_reg = 0; offset_port = 0x300; offset_io = (uint32_t) rinfo->io_base - (uint32_t) offset_port; offset_mem = (uint32_t) rinfo->fb_base - 0xA0000; - rom_header = (struct rom_header *) 0; + + rom_header = NULL; do { rom_header = (struct rom_header *) ((unsigned long) rom_header + image_size); // get next image