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tried, but did not find the cause of access error during alignment of the TD buffers...

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Markus Fröschle
2013-11-04 20:09:32 +00:00
parent a915e69181
commit 5ee4e0a0a4
8 changed files with 57 additions and 37 deletions
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9
BaS_gcc/bas_m5484.bdm
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@@ -22,8 +22,8 @@ write-ctrl 0x0C04 0xFF100007
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
write-ctrl 0x0C05 0xFF101001
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
write 0xFF000500 0xE0080000 4
# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 8Mbytes)
write 0xFF000500 0xE0000000 4
write 0xFF000508 0x00041180 4
write 0xFF000504 0x003F0001 4
wait
@@ -49,9 +49,4 @@ write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
sleep 100
load -v m5484lite/ram.elf
write-ctrl 0x80e 0x2700
write-ctrl 0x2 0xa50c8120
dump-register SR
dump-register CACR
dump-register MBAR
execute