diff --git a/include/interrupts.h b/include/interrupts.h index 48ee4dc..d0d1184 100644 --- a/include/interrupts.h +++ b/include/interrupts.h @@ -99,34 +99,34 @@ #define ISR_USER_ISR 0x02 #if defined(MACHINE_FIREBEE) + /* Firebee FPGA interrupt controller */ -#define FPGA_INTR_CONTROL ((volatile uint32_t *) 0xf0010000) -#define FPGA_INTR_ENABLE ((volatile uint32_t *) 0xf0010004) -#define FPGA_INTR_CLEAR ((volatile uint32_t *) 0xf0010008) -#define FPGA_INTR_PENDING ((volatile uint32_t *) 0xff01000c) +#define FBEE_INTR_CONTROL * ((volatile uint32_t *) 0xf0010000) +#define FBEE_INTR_ENABLE * ((volatile uint32_t *) 0xf0010004) +#define FBEE_INTR_CLEAR * ((volatile uint32_t *) 0xf0010008) +#define FBEE_INTR_PENDING * ((volatile uint32_t *) 0xff01000c) /* register bits for Firebee FPGA-based interrupt controller */ -#define FPGA_INTR_PIC (1) -#define FPGA_INTR_ETHERNET (1 << 1) -#define FPGA_INTR_DVI (1 << 2) -#define FPGA_INTR_PCI_INTA (1 << 3) -#define FPGA_INTR_PCI_INTB (1 << 4) -#define FPGA_INTR_PCI_INTC (1 << 5) -#define FPGA_INTR_PCI_INTD (1 << 6) -#define FPGA_INTR_INT_DSP (1 << 7) -#define FPGA_INTR_INT_VSYNC (1 << 8) -#define FPGA_INTR_INT_HSYNC (1 << 9) -#define FPGA_INTR_INT_HSYNC_IRQ2 (1 << 26) -#define FPGA_INTR_INT_CTR0_IRQ3 (1 << 27) -#define FPGA_INTR_INT_VSYNC_IRQ4 (1 << 28) -#define FPGA_INTR_INT_FPGA_IRQ5 (1 << 29) -#define FPGA_INTR_INT_MFP_IRQ6 (1 << 30) -#define FPGA_INTR_INT_IRQ7 (1 << 31) +#define FBEE_INTR_PIC (1 << 0) /* PIC interrupt enable/pending/clear bit */ +#define FBEE_INTR_ETHERNET (1 << 1) /* ethernet PHY interrupt enable/pending/clear bit */ +#define FBEE_INTR_DVI (1 << 2) /* TFP410 monitor sense interrupt enable/pending/clear bit */ +#define FBEE_INTR_PCI_INTA (1 << 3) /* /PCIINTA enable/pending clear bit */ +#define FBEE_INTR_PCI_INTB (1 << 4) /* /PCIINTB enable/pending clear bit */ +#define FBEE_INTR_PCI_INTC (1 << 5) /* /PCIINTC enable/pending clear bit */ +#define FBEE_INTR_PCI_INTD (1 << 6) /* /PCIINTD enable/pending clear bit */ +#define FBEE_INTR_DSP (1 << 7) /* DSP interrupt enable/pending/clear bit */ +#define FBEE_INTR_VSYNC (1 << 8) /* VSYNC interrupt enable/pending/clear bit */ +#define FBEE_INTR_HSYNC (1 << 9) /* HSYNC interrupt enable/pending/clear bit */ + +#define FBEE_INTR_INT_HSYNC_IRQ2 (1 << 26) /* these bits are only meaningful for the FBEE_INTR_ENABLE register */ +#define FBEE_INTR_INT_CTR0_IRQ3 (1 << 27) +#define FBEE_INTR_INT_VSYNC_IRQ4 (1 << 28) +#define FBEE_INTR_INT_FPGA_IRQ5 (1 << 29) +#define FBEE_INTR_INT_MFP_IRQ6 (1 << 30) +#define FBEE_INTR_INT_IRQ7 (1 << 31) /* * Atari MFP interrupt registers. - * - * TODO: should go into a header file */ #define FALCON_MFP_IERA *((volatile uint8_t *) 0xfffffa07) @@ -136,14 +136,15 @@ #define FALCON_MFP_IMRA *((volatile uint8_t *) 0xfffffa13) #define FALCON_MFP_IMRB *((volatile uint8_t *) 0xfffffa15) -#define vbasehi (* (volatile uint8_t *) 0xffff8201) -#define vbasemid (* (volatile uint8_t *) 0xffff8203) -#define vbaselow (* (volatile uint8_t *) 0xffff820d) - -#define vwrap (* (volatile uint16_t *) 0xffff8210) -#define vde (* (volatile uint16_t *) 0xffff82aa) -#define vdb (* (volatile uint16_t *) 0xffff82a8) +#ifdef _NOT_USED_ +#define vbasehi * ((volatile uint8_t *) 0xffff8201) +#define vbasemid * ((volatile uint8_t *) 0xffff8203) +#define vbaselow * ((volatile uint8_t *) 0xffff820d) +#define vwrap * ((volatile uint16_t *) 0xffff8210) +#define vde * ((volatile uint16_t *) 0xffff82aa) +#define vdb * ((volatile uint16_t *) 0xffff82a8) +#endif /* _NOT_USED_ */ #endif /* MACHINE_FIREBEE */ extern void isr_init(void); diff --git a/sys/BaS.c b/sys/BaS.c index 0f87ff3..bb554d7 100644 --- a/sys/BaS.c +++ b/sys/BaS.c @@ -79,12 +79,12 @@ extern uint8_t _EMUTOS_SIZE[]; */ static inline bool pic_txready(void) { - if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY) + if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY) { - return true; + return true; } - return false; + return false; } /* @@ -92,12 +92,12 @@ static inline bool pic_txready(void) */ static inline bool pic_rxready(void) { - if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY) + if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY) { - return true; + return true; } - return false; + return false; } void write_pic_byte(uint8_t value) @@ -105,12 +105,12 @@ void write_pic_byte(uint8_t value) /* * Wait until the transmitter is ready or 1000us are passed */ - waitfor(1000, pic_txready); + waitfor(1000, pic_txready); /* * Transmit the byte */ - *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit + *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit } uint8_t read_pic_byte(void) @@ -118,152 +118,149 @@ uint8_t read_pic_byte(void) /* * Wait until a byte has been received or 1000us are passed */ - waitfor(1000, pic_rxready); + waitfor(1000, pic_rxready); /* * Return the received byte */ - return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit + return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit } void pic_init(void) { - char answer[4] = "OLD"; + char answer[4] = "OLD"; - xprintf("initialize the PIC: "); + xprintf("initialize the PIC: "); /* * Send the PIC initialization string */ - write_pic_byte('A'); - write_pic_byte('C'); - write_pic_byte('P'); - write_pic_byte('F'); + write_pic_byte('A'); + write_pic_byte('C'); + write_pic_byte('P'); + write_pic_byte('F'); /* * Read the 3-char answer string. Should be "OK!". */ - answer[0] = read_pic_byte(); - answer[1] = read_pic_byte(); - answer[2] = read_pic_byte(); - answer[3] = '\0'; + answer[0] = read_pic_byte(); + answer[1] = read_pic_byte(); + answer[2] = read_pic_byte(); + answer[3] = '\0'; - if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!') - { - dbg("PIC initialization failed. Already initialized?\r\n"); - } - else - { - xprintf("%s\r\n", answer); - } + if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!') + { + dbg("PIC initialization failed. Already initialized?\r\n"); + } + else + { + xprintf("%s\r\n", answer); + } } void nvram_init(void) { - int i; + int i; - xprintf("Restore the NVRAM data: "); + xprintf("Restore the NVRAM data: "); - /* Request for NVRAM backup data */ - write_pic_byte(0x01); + /* Request for NVRAM backup data */ + write_pic_byte(0x01); - /* Check answer type */ - if (read_pic_byte() != 0x81) - { - // FIXME: PIC protocol error - xprintf("FAILED\r\n"); - return; - } + /* Check answer type */ + if (read_pic_byte() != 0x81) + { + // FIXME: PIC protocol error + xprintf("FAILED\r\n"); + return; + } - /* Restore the NVRAM backup to the FPGA */ - for (i = 0; i < 64; i++) - { - uint8_t data = read_pic_byte(); - *(volatile uint8_t*)0xffff8961 = i; - *(volatile uint8_t*)0xffff8963 = data; - } + /* Restore the NVRAM backup to the FPGA */ + for (i = 0; i < 64; i++) + { + uint8_t data = read_pic_byte(); + *(volatile uint8_t*)0xffff8961 = i; + *(volatile uint8_t*)0xffff8963 = data; + } - xprintf("finished\r\n"); + xprintf("finished\r\n"); } -#define KBD_ACIA_CONTROL ((uint8_t *) 0xfffffc00) -#define MIDI_ACIA_CONTROL ((uint8_t *) 0xfffffc04) -#define MFP_INTR_IN_SERVICE_A ((uint8_t *) 0xfffffa0f) -#define MFP_INTR_IN_SERVICE_B ((uint8_t *) 0xfffffa11) +#define KBD_ACIA_CONTROL ((uint8_t *) 0xfffffc00) +#define MIDI_ACIA_CONTROL ((uint8_t *) 0xfffffc04) +#define MFP_INTR_IN_SERVICE_A ((uint8_t *) 0xfffffa0f) +#define MFP_INTR_IN_SERVICE_B ((uint8_t *) 0xfffffa11) void acia_init() { - xprintf("init ACIA: "); - /* init ACIA */ - * KBD_ACIA_CONTROL = 3; /* master reset */ - NOP(); + xprintf("init ACIA: "); + /* init ACIA */ + * KBD_ACIA_CONTROL = 3; /* master reset */ + NOP(); - * MIDI_ACIA_CONTROL = 3; /* master reset */ - NOP(); + * MIDI_ACIA_CONTROL = 3; /* master reset */ + NOP(); - * KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */ - NOP(); + * KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */ + NOP(); - * MFP_INTR_IN_SERVICE_A = -1; - NOP(); + * MFP_INTR_IN_SERVICE_A = -1; + NOP(); - * MFP_INTR_IN_SERVICE_B = -1; - NOP(); + * MFP_INTR_IN_SERVICE_B = -1; + NOP(); - xprintf("finished\r\n"); + xprintf("finished\r\n"); } void enable_coldfire_interrupts() { - xprintf("enable interrupts: "); + xprintf("enable interrupts: "); #if defined(MACHINE_FIREBEE) - *FPGA_INTR_CONTROL = 0L; /* disable all interrupts */ + FBEE_INTR_CONTROL = 0L; /* disable all interrupts */ #endif /* MACHINE_FIREBEE */ - MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */ + MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */ #if defined(MACHINE_FIREBEE) - /* - * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write - * access to 0xff8201 (vbasehi), i.e. everytime the video base address is written - */ - MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */ - MCF_GPT_GMS_IEN | - MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */ - MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) | - MCF_INTC_ICR_IP(7); /* interrupt level 7, interrupt priority 7 */ + /* + * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write + * access to 0xff8201 (vbasehi), i.e. everytime the video base address is written + */ + MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */ + MCF_GPT_GMS_IEN | + MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */ + MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) | + MCF_INTC_ICR_IP(7); /* interrupt level 7, interrupt priority 7 */ - MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */ - MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */ - MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */ - MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */ - *FPGA_INTR_ENABLE = FPGA_INTR_INT_IRQ7 | - FPGA_INTR_INT_MFP_IRQ6 | - FPGA_INTR_INT_FPGA_IRQ5 | - FPGA_INTR_INT_VSYNC_IRQ4 | - FPGA_INTR_INT_CTR0_IRQ3 | - FPGA_INTR_INT_HSYNC_IRQ2 | - FPGA_INTR_PCI_INTA | - FPGA_INTR_PCI_INTB | - FPGA_INTR_PCI_INTC | - FPGA_INTR_PCI_INTD | - FPGA_INTR_ETHERNET; + MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */ + MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */ + MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */ + MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */ + FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */ + FBEE_INTR_INT_MFP_IRQ6 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */ + FBEE_INTR_INT_FPGA_IRQ5 | /* enable MFP interrupts */ + FBEE_INTR_INT_VSYNC_IRQ4 | /* enable vsync interrupts */ + FBEE_INTR_PCI_INTA | /* enable PCI interrupts */ + FBEE_INTR_PCI_INTB | + FBEE_INTR_PCI_INTC | + FBEE_INTR_PCI_INTD; #endif - xprintf("finished\r\n"); + xprintf("finished\r\n"); } void disable_coldfire_interrupts() { #if defined(MACHINE_FIREBEE) - *FPGA_INTR_ENABLE = 0; /* disable all interrupts */ + FBEE_INTR_ENABLE = 0; /* disable all interrupts */ #endif /* MACHINE_FIREBEE */ - MCF_EPORT_EPIER = 0x0; - MCF_EPORT_EPFR = 0x0; - MCF_INTC_IMRL = 0xfffffffe; - MCF_INTC_IMRH = 0xffffffff; + MCF_EPORT_EPIER = 0x0; + MCF_EPORT_EPFR = 0x0; + MCF_INTC_IMRL = 0xfffffffe; + MCF_INTC_IMRH = 0xffffffff; } @@ -278,181 +275,181 @@ NIF nif2; */ void init_isr(void) { - isr_init(); /* need to call that explicitely, otherwise isr table might be full */ + isr_init(); /* need to call that explicitely, otherwise isr table might be full */ - /* - * register the FEC interrupt handler - */ - if (!isr_register_handler(64 + INT_SOURCE_FEC0, fec0_interrupt_handler, NULL, (void *) &nif1)) - { - dbg("unable to register isr for FEC0\r\n"); - return; - } + /* + * register the FEC interrupt handler + */ + if (!isr_register_handler(64 + INT_SOURCE_FEC0, fec0_interrupt_handler, NULL, (void *) &nif1)) + { + dbg("unable to register isr for FEC0\r\n"); + return; + } - /* - * Register the DMA interrupt handler - */ + /* + * Register the DMA interrupt handler + */ - if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL,NULL)) - { - dbg("Error: Unable to register isr for DMA\r\n"); - return; - } + if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL,NULL)) + { + dbg("Error: Unable to register isr for DMA\r\n"); + return; + } - dma_irq_enable(5, 3); /* TODO: need to match the FEC driver's specs in MiNT? */ + dma_irq_enable(5, 3); /* TODO: need to match the FEC driver's specs in MiNT? */ - /* - * register the PIC interrupt handler - */ - if (isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL)) - { - dbg("Error: unable to register ISR for PSC3\r\n"); - return; - } + /* + * register the PIC interrupt handler + */ + if (isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL)) + { + dbg("Error: unable to register ISR for PSC3\r\n"); + return; + } - /* - * register the XLB PCI interrupt handler - */ - if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, xlbpci_interrupt_handler, NULL, NULL)) - { - dbg("Error: unable to register isr for XLB PCI interrupts\r\n"); - return; - } - MCF_INTC_ICR43 = MCF_INTC_ICR_IL(5) | /* level 5, priority 1 */ - MCF_INTC_ICR_IP(1); + /* + * register the XLB PCI interrupt handler + */ + if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, xlbpci_interrupt_handler, NULL, NULL)) + { + dbg("Error: unable to register isr for XLB PCI interrupts\r\n"); + return; + } + MCF_INTC_ICR43 = MCF_INTC_ICR_IL(5) | /* level 5, priority 1 */ + MCF_INTC_ICR_IP(1); - MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */ - MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */ - MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */ - MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */ - MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */ - MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */ - MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */ + MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */ + MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */ + MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */ + MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */ + MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */ + MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */ + MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */ - if (!isr_register_handler(64 + INT_SOURCE_PCIARB, pciarb_interrupt_handler, NULL, NULL)) - { - dbg("Error: unable to register isr for PCIARB interrupts\r\n"); + if (!isr_register_handler(64 + INT_SOURCE_PCIARB, pciarb_interrupt_handler, NULL, NULL)) + { + dbg("Error: unable to register isr for PCIARB interrupts\r\n"); - return; - } - MCF_INTC_ICR41 = MCF_INTC_ICR_IL(5) | /* level 5, priority 0 */ - MCF_INTC_ICR_IP(0); + return; + } + MCF_INTC_ICR41 = MCF_INTC_ICR_IL(5) | /* level 5, priority 0 */ + MCF_INTC_ICR_IP(0); - MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */ - MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */ + MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */ + MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */ } void BaS(void) { - uint8_t *src; - uint8_t *dst = (uint8_t *) TOS; + uint8_t *src; + uint8_t *dst = (uint8_t *) TOS; #if defined(MACHINE_FIREBEE) /* LITE board has no pic and (currently) no nvram */ - pic_init(); - nvram_init(); + pic_init(); + nvram_init(); #endif /* MACHINE_FIREBEE */ - xprintf("copy EmuTOS: "); + xprintf("copy EmuTOS: "); - /* copy EMUTOS */ - src = (uint8_t *) EMUTOS; - dma_memcpy(dst, src, EMUTOS_SIZE); - xprintf("finished\r\n"); + /* copy EMUTOS */ + src = (uint8_t *) EMUTOS; + dma_memcpy(dst, src, EMUTOS_SIZE); + xprintf("finished\r\n"); - xprintf("initialize MMU: "); - mmu_init(); - xprintf("finished\r\n"); + xprintf("initialize MMU: "); + mmu_init(); + xprintf("finished\r\n"); - xprintf("initialize exception vector table: "); - vec_init(); - xprintf("finished\r\n"); + xprintf("initialize exception vector table: "); + vec_init(); + xprintf("finished\r\n"); - xprintf("flush caches: "); - flush_and_invalidate_caches(); - xprintf("finished\r\n"); - xprintf("enable MMU: "); - MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */ - NOP(); /* force pipeline sync */ - xprintf("finished\r\n"); + xprintf("flush caches: "); + flush_and_invalidate_caches(); + xprintf("finished\r\n"); + xprintf("enable MMU: "); + MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */ + NOP(); /* force pipeline sync */ + xprintf("finished\r\n"); - #ifdef MACHINE_FIREBEE - xprintf("IDE reset: "); - /* IDE reset */ - * (volatile uint8_t *) (0xffff8802 - 2) = 14; - * (volatile uint8_t *) (0xffff8802 - 0) = 0x80; - wait(1); + #ifdef MACHINE_FIREBEE + xprintf("IDE reset: "); + /* IDE reset */ + * (volatile uint8_t *) (0xffff8802 - 2) = 14; + * (volatile uint8_t *) (0xffff8802 - 0) = 0x80; + wait(1); - * (volatile uint8_t *) (0xffff8802 - 0) = 0; + * (volatile uint8_t *) (0xffff8802 - 0) = 0; - xprintf("finished\r\n"); - xprintf("enable video: "); - /* - * video setup (25MHz) - */ - * (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba; /* horizontal 640x480 */ - * (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a; /* vertical 640x480 */ - * (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d; /* horizontal 320x240 */ - * (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */ + xprintf("finished\r\n"); + xprintf("enable video: "); + /* + * video setup (25MHz) + */ + * (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba; /* horizontal 640x480 */ + * (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a; /* vertical 640x480 */ + * (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d; /* horizontal 320x240 */ + * (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */ - /* fifo on, refresh on, ddrcs and cke on, video dac on */ - * (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002; + /* fifo on, refresh on, ddrcs and cke on, video dac on */ + * (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002; - xprintf("finished\r\n"); + xprintf("finished\r\n"); #endif /* MACHINE_FIREBEE */ - sd_card_init(); + sd_card_init(); - /* - * memory setup - */ - memset((void *) 0x400, 0, 0x400); + /* + * memory setup + */ + memset((void *) 0x400, 0, 0x400); #if defined(MACHINE_FIREBEE) - /* set Falcon bus control register */ - /* sets bit 3 and 6. Both are undefined on an original Falcon? */ + /* set Falcon bus control register */ + /* sets bit 3 and 6. Both are undefined on an original Falcon? */ - * (volatile uint8_t *) 0xffff8007 = 0x48; + * (volatile uint8_t *) 0xffff8007 = 0x48; #endif /* MACHINE_FIREBEE */ - /* ST RAM */ + /* ST RAM */ - * (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */ - * (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */ - * (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */ - * (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */ + * (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */ + * (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */ + * (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */ + * (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */ - /* TT-RAM */ + /* TT-RAM */ - * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */ - * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ + * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ #if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */ - acia_init(); + acia_init(); #endif /* MACHINE_FIREBEE */ - srec_execute("BASFLASH.S19"); + srec_execute("BASFLASH.S19"); - /* Jump into the OS */ - typedef void void_func(void); - struct rom_header - { - void *initial_sp; - void_func *initial_pc; - }; + /* Jump into the OS */ + typedef void void_func(void); + struct rom_header + { + void *initial_sp; + void_func *initial_pc; + }; - xprintf("BaS initialization finished, enable interrupts\r\n"); - init_isr(); - enable_coldfire_interrupts(); - init_pci(); - video_init(); - set_ipl(0); /* enable interrupts */ + xprintf("BaS initialization finished, enable interrupts\r\n"); + init_isr(); + enable_coldfire_interrupts(); + init_pci(); + video_init(); + set_ipl(0); /* enable interrupts */ - /* initialize USB devices */ - init_usb(); + /* initialize USB devices */ + init_usb(); - //set_ipl(7); /* disable interrupts */ + //set_ipl(7); /* disable interrupts */ - xprintf("call EmuTOS\r\n"); - struct rom_header *os_header = (struct rom_header *) TOS; - os_header->initial_pc(); + xprintf("call EmuTOS\r\n"); + struct rom_header *os_header = (struct rom_header *) TOS; + os_header->initial_pc(); } diff --git a/sys/exceptions.S b/sys/exceptions.S index 4827823..68e954b 100644 --- a/sys/exceptions.S +++ b/sys/exceptions.S @@ -186,22 +186,6 @@ init_vec_loop: move.l a1,0x80(a0) // trap #0 exception vector #ifdef MACHINE_FIREBEE -// ACP interrupts 1-7 (user-defined, generated by FPGA on the FireBee, M5484LITE has irq7 and irq5 for PCI) - lea mfp_irq1(pc),a1 - move.l a1,0x104(a0) - lea mfp_irq2(pc),a1 - move.l a1,0x108(a0) - lea mfp_irq3(pc),a1 - move.l a1,0x10c(a0) - lea mfp_irq4(pc),a1 - move.l a1,0x110(a0) - lea mfp_irq5(pc),a1 - move.l a1,0x114(a0) - lea mfp_irq6(pc),a1 - move.l a1,0x118(a0) - lea mfp_irq7(pc),a1 - move.l a1,0x11c(a0) - // timer vectors (triggers when vbashi gets changed, used for video page copy) lea handler_gpt0(pc),a1 @@ -229,7 +213,7 @@ init_vec_loop: move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0) #endif -// install lowlevel_isr_handler for DMA interrupts +// install lowlevel_isr_handler for Coldfire DMA interrupts move.l a1,(INT_SOURCE_DMA + 64) * 4(a0) move.l (sp)+,a2 // Restore registers @@ -381,41 +365,8 @@ flpoow: nop #endif /* _NOT_USED */ -irq1: - irq 0x64,1,0x02 // IRQ1 -irq2: - irq 0x68,2,0x04 // IRQ2 - -irq3: - irq 0x6c,3,0x08 // IRQ3 - -irq4: - irq 0x70,4,0x10 // IRQ4 - -irq5: - irq 0x74,5,0x20 // IRQ5 - -irq6: - irq 0x78,6,0x40 // IRQ6 - -irq7: - irq 0x7c,7,0x80 // IRQ7 - -mfp_irq1: - irq 0x104,1,0x02 // MFP IRQ1 - -mfp_irq2: - irq 0x108,2,0x04 // MFP IRQ2 - -mfp_irq3: - irq 0x10c,3,0x08 // MFP IRQ3 - -mfp_irq4: - irq 0x110,4,0x10 // MFP IRQ4 - - -#if MACHINE_M5484LITE_notyet // handlers for M5484LITE +#if MACHINE_M5484LITE // handlers for M5484LITE irq5: // irq5 is tied to PCI INTC# and PCI INTD# on the M5484LITE move.w #0x2700,sr // disable interrupts @@ -458,7 +409,7 @@ irq7text: .text #elif MACHINE_FIREBEE /* these handlers are only meaningful for the Firebee */ -mfp_irq5: move.w #0x2700,sr // disable interrupts +irq5: move.w #0x2700,sr // disable interrupts subq.l #4,sp // extra space link a6,#-4 * 4 // save gcc scratch registers @@ -484,9 +435,10 @@ irq5_forward: move.l 0x74,a0 // fetch OS irq5 vector move.w #0x2500,sr // set interrupt level rts // jump through vector -#ifdef _NOT_USED_ -mfp_irq6: move.w #0x2700,sr // disable interrupt + +irq6: move.w #0x2700,sr // disable interrupt subq.l #4,sp // extra space + link a6,#-4 * 4 // save gcc scratch registers movem.l d0-d1/a0-a1,(sp) @@ -503,8 +455,8 @@ mfp_irq6: move.w #0x2700,sr // disable interrupt addq.l #4,sp // "extra space" not needed in this case rte -mfp_irq6_forward: - move.l 0xf0020000,a0 // fetch FPGA "autovector" +irq6_forward: + move.l 0xf0020000,a0 // fetch FPGA "MFP autovector" add.l _rt_vbr,a0 // add runtime VBR move.l (a0),4(a6) // fetch handler address and put it on "extra space" @@ -514,147 +466,10 @@ mfp_irq6_forward: rts // jump through vector -#else /* _NOT_USED_ */ - - // this is the old code from Fredi - -mfp_irq6: - // MFP interrupt from FPGA - move.w #0x2700,sr // disable interrupt - subq.l #8,sp - movem.l d0/a5,(sp) // save registers - - lea MCF_EPORT_EPFR,a5 // clear int6 from edge port - bset #6,(a5) - -mfp_irq6_non_sca: -// test auf acsi dma ----------------------------------------------------------------- - lea 0xfffffa0b,a5 - bset #7,-4(a5) // int ena - btst.b #7,(a5) // acsi dma int? - beq mfp_non_acsi_dma - bsr acsi_dma -mfp_non_acsi_dma: -// ---------------------------------------------------------------------------------- - tst.b (a5) - bne mfp_irq6_1 - tst.b 2(a5) - bne mfp_irq6_1 - movem.l (sp),d0/a5 - addq.l #8,sp - rte -mfp_irq6_1: - lea MCF_GPIO_PODR_FEC1L,a5 - bclr.b #4,(a5) // led on - lea blinker,a5 - addq.l #1,(a5) // +1 - move.l (a5),d0 - and.l #0x80,d0 - bne mfp_irq6_2 - lea MCF_GPIO_PODR_FEC1L,a5 - bset.b #4,(a5) // led off - -/* - * Firebee inthandler. 0xf0020000 delivers the interrupt vector - * - * 0: PIC_INT - * 1: E0_INT - * 2: DVI_INT - * 3: PCI_INT#A - * 4: PCI_INT#B - * 5: PCI_INT#C - * 6: PCI_INT#D - * 7: DSP_INT - * 8: VSYNC - * 9: HSYNC - */ - -mfp_irq6_2: - move.l 0xF0020000,a5 // vector holen - add.l _rt_vbr,a5 // basis - move.l (a5),d0 // vector holen - move.l 4(sp),a5 // a5 zurück - move.l d0,4(sp) // vector eintragen - move.l (sp)+,d0 // d0 zurück - move #0x2600,sr - rts - - .data -blinker:.long 0 - - - .text - -/* - * pseudo dma - */ -acsi_dma: // atari dma - move.l a1,-(sp) - move.l d1,-(sp) - - //lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr - //mchar move.l, 'D,'M','A,'\ ,(a1) - //move.l #"DMA ",(a1) - //mchar move.l,'I,'N,'T,'!,(a1) - //move.l #'INT!',(a1) - - lea 0xf0020110,a5 // fifo daten -acsi_dma_start: - move.l -12(a5),a1 // dma adresse - move.l -8(a5),d0 // byt counter - ble acsi_dma_end - btst.b #0,-16(a5) // write? (dma modus reg) - bne acsi_dma_wl // ja-> -acsi_dma_rl: - tst.b -4(a5) // dma req? - bpl acsi_dma_finished // nein-> - move.l (a5),(a1)+ // read 4 bytes - move.l (a5),(a1)+ // read 4 bytes - move.l (a5),(a1)+ // read 4 bytes - move.l (a5),(a1)+ // read 4 bytes - - moveq #'.',d1 - move.b d1,MCF_PSC0_PSCTB_8BIT - - sub.l #16,d0 // byt counter -16 - bpl acsi_dma_rl - bra acsi_dma_finished -acsi_dma_wl: - tst.b -4(a5) // dma req? - bpl acsi_dma_finished // nein-> - move.l (a1)+,(a5) // write 4 byts - move.l (a1)+,(a5) // write 4 byts - move.l (a1)+,(a5) // write 4 byts - move.l (a1)+,(a5) // write 4 byts - - moveq #'.',d1 - move.b d1,MCF_PSC0_PSCTB_8BIT - - sub.l #16,d0 // byt counter -16 - bpl acsi_dma_wl -acsi_dma_finished: - move.l a1,-12(a5) // adresse zur�ck - move.l d0,-8(a5) // byt counter zur�ck -acsi_dma_end: - tst.b -4(a5) // dma req? - bmi acsi_dma_start // ja-> - lea 0xfffffa0b,a5 - bclr.b #7,4(a5) // clear int in service mfp - bclr.b #7,(a5) // clear int pending mfp 0xfffffa0b - - move.w #0x0d0a,d1 - move.w d1,MCF_PSC0_PSCTB_8BIT - - move.l (sp)+,d1 - move.l (sp)+,a1 - rts - -#endif /* _NOT_USED_ */ - /* * irq 7 = pseudo bus error */ -mfp_irq7: +irq7: lea -12(sp),sp movem.l d0/a0,(sp) diff --git a/sys/interrupts.c b/sys/interrupts.c index c6e90c7..84e05d5 100644 --- a/sys/interrupts.c +++ b/sys/interrupts.c @@ -182,7 +182,7 @@ int pic_interrupt_handler(void *arg1, void *arg2) uint8_t *rtc_data = (uint8_t *) 0xffff8963; int index = 0; - err("PIC interrupt: requesting RTC data\r\n"); + err("PIC interrupt: requesting RTC data\r\n"); MCF_PSC3_PSCTB_8BIT = 0x82; // header byte to PIC do @@ -211,50 +211,59 @@ int pciarb_interrupt_handler(void *arg1, void *arg2) #if defined(MACHINE_FIREBEE) /* * This gets called from irq5 in exceptions.S + * + * IRQ5 are the "FBEE" (PIC, ETH PHY, PCI, DVI monitor sense and DSP) interrupts multiplexed by the FPGA interrupt handler + * * Once we arrive here, the SR has been set to disable interrupts and the gcc scratch registers have been saved */ int irq5_handler(void *arg1, void *arg2) { - int32_t handle; - int32_t value = 0; - int32_t newvalue; + uint32_t pending_interrupts = FBEE_INTR_PENDING; - dbg("FPGA_INTR_CONTROL = 0x%08x\r\n", * FPGA_INTR_CONTROL); - dbg("FPGA_INTR_ENABLE = 0x%08x\r\n", * FPGA_INTR_ENABLE); - dbg("FPGA_INTR_CLEAR = 0x%08x\r\n", * FPGA_INTR_CLEAR); - dbg("FPGA_INTR_PENDING = 0x%08x\r\n", * FPGA_INTR_PENDING); + if (pending_interrupts & FBEE_INTR_PIC) + { + dbg("PIC interrupt\r\n"); + FBEE_INTR_CLEAR = FBEE_INTR_PIC; + } + + if (pending_interrupts & FBEE_INTR_ETHERNET) + { + dbg("ethernet 0 PHY interrupt\r\n"); + FBEE_INTR_CLEAR = FBEE_INTR_ETHERNET; + } + + if (pending_interrupts & FBEE_INTR_DVI) + { + dbg("DVI monitor sense interrupt\r\n"); + FBEE_INTR_CLEAR = FBEE_INTR_DVI; + } + + if (pending_interrupts & FBEE_INTR_PCI_INTA || + pending_interrupts & FBEE_INTR_PCI_INTB || + pending_interrupts & FBEE_INTR_PCI_INTC || + pending_interrupts & FBEE_INTR_PCI_INTD) + { + dbg("PCI interrupt\r\n"); + FBEE_INTR_CLEAR = FBEE_INTR_PCI_INTA | + FBEE_INTR_PCI_INTB | + FBEE_INTR_PCI_INTC | + FBEE_INTR_PCI_INTD; + } + + if (pending_interrupts & FBEE_INTR_DSP) + { + dbg("DSP interrupt\r\n"); + FBEE_INTR_CLEAR = FBEE_INTR_DSP; + } + + if (pending_interrupts & FBEE_INTR_VSYNC || pending_interrupts & FBEE_INTR_HSYNC) + { + /* hsync and vsync should go to TOS unhandled */ + return 1; + } - * FPGA_INTR_CLEAR &= ~0x20000000UL; /* clear interrupt from FPGA */ - dbg("\r\nFPGA_INTR_CLEAR = 0x%08x\r\n", * FPGA_INTR_CLEAR); MCF_EPORT_EPFR |= (1 << 5); /* clear interrupt from edge port */ - //xprintf("IRQ5!\r\n"); - -#ifdef _NOT_USED_ - if ((handle = pci_get_interrupt_cause()) > 0) - { - newvalue = pci_call_interrupt_chain(handle, value); - if (newvalue == value) - { - dbg("interrupt not handled!\r\n"); - - return 1; - } - } -#endif - - return 0; -} - -int irq6_handler(void *arg1, void *arg2) -{ - err("IRQ6!\r\n"); - - return 0; -} -#else -int irq5_handler(void *arg1, void *arg2) -{ return 0; } @@ -314,9 +323,20 @@ bool irq6_handler(uint32_t sf1, uint32_t sf2) return handled; } -#endif /* MACHINE_FIREBEE */ +#else /* MACHINE_FIREBEE */ + +int irq5_handler(void *arg1, void *arg2) +{ + return 0; +} + +bool irq6_handler(void *arg1, void *arg2) +{ + err("IRQ6!\r\n"); + + return 0; +} -#ifdef MACHINE_M5484LITE /* * This gets called from irq7 in exceptions.S * Once we arrive here, the SR has been set to disable interrupts and the gcc scratch registers have been saved @@ -341,18 +361,6 @@ void irq7_handler(void) #endif /* MACHINE_M548X */ #if defined(MACHINE_FIREBEE) -/* - * Firebee/Falcon Videl registers - * TODO: should go into an include file - */ -#define vbasehi (* (volatile uint8_t *) 0xffff8201) -#define vbasemid (* (volatile uint8_t *) 0xffff8203) -#define vbaselow (* (volatile uint8_t *) 0xffff820d) - -#define vwrap (* (volatile uint16_t *) 0xffff8210) -#define vde (* (volatile uint16_t *) 0xffff82aa) -#define vdb (* (volatile uint16_t *) 0xffff82a8) - /* * this is the higlevel interrupt service routine for gpt0 timer interrupts. * @@ -369,8 +377,6 @@ void irq7_handler(void) */ void gpt0_interrupt_handler(void) { - dbg("screen base = 0x%x\r\n", vbasehi); - MCF_GPT0_GMS &= ~1; /* rearm trigger */ NOP(); MCF_GPT0_GMS |= 1;