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PCI memory access working

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This commit is contained in:
Markus Fröschle
2016-10-15 21:26:49 +00:00
parent 369cc9dc0a
commit 42729fa2ea
68 changed files with 14798 additions and 2460 deletions
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6
.gdbinit
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@@ -1,14 +1,14 @@
#set disassemble-next-line on
define tr
#!killall m68k-bdm-gdbserver
target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
#target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
#target remote localhost:1234
#target remote | m68k-bdm-gdbserver pipe /dev/tblcf1
target remote | m68k-bdm-gdbserver pipe /dev/tblcf2
#target dbug /dev/ttyS0
#monitor bdm-reset
end
define tbtr
target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
target remote | m68k-bdm-gdbserver pipe /dev/tblcf2
end
source mcf5474.gdb
set breakpoint auto-hw

3
BaS_gcc.config
View File

@@ -1,2 +1,3 @@
// ADD PREDEFINED MACROS HERE!
#define MACHINE_FIREBEE
//#define MACHINE_FIREBEE
#define MACHINE_M5484LITE

166
BaS_gcc.files
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@@ -452,7 +452,6 @@ tos/jtagwait/jtagwait.files
tos/jtagwait/jtagwait.includes
tos/jtagwait/Makefile
tos/jtagwait/mapfile
tos/pci_test/include/bas_printf.h
tos/pci_test/include/bas_string.h
tos/pci_test/include/driver_vec.h
tos/pci_test/include/MCF5475.h
@@ -481,8 +480,6 @@ tos/pci_test/include/MCF5475_USB.h
tos/pci_test/include/MCF5475_XLB.h
tos/pci_test/m5475/mshort/pci_test.prg
tos/pci_test/m5475/pci_test.prg
tos/pci_test/sources/bas_printf.c
tos/pci_test/sources/bas_string.c
tos/pci_test/sources/pci_test.c
tos/pci_test/sources/printf_helper.S
tos/pci_test/depend
@@ -733,3 +730,166 @@ tos/vmem_test/Makefile
tos/Makefile
tos/fpga_test/sources/fpga_test.c
include/debug.h
tos/bascook/sources/bascook.c
tos/bascook/Makefile
tos/fpga_test/include/bas_printf.h
tos/fpga_test/include/bas_string.h
tos/fpga_test/include/driver_vec.h
tos/fpga_test/include/MCF5475.h
tos/fpga_test/include/MCF5475_CLOCK.h
tos/fpga_test/include/MCF5475_CTM.h
tos/fpga_test/include/MCF5475_DMA.h
tos/fpga_test/include/MCF5475_DSPI.h
tos/fpga_test/include/MCF5475_EPORT.h
tos/fpga_test/include/MCF5475_FBCS.h
tos/fpga_test/include/MCF5475_FEC.h
tos/fpga_test/include/MCF5475_GPIO.h
tos/fpga_test/include/MCF5475_GPT.h
tos/fpga_test/include/MCF5475_I2C.h
tos/fpga_test/include/MCF5475_INTC.h
tos/fpga_test/include/MCF5475_MMU.h
tos/fpga_test/include/MCF5475_PAD.h
tos/fpga_test/include/MCF5475_PCI.h
tos/fpga_test/include/MCF5475_PCIARB.h
tos/fpga_test/include/MCF5475_PSC.h
tos/fpga_test/include/MCF5475_SDRAMC.h
tos/fpga_test/include/MCF5475_SEC.h
tos/fpga_test/include/MCF5475_SIU.h
tos/fpga_test/include/MCF5475_SLT.h
tos/fpga_test/include/MCF5475_SRAM.h
tos/fpga_test/include/MCF5475_USB.h
tos/fpga_test/include/MCF5475_XLB.h
tos/fpga_test/sources/bas_printf.c
tos/fpga_test/sources/bas_string.c
tos/fpga_test/sources/fpga_test.c
tos/fpga_test/sources/printf_helper.S
tos/fpga_test/sources/vmem_test.c
tos/fpga_test/Makefile
tos/jtagwait/include/bas_printf.h
tos/jtagwait/include/bas_string.h
tos/jtagwait/include/driver_vec.h
tos/jtagwait/include/MCF5475.h
tos/jtagwait/include/MCF5475_CLOCK.h
tos/jtagwait/include/MCF5475_CTM.h
tos/jtagwait/include/MCF5475_DMA.h
tos/jtagwait/include/MCF5475_DSPI.h
tos/jtagwait/include/MCF5475_EPORT.h
tos/jtagwait/include/MCF5475_FBCS.h
tos/jtagwait/include/MCF5475_FEC.h
tos/jtagwait/include/MCF5475_GPIO.h
tos/jtagwait/include/MCF5475_GPT.h
tos/jtagwait/include/MCF5475_I2C.h
tos/jtagwait/include/MCF5475_INTC.h
tos/jtagwait/include/MCF5475_MMU.h
tos/jtagwait/include/MCF5475_PAD.h
tos/jtagwait/include/MCF5475_PCI.h
tos/jtagwait/include/MCF5475_PCIARB.h
tos/jtagwait/include/MCF5475_PSC.h
tos/jtagwait/include/MCF5475_SDRAMC.h
tos/jtagwait/include/MCF5475_SEC.h
tos/jtagwait/include/MCF5475_SIU.h
tos/jtagwait/include/MCF5475_SLT.h
tos/jtagwait/include/MCF5475_SRAM.h
tos/jtagwait/include/MCF5475_USB.h
tos/jtagwait/include/MCF5475_XLB.h
tos/jtagwait/sources/bas_printf.c
tos/jtagwait/sources/bas_string.c
tos/jtagwait/sources/jtagwait.c
tos/jtagwait/sources/printf_helper.S
tos/jtagwait/Makefile
tos/pci_mem/include/bas_string.h
tos/pci_mem/include/bas_types.h
tos/pci_mem/include/driver_vec.h
tos/pci_mem/include/MCF5475.h
tos/pci_mem/include/MCF5475_CLOCK.h
tos/pci_mem/include/MCF5475_CTM.h
tos/pci_mem/include/MCF5475_DMA.h
tos/pci_mem/include/MCF5475_DSPI.h
tos/pci_mem/include/MCF5475_EPORT.h
tos/pci_mem/include/MCF5475_FBCS.h
tos/pci_mem/include/MCF5475_FEC.h
tos/pci_mem/include/MCF5475_GPIO.h
tos/pci_mem/include/MCF5475_GPT.h
tos/pci_mem/include/MCF5475_I2C.h
tos/pci_mem/include/MCF5475_INTC.h
tos/pci_mem/include/MCF5475_MMU.h
tos/pci_mem/include/MCF5475_PAD.h
tos/pci_mem/include/MCF5475_PCI.h
tos/pci_mem/include/MCF5475_PCIARB.h
tos/pci_mem/include/MCF5475_PSC.h
tos/pci_mem/include/MCF5475_SDRAMC.h
tos/pci_mem/include/MCF5475_SEC.h
tos/pci_mem/include/MCF5475_SIU.h
tos/pci_mem/include/MCF5475_SLT.h
tos/pci_mem/include/MCF5475_SRAM.h
tos/pci_mem/include/MCF5475_USB.h
tos/pci_mem/include/MCF5475_XLB.h
tos/pci_mem/include/pci.h
tos/pci_mem/include/util.h
tos/pci_mem/sources/pci_mem.c
tos/pci_mem/Makefile
tos/pci_test/include/bas_string.h
tos/pci_test/include/bas_types.h
tos/pci_test/include/driver_vec.h
tos/pci_test/include/MCF5475.h
tos/pci_test/include/MCF5475_CLOCK.h
tos/pci_test/include/MCF5475_CTM.h
tos/pci_test/include/MCF5475_DMA.h
tos/pci_test/include/MCF5475_DSPI.h
tos/pci_test/include/MCF5475_EPORT.h
tos/pci_test/include/MCF5475_FBCS.h
tos/pci_test/include/MCF5475_FEC.h
tos/pci_test/include/MCF5475_GPIO.h
tos/pci_test/include/MCF5475_GPT.h
tos/pci_test/include/MCF5475_I2C.h
tos/pci_test/include/MCF5475_INTC.h
tos/pci_test/include/MCF5475_MMU.h
tos/pci_test/include/MCF5475_PAD.h
tos/pci_test/include/MCF5475_PCI.h
tos/pci_test/include/MCF5475_PCIARB.h
tos/pci_test/include/MCF5475_PSC.h
tos/pci_test/include/MCF5475_SDRAMC.h
tos/pci_test/include/MCF5475_SEC.h
tos/pci_test/include/MCF5475_SIU.h
tos/pci_test/include/MCF5475_SLT.h
tos/pci_test/include/MCF5475_SRAM.h
tos/pci_test/include/MCF5475_USB.h
tos/pci_test/include/MCF5475_XLB.h
tos/pci_test/include/pci.h
tos/pci_test/include/util.h
tos/pci_test/sources/pci_test.c
tos/pci_test/sources/printf_helper.S
tos/pci_test/Makefile
tos/vmem_test/include/bas_printf.h
tos/vmem_test/include/bas_string.h
tos/vmem_test/include/driver_vec.h
tos/vmem_test/include/MCF5475.h
tos/vmem_test/include/MCF5475_CLOCK.h
tos/vmem_test/include/MCF5475_CTM.h
tos/vmem_test/include/MCF5475_DMA.h
tos/vmem_test/include/MCF5475_DSPI.h
tos/vmem_test/include/MCF5475_EPORT.h
tos/vmem_test/include/MCF5475_FBCS.h
tos/vmem_test/include/MCF5475_FEC.h
tos/vmem_test/include/MCF5475_GPIO.h
tos/vmem_test/include/MCF5475_GPT.h
tos/vmem_test/include/MCF5475_I2C.h
tos/vmem_test/include/MCF5475_INTC.h
tos/vmem_test/include/MCF5475_MMU.h
tos/vmem_test/include/MCF5475_PAD.h
tos/vmem_test/include/MCF5475_PCI.h
tos/vmem_test/include/MCF5475_PCIARB.h
tos/vmem_test/include/MCF5475_PSC.h
tos/vmem_test/include/MCF5475_SDRAMC.h
tos/vmem_test/include/MCF5475_SEC.h
tos/vmem_test/include/MCF5475_SIU.h
tos/vmem_test/include/MCF5475_SLT.h
tos/vmem_test/include/MCF5475_SRAM.h
tos/vmem_test/include/MCF5475_USB.h
tos/vmem_test/include/MCF5475_XLB.h
tos/vmem_test/sources/bas_printf.c
tos/vmem_test/sources/bas_string.c
tos/vmem_test/sources/printf_helper.S
tos/vmem_test/sources/vmem_test.c
tos/vmem_test/Makefile
tos/Makefile

3
BaS_gcc.includes
View File

@@ -47,3 +47,6 @@ tos/jtagwait
tos/fpga_test/include
tos/fpga_test
tos/fpga_test/sources
tos/pci_mem
tos/pci_mem/include
tos/pci_mem/sources

2
Makefile
View File

@@ -22,7 +22,7 @@ EXE=s19
FORMAT=srec
endif
CC=$(TCPREFIX)gcc
CC=$(TCPREFIX)gcc-4.6.4
LD=$(TCPREFIX)ld
CPP=$(TCPREFIX)cpp
OBJCOPY=$(TCPREFIX)objcopy

6
flash/s19reader.c
View File

@@ -103,13 +103,13 @@ static uint32_t hex_to_long(uint8_t hex[8])
static uint8_t checksum(uint8_t arr[])
{
int i;
uint8_t csum = SREC_COUNT(arr);
uint8_t cs = SREC_COUNT(arr);
for (i = 0; i < SREC_COUNT(arr) - 1; i++)
{
csum += arr[i + 2];
cs += arr[i + 2];
}
return ~csum;
return ~cs;
}
#ifdef _NOT_USED_

BIN
flash_scripts/m548xlite_dbug_ram.elf Normal file
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Binary file not shown.

5922
flash_scripts/m548xlite_dbug_ram.s19 Normal file
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File diff suppressed because it is too large Load Diff

57
flash_scripts/run_m548x_dbug.bdm Executable file
View File

@@ -0,0 +1,57 @@
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
#
# firebee board initialization for bdmctrl
#
open $1
reset
sleep 1
wait
# Turn on MBAR at 0x1000_0000
write-ctrl 0x0C0F 0x10000000
dump-register MBAR
# Turn on RAMBAR0 at address 20000000
write-ctrl 0x0C04 0x20000021
# Turn on RAMBAR1 at address 20001000
write-ctrl 0x0C05 0x20001021
# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 8Mbytes)
write 0x10000500 0xE0000000 4
write 0x10000508 0x00041180 4
write 0x10000504 0x003F0001 4
wait
# SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 MBytes
write 0x10000004 0x000002AA 4 # SDRAMDS configuration
write 0x10000020 0x00000019 4 # SDRAM CS0 configuration (64Mbytes 0000_0000 - 03FF_FFFF)
write 0x10000024 0x00000000 4 # SDRAM CS1 configuration
write 0x10000028 0x00000000 4 # SDRAM CS2 configuration
write 0x1000002C 0x00000000 4 # SDRAM CS3 configuration
write 0x10000108 0x73711630 4 # SDCFG1
write 0x1000010C 0x46370000 4 # SDCFG2
write 0x10000104 0xE10B0002 4 # SDCR + IPALL
write 0x10000100 0x40010000 4 # SDMR (write to LEMR)
write 0x10000100 0x058D0000 4 # SDMR (write to LMR)
sleep 100
write 0x10000104 0xE10D0002 4 # SDCR + IPALL
write 0x10000104 0xE10D0004 4 # SDCR + IREF (first refresh)
write 0x10000104 0xE10D0004 4 # SDCR + IREF (first refresh)
write 0x10000100 0x018D0000 4 # SDMR (write to LMR)
write 0x10000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
sleep 100
load m548xlite_dbug_ram.elf .sec1 .sec2 .sec3
# set VBR
write-ctrl 0x0801 0x00000000
dump-register VBR
execute
wait

19
include/mmu.h
View File

@@ -30,8 +30,8 @@
/*
* ACR register handling macros
*/
#define ACR_BA(x) ((x) & 0xffff0000)
#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
#define ACR_BA(x) ((x) & 0xff000000)
#define ACR_ADMSK(x) (((x) & 0xff) << 16)
#define ACR_E(x) (((x) & 1) << 15)
#define ACR_S(x) (((x) & 3) << 13)
@@ -45,6 +45,17 @@
#define ACR_SUPERVISOR_PROTECT(x) (((x) & 1) << 3)
#define ACR_WRITE_PROTECT(x) (((x) & 1) << 2)
#define ACR_AMM(x) (((x) & 1) << 10)
#define ACR_CM(x) (((x) & 3) << 5)
#define ACR_CM_CACHEABLE_WT 0x0
#define ACR_CM_CACHEABLE_CB 0x1
#define ACR_CM_CACHE_INH_PRECISE 0x2
#define ACR_CM_CACHE_INH_IMPRECISE 0x3
#define ACR_SP(x) (((x) & 1) << 3)
#define ACR_W(x) (((x) & 1) << 2)
/*
* MMU register handling macros
@@ -98,7 +109,7 @@ enum mmu_page_size
extern long video_tlb;
extern long video_sbt;
struct mmu_page_descriptor
struct mmu_page_descriptor_ram
{
uint8_t cache_mode : 2;
uint8_t supervisor_protect : 1;
@@ -110,7 +121,7 @@ struct mmu_page_descriptor
};
extern void mmu_init(void);
extern uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags);
extern uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor_ram *flags);
/*
* API functions for the BaS driver interface

117
include/pci.h
View File

@@ -27,22 +27,27 @@
#define PCI_MEMORY_OFFSET 0x80000000
#define PCI_MEMORY_SIZE 0x40000000 /* 1 GByte PCI memory window */
#define PCI_IO_OFFSET 0xD0000000
#define PCI_IO_SIZE 0x10000000 /* 128 MByte PCI I/O window */
#define PCI_IO_SIZE 0x10000000 /* 256 MByte PCI I/O window */
#define PCI_LANESWAP_B(x) (x ^ 3)
#define PCI_LANESWAP_W(x) (x ^ 2)
#define PCI_LANESWAP_L(x) (x) /* for completeness only */
/*
* Note: the byte offsets are in little endian format, so you can't use them
* on byteswapped (Motorola format) values!
* Note: the byte offsets are in little endian format, so for pci_xxx_config_byte()
* accesses to hit the right offset, you'll need to wrap them into PCI_LANESWAP_B()
* and for pci_xxx_config_word() into PCI_LANESWAP_W()
*/
#define PCIIDR 0x00 /* PCI Configuration ID Register */
#define PCICSR 0x04 /* PCI Command/Status Register */
#define PCICR 0x04 /* PCI Command Register */
#define PCISR 0x06 /* PCI Status Register */
#define PCIREV 0x08 /* PCI Revision ID Register */
#define PCICCR 0x0B /* PCI Class Code Register */
#define PCICLSR 0x0C /* PCI Cache Line Size Register */
#define PCILTR 0x0D /* PCI Latency Timer Register */
#define PCIHTR 0x0E /* PCI Header Type Register */
#define PCIBISTR 0x0F /* PCI Build-In Self Test Register */
#define PCICR 0x06 /* PCI Command Register */
#define PCISR 0x04 /* PCI Status Register */
#define PCIREV 0x0B /* PCI Revision ID Register */
#define PCICCR 0x08 /* PCI Class Code Register */
#define PCICLSR 0x0F /* PCI Cache Line Size Register */
#define PCILTR 0x0E /* PCI Latency Timer Register */
#define PCIHTR 0x0D /* PCI Header Type Register */
#define PCIBISTR 0x0C /* PCI Build-In Self Test Register */
#define PCIBAR0 0x10 /* PCI Base Address Register for Memory
Accesses to Local, Runtime, and DMA */
#define PCIBAR1 0x14 /* PCI Base Address Register for I/O
@@ -55,13 +60,13 @@
#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */
#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/
#define PCISVID 0x2E /* PCI Subsystem Vendor ID */
#define PCISID 0x2E /* PCI Subsystem ID */
#define PCISID 0x2D /* PCI Subsystem ID */
#define PCIERBAR 0x30 /* PCI Expansion ROM Base Register */
#define CAP_PTR 0x34 /* New Capability Pointer */
#define PCIILR 0x3C /* PCI Interrupt Line Register */
#define PCIIPR 0x3D /* PCI Interrupt Pin Register */
#define PCIMGR 0x3E /* PCI Min_Gnt Register */
#define PCIMLR 0x3F /* PCI Max_Lat Register */
#define PCIILR 0x3F /* PCI Interrupt Line Register */
#define PCIIPR 0x3E /* PCI Interrupt Pin Register */
#define PCIMGR 0x3D /* PCI Min_Gnt Register */
#define PCIMLR 0x3C /* PCI Max_Lat Register */
#define PMCAPID 0x40 /* Power Management Capability ID */
#define PMNEXT 0x41 /* Power Management Next Capability
Pointer */
@@ -81,41 +86,41 @@
/*
* bit definitions for PCICSR lower half (Command Register)
*/
#define PCICSR_IO (1 << 0) /* if set: device responds to I/O space accesses */
#define PCICSR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */
#define PCICSR_MASTER (1 << 2) /* if set: device is master */
#define PCICSR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */
#define PCICSR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */
#define PCICSR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */
#define PCICSR_PERR (1 << 6) /* if set: reacts to parity errors */
#define PCICSR_STEPPING (1 << 7) /* if set: stepping enabled */
#define PCICSR_SERR (1 << 8) /* if set: SERR pin enabled */
#define PCICSR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
#define PCICSR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */
#define PCICR_IO (1 << 0) /* if set: device responds to I/O space accesses */
#define PCICR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */
#define PCICR_MASTER (1 << 2) /* if set: device is master */
#define PCICR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */
#define PCICR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */
#define PCICR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */
#define PCICR_PERR (1 << 6) /* if set: reacts to parity errors */
#define PCICR_STEPPING (1 << 7) /* if set: stepping enabled */
#define PCICR_SERR (1 << 8) /* if set: SERR pin enabled */
#define PCICR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
#define PCICR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */
/*
* bit definitions for PCICSR upper half (Status Register)
*/
#define PCICSR_INTERRUPT (1 << 3) /* device requested interrupt */
#define PCICSR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */
#define PCICSR_66MHZ (1 << 5) /* 66 MHz capable */
#define PCICSR_UDF (1 << 6) /* UDF supported */
#define PCICSR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
#define PCICSR_DPARITY_ERROR (1 << 8) /* data parity error detected */
#define PCISR_INTERRUPT (1 << 3) /* device requested interrupt */
#define PCISR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */
#define PCISR_66MHZ (1 << 5) /* 66 MHz capable */
#define PCISR_UDF (1 << 6) /* UDF supported */
#define PCISR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
#define PCISR_DPARITY_ERROR (1 << 8) /* data parity error detected */
#define PCICSR_T_ABORT_S (1 << 11) /* target abort signaled */
#define PCICSR_T_ABORT_R (1 << 12) /* target abort received */
#define PCICSR_M_ABORT_R (1 << 13) /* master abort received */
#define PCICSR_S_ERROR_S (1 << 14) /* system error signaled */
#define PCICSR_PARITY_ERR (1 << 15) /* data parity error */
#define PCISR_T_ABORT_S (1 << 11) /* target abort signaled */
#define PCISR_T_ABORT_R (1 << 12) /* target abort received */
#define PCISR_M_ABORT_R (1 << 13) /* master abort received */
#define PCISR_S_ERROR_S (1 << 14) /* system error signaled */
#define PCISR_PARITY_ERR (1 << 15) /* data parity error */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x1A /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x1B /* Latency timer for secondary interface */
#define PCI_PRIMARY_BUS 0x1B /* Primary bus number */
#define PCI_SECONDARY_BUS 0x1A /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x19 /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x18 /* Latency timer for secondary interface */
#define PCI_IO_BASE 0x1C /* I/O range behind the bridge */
#define PCI_IO_LIMIT 0x1D
#define PCI_SEC_STATUS 0x1E /* Secondary status register, only bit 14 used */
#define PCI_SEC_STATUS 0x1C /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
@@ -186,28 +191,28 @@ typedef struct /* structure of address conversion */
/* PCI configuration space macros */
/* register 0x00 macros */
#define PCI_VENDOR_ID(i) swpw((uint16_t)(((i) & 0xffff0000) >> 16))
#define PCI_DEVICE_ID(i) swpw((uint16_t) ((i) & 0xffff))
#define PCI_DEVICE_ID(i) (uint16_t)(((i) & 0xffff0000) >> 16)
#define PCI_VENDOR_ID(i) (uint16_t) ((i) & 0xffff)
/* register 0x04 macros */
#define PCI_STATUS(i) ((i) & 0xffff)
#define PCI_COMMAND(i) (((i) >> 16) & 0xffff)
/* register 0x08 macros */
#define PCI_CLASS_CODE(i) ((swpl((i)) & 0xff000000) >> 24)
#define PCI_SUBCLASS(i) ((swpl((i)) & 0x00ff0000) >> 16)
#define PCI_PROG_IF(i) ((swpl((i)) & 0x0000ff00) >> 8)
#define PCI_REVISION_ID(i) ((swpl((i)) & 0x000000ff))
#define PCI_CLASS_CODE(i) (((i) & 0xff000000) >> 24)
#define PCI_SUBCLASS(i) (((i) & 0x00ff0000) >> 16)
#define PCI_PROG_IF(i) (((i) & 0x0000ff00) >> 8)
#define PCI_REVISION_ID(i) (((i) & 0x000000ff))
/* register 0x0c macros */
#define PCI_BIST(i) ((swpl((i)) & 0xff000000) >> 24)
#define PCI_HEADER_TYPE(i) ((swpl((i)) & 0x00ff0000) >> 16)
#define PCI_LAT_TIMER(i) ((swpl((i)) & 0x0000ff00) >> 8)
#define PCI_CACHELINE_SIZE(i) ((swpl((i)) & 0x000000ff))
#define PCI_BIST(i) (((i) & 0xff000000) >> 24)
#define PCI_HEADER_TYPE(i) (((i) & 0x00ff0000) >> 16)
#define PCI_LAT_TIMER(i) (((i) & 0x0000ff00) >> 8)
#define PCI_CACHELINE_SIZE(i) (((i) & 0x000000ff))
/* register 0x2c macros */
#define PCI_SUBSYS_ID(i) (((i) & 0xffff0000) >> 16)
#define PCI_SUBSYS_VID(i) (((i) & 0xffff))
#define PCI_SUBSYS_ID(i) ((i) & 0xffff0000) >> 16)
#define PCI_SUBSYS_VID(i) ((i) & 0xffff))
/* register 0x34 macros */
#define PCI_CAPABILITIES(i) ((i) & 0xff)
@@ -350,4 +355,6 @@ extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3)
#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7))
extern void pci_dump_registers(int32_t handle);
#endif /* _PCI_H_ */

32
include/util.h
View File

@@ -35,18 +35,7 @@
*/
static inline uint16_t swpw(uint16_t w)
{
register uint32_t result asm("d0");
__asm__ __volatile__
(
"lea %[input],a0\n\t" \
"mvz.b 1(a0),%[output]\n\t" \
"lsl.l #8,%[output]\n\t" \
"move.b (a0),%[output]\n\t" \
: [output] "=d" (result) /* output */
: [input] "o" (w) /* input */
: "cc", "a0", "memory" /* clobbered */
);
return result;
return (w << 8) | (w >> 8);
}
/*
@@ -56,23 +45,8 @@ static inline uint16_t swpw(uint16_t w)
*/
static inline uint32_t swpl(uint32_t l)
{
register uint32_t result asm("d0");
__asm__ __volatile__
(
"lea %[input],a0\n\t" \
"mvz.b 3(a0),%[output]\n\t" \
"lsl.l #8,%[output]\n\t" \
"move.b 2(a0),%[output]\n\t" \
"lsl.l #8,%[output]\n\t" \
"move.b 1(a0),%[output]\n\t" \
"lsl.l #8,%[output]\n\t" \
"move.b (a0),%[output]\n\t" \
: [output] "=d" (result) /* output */
: [input] "o" (l) /* input */
: "cc", "a0", "memory" /* clobbered */
);
return result;
return ((l & 0xff000000) >> 24) | ((l & 0x00ff0000) >> 8) |
((l & 0x0000ff00) << 8) | (l << 24);
}

119
pci/pci.c
View File

@@ -34,6 +34,7 @@
#include "interrupts.h"
#include "wait.h"
#define DEBUG
#include "debug.h"
#define pci_config_wait() do { __asm__ __volatile("tpf" ::: "memory"); } while (0)
@@ -112,13 +113,13 @@ int32_t pci_get_interrupt_cause(void)
dbg("");
while ((handle = *hdl++) != -1)
{
uint16_t command_register = swpw(pci_read_config_word(handle, PCICR));
uint16_t status_register = swpw(pci_read_config_word(handle, PCISR));
uint16_t command_register = swpw(pci_read_config_word(handle, PCI_LANESWAP_W(PCICR)));
uint16_t status_register = swpw(pci_read_config_word(handle, PCI_LANESWAP_W(PCISR)));
/*
* ...to see which device caused the interrupt
*/
if ((status_register & PCICSR_INTERRUPT) && !(command_register & PCICSR_INT_DISABLE))
if ((status_register & PCISR_INTERRUPT) && !(command_register & PCICR_INT_DISABLE))
{
/* device has interrupts enabled and has an active interrupt, so its probably ours */
@@ -284,7 +285,7 @@ uint16_t pci_read_config_word(int32_t handle, int offset)
NOP();
value = * (volatile uint16_t *) PCI_IO_OFFSET + (offset & 2);
value = * (volatile uint16_t *) (PCI_IO_OFFSET + (offset & 2));
NOP();
@@ -329,17 +330,15 @@ int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value)
{
/* initiate PCI configuration access to device */
dbg("initiate configuration access\r\n");
MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */
MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) |
MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */
MCF_PCI_PCICAR_DWORD(offset / 4);
chip_errata_135();
NOP();
dbg("access device\r\n");
* (volatile uint32_t *) PCI_IO_OFFSET = value; /* access device */
dbg("chip errata\r\n");
@@ -347,7 +346,6 @@ int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value)
NOP();
dbg("finish config space access cycle\r\n");
/* finish configuration space access cycle */
MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
@@ -367,12 +365,14 @@ int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value)
MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |
MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |
MCF_PCI_PCICAR_DWORD(offset / 4);
chip_errata_135();
NOP();
* (volatile uint16_t *) (PCI_IO_OFFSET + (offset & 2)) = value;
chip_errata_135();
NOP();
/* finish configuration space access cycle */
MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
@@ -399,7 +399,8 @@ int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value)
* (volatile uint8_t *) (PCI_IO_OFFSET + (offset & 3)) = value;
chip_errata_135();
__asm__ __volatile__("tpf" ::: "memory");
NOP();
/* finish configuration space access cycle */
MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
@@ -456,7 +457,7 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
uint8_t htr;
handle = PCI_HANDLE(bus, device, 0);
value = pci_read_config_longword(handle, PCIIDR);
value = swpl(pci_read_config_longword(handle, PCIIDR));
if (value != 0xffffffff) /* we have a device at this position */
{
if (vendor_id == 0xffff ||
@@ -474,14 +475,14 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
* Check to see if it is a multi-function device. We need to look "behind" it
* for the other functions in that case.
*/
if ((htr = pci_read_config_byte(handle, PCIHTR)) & 0x80)
if ((htr = pci_read_config_byte(handle, PCI_LANESWAP_B(PCIHTR))) & 0x80)
{
/* yes, this is a multi-function device, look for more functions */
for (function = 1; function < 8; function++)
{
handle = PCI_HANDLE(bus, device, function);
value = pci_read_config_longword(handle, PCIIDR);
value = swpl(pci_read_config_longword(handle, PCIIDR));
if (value != 0xffffffff) /* device found */
{
if (vendor_id == 0xffff ||
@@ -528,11 +529,11 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
handle = PCI_HANDLE(bus, device, 0);
dbg("check handle %d\r\n", handle);
value = pci_read_config_longword(handle, PCIIDR);
value = swpl(pci_read_config_longword(handle, PCIIDR));
if (value != 0xffffffff) /* device found */
{
value = pci_read_config_longword(handle, PCICCR);
value = swpl(pci_read_config_longword(handle, PCICCR));
dbg("classcode to search for=%x\r\n", classcode);
dbg("PCI_CLASSCODE found=%02x\r\n", PCI_CLASS_CODE(value));
@@ -556,7 +557,7 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
* Check to see if it is a multi-function device. We need to look "behind" it
* for the other functions in that case.
*/
if ((htr = pci_read_config_byte(handle, PCIHTR)) & 0x80)
if ((htr = pci_read_config_byte(handle, PCI_LANESWAP_B(PCIHTR))) & 0x80)
{
/* yes, this is a multi-function device, look for more functions */
@@ -567,7 +568,7 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
if (value != 0xffffffff) /* device found */
{
value = pci_read_config_longword(handle, PCICCR);
value = swpl(pci_read_config_longword(handle, PCICCR));
if ((classcode & PCI_FIND_BASE_CLASS ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
(classcode & PCI_FIND_SUB_CLASS ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
@@ -831,9 +832,9 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
* disable device
*/
cr = swpw(pci_read_config_word(handle, PCICSR));
cr = swpw(pci_read_config_word(handle, PCI_LANESWAP_W(PCICR)));
cr &= ~3; /* disable device response to address */
pci_write_config_word(handle, PCICSR, swpw(cr));
pci_write_config_word(handle, PCI_LANESWAP_W(PCICR), swpw(cr));
int barnum = 0;
@@ -861,8 +862,8 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
if (IS_PCI_MEM_BAR(address))
{
/* adjust base address to card's alignment requirements */
int size = ~(address & 0xfffffff0) + 1;
dbg("device 0x%x: BAR[%d] requests %d bytes of memory\r\n", handle, i / 4, size);
long size = ~(address & 0xfffffff0) + 1;
dbg("device 0x%02x: BAR[%d] requests %ld kBytes of memory\r\n", handle, i / 4, size / 1024);
/* calculate a valid map adress with alignment requirements */
address = (mem_address + size - 1) & ~(size - 1);
@@ -923,7 +924,6 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
/*
* check if we have an expansion ROM
*/
value = swpl(pci_read_config_longword(handle, PCIERBAR));
/*
* write all bits of PCIERBAR
@@ -936,8 +936,15 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
address = swpl(pci_read_config_longword(handle, PCIERBAR));
if (address & 1)
{
/*
* there is a ROM
*/
struct pci_rd *rd = &descriptors[barnum];
int size = ~(address & ~0x7ff);
int size = ~(address & ~0x7ff) + 1;
dbg("expansion ROM requested size=0x%08x\r\n", size);
dbg("device 0x%02x: requests %ld kBytes for expansion ROM\r\n", handle, size / 1024);
/* expansion ROM active and mapped */
@@ -959,6 +966,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
rd->length = size;
rd->dmaoffset = 0;
cr |= 2; /* enable Memory */
mem_address += size;
barnum++;
}
@@ -968,19 +976,17 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
descriptors[barnum - 1].flags |= FLG_LAST;
/* check if device requests an interrupt */
il = pci_read_config_byte(handle, PCIIPR);
il = pci_read_config_byte(handle, PCI_LANESWAP_B(PCIIPR));
dbg("device requests interrupts on interrupt pin %d\r\n", il);
/* enable interrupt on PCI device */
il = pci_read_config_byte(handle, PCICR);
il &= ~PCICSR_INT_DISABLE;
pci_write_config_byte(handle, PCICR, il);
cr &= ~PCICR_INT_DISABLE;
/*
* enable device memory or I/O access
*/
pci_write_config_word(handle, PCICSR, swpw(cr));
pci_write_config_word(handle, PCI_LANESWAP_W(PCICR), swpw(cr));
}
static void pci_bridge_config(uint16_t bus, uint16_t device, uint16_t function)
@@ -995,9 +1001,18 @@ static void pci_bridge_config(uint16_t bus, uint16_t device, uint16_t function)
handle = PCI_HANDLE(bus, device, function);
dbg("handle=%d\r\n", handle);
pci_write_config_longword(handle, PCIBISTR, MCF_PCI_PCICR1_CACHELINESIZE(8) |
MCF_PCI_PCICR1_LATTIMER(0x20));
pci_write_config_longword(handle, PCIBAR0, swpl(0x40000000));
pci_write_config_longword(handle, PCIBAR1, 0x0);
pci_write_config_longword(handle, PCICSR, 0x146);
pci_write_config_word(handle, PCI_LANESWAP_W(PCICR), swpw(
(1 << 1) /* memory space */
| (1 << 2) /* bus master */
| (1 << 4) /* memory write and invalidate */
| (1 << 6) /* parity errors */
| (1 << 8) /* SERR */
| (1 << 9) /* fast back-to-back */
));
}
/*
@@ -1017,7 +1032,7 @@ void pci_scan(void)
{
uint32_t value;
value = pci_read_config_longword(handle, PCIIDR);
value = swpl(pci_read_config_longword(handle, PCIIDR));
xprintf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x, 0x%04x)\r\n",
PCI_BUS_FROM_HANDLE(handle),
@@ -1025,9 +1040,9 @@ void pci_scan(void)
PCI_FUNCTION_FROM_HANDLE(handle),
PCI_VENDOR_ID(value), PCI_DEVICE_ID(value),
handle,
device_class(pci_read_config_byte(handle, PCICCR)),
pci_read_config_byte(handle, PCICCR),
pci_read_config_word(handle, PCICCR));
device_class(pci_read_config_byte(handle, PCI_LANESWAP_B(PCICCR))),
pci_read_config_byte(handle, PCI_LANESWAP_B(PCICCR)),
pci_read_config_word(handle, PCI_LANESWAP_W(PCICCR)));
/* save handle to index value so that we'll be able to later find our resources */
handles[index] = handle;
@@ -1042,12 +1057,12 @@ void pci_scan(void)
}
else
{
dbg("");
dbg("\r\n");
pci_bridge_config(PCI_BUS_FROM_HANDLE(handle),
PCI_DEVICE_FROM_HANDLE(handle),
PCI_FUNCTION_FROM_HANDLE(handle));
}
dbg("");
dbg("\r\n");
handle = pci_find_device(0x0, 0xFFFF, ++index);
}
xprintf("\r\n...finished\r\n");
@@ -1125,13 +1140,14 @@ void init_pci(void)
init_eport();
init_xlbus_arbiter();
MCF_PCI_PCIGSCR = -1;
MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_PR; /* reset PCI devices */
/*
* setup the PCI arbiter
*/
MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI /* internal master priority: high */
| MCF_PCIARB_PACR_EXTMPRI(0xf) /* external master priority: high */
| MCF_PCIARB_PACR_EXTMPRI(0x0) /* external master priority: high */
| MCF_PCIARB_PACR_INTMINTEN /* enable "internal master broken" interrupt */
| MCF_PCIARB_PACR_EXTMINTEN(0x0f); /* enable "external master broken" interrupt */
@@ -1146,20 +1162,29 @@ void init_pci(void)
MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 |
MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 |
MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0;
#elif MACHINE_M5484LITE
MCF_PAD_PAR_PCIBG = 0x3ff; /* enable all PCI bus grant and bus requests on the LITE board */
MCF_PAD_PAR_PCIBR = 0x3ff;
#elif defined(MACHINE_M5484LITE)
MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 |
MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 |
MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 |
MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 |
MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4; /* enable all PCI bus grant and bus requests on the LITE board */
MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 |
MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 |
MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 |
MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 |
MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4;
#endif /* MACHINE_FIREBEE */
MCF_PCI_PCISCR = MCF_PCI_PCISCR_M | /* memory access control enabled */
MCF_PCI_PCISCR_B | /* bus master enabled */
MCF_PCI_PCISCR_M | /* mem access enable */
MCF_PCI_PCISCR_MA | /* clear master abort error */
MCF_PCI_PCISCR_MW; /* memory write and invalidate enabled */
MCF_PCI_PCISCR_MW | /* memory write and invalidate enabled */
MCF_PCI_PCISCR_PER; /* assert PERR on parity error */
/* Setup burst parameters */
MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(0) |
MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(8) |
MCF_PCI_PCICR1_LATTIMER(0x20); /* TODO: test increased latency timer */
MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(1) |
@@ -1174,8 +1199,8 @@ void init_pci(void)
// MCF_PCI_PCIICR = 0; /* this is what Linux does */
MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE; /* system error interrupt enable */
MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE | /* system error interrupt enable */
MCF_PCI_PCIGSCR_PEE; /* parity error interrupt enable */
/* Configure Initiator Windows */
/*
@@ -1183,7 +1208,7 @@ void init_pci(void)
* used for PCI memory access
*/
MCF_PCI_PCIIW0BTAR = ((PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8)) & 0xffff0000)
+ (PCI_MEMORY_OFFSET >> 16);
| (PCI_MEMORY_OFFSET >> 16);
NOP();
dbg("PCIIW0BTAR=0x%08x\r\n", MCF_PCI_PCIIW0BTAR);
@@ -1192,8 +1217,8 @@ void init_pci(void)
* initiator window 1 base / translation adress register
* used for PCI I/O access
*/
MCF_PCI_PCIIW1BTAR = ((PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000) +
+ (PCI_IO_OFFSET >> 16);
MCF_PCI_PCIIW1BTAR = ((PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000)
| (PCI_IO_OFFSET >> 16);
NOP();
/* initiator window 2 base / translation address register */
MCF_PCI_PCIIW2BTAR = 0L; /* not used */
@@ -1217,6 +1242,8 @@ void init_pci(void)
/* reset PCI devices */
MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
do { NOP(); } while (MCF_PCI_PCIGSCR & MCF_PCI_PCIGSCR_PR); /* wait until reset finished */
wait(200);
xprintf("finished\r\n");
/* initialize/clear resource descriptor table */

17
radeon/radeon_base.c
View File

@@ -62,13 +62,8 @@
#include "bas_string.h"
#include "exceptions.h" /* for set_ipl() */
#define DBG_RADEON
#ifdef DBG_RADEON
#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
#else
#define dbg(format, arg...) do {;} while (0)
#endif /* DBG_RADEON */
#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0)
// #define DEBUG
#include "debug.h"
extern void run_bios(struct radeonfb_info *rinfo);
@@ -241,8 +236,9 @@ extern struct fb_info *info_fb;
#define rinfo ((struct radeonfb_info *) info_fb->par)
static uint32_t inreg(uint32_t addr)
{
return swpl(*(uint32_t *)(rinfo->mmio_base + addr));
//return INREG(addr);
dbg("info_fb = %p, info_fb->par = %p\r\n", info_fb, info_fb->par);
dbg("retrieve from addr %p\r\n", rinfo->mmio_base + addr);
return INREG(addr);
}
static void outreg(uint32_t addr, uint32_t val)
@@ -367,7 +363,9 @@ static int radeon_map_ROM(struct radeonfb_info *rinfo)
dbg("bios_seg=%p\r\n", rinfo->bios_seg);
dbg("bios_seg_phys=%p\r\n", rinfo->bios_seg_phys);
dbg("before inreg\r\n");
temp = inreg(MPP_TB_CONFIG);
dbg("after inreg\r\n");
dbg("temp=%d\r\n", temp);
temp &= 0x00ffffffu;
@@ -2218,6 +2216,7 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
hexdump((uint8_t *) rinfo->bios_seg_phys, 0x100);
#endif
rinfo->bios_seg_phys = 0;
return 0;
}
}
}

7
sys/BaS.c
View File

@@ -295,9 +295,10 @@ NIF nif2;
bool spurious_interrupt_handler(void *arg1, void *arg2)
{
dbg("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL);
dbg("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL);
dbg("IRLR=%x\r\n", MCF_INTC_IRLR);
err("spurious interrupt\r\n");
err("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL);
err("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL);
err("IRLR=%x\r\n", MCF_INTC_IRLR);
return true;
}

146
sys/interrupts.c
View File

@@ -37,14 +37,8 @@
#include "dma.h"
#include "pci.h"
// #define IRQ_DEBUG
#if defined(IRQ_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
#define err(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
// #define DEBUG
#include "debug.h"
#ifndef MAX_ISR_ENTRY
#define MAX_ISR_ENTRY (20)
@@ -206,6 +200,140 @@ void isr_remove_handler(bool (*handler)(void *, void *))
dbg("no such handler registered (handler=%p\r\n", handler);
}
#ifdef DEBUG
static char *vector_to_str[] =
{
"initial stack pointer", /* 0 */
"initial program counter", /* 1 */
"access error", /* 2 */
"address error", /* 3 */
"illegal instruction", /* 4 */
"divide by zero", /* 5 */
"reserved6", /* 6 */
"reserved7", /* 7 */
"privilege violation", /* 8 */
"trace", /* 9 */
"unimplemented line-a opcode", /* 10 */
"unimplemented line-f opcode", /* 11 */
"non-PC breakpoint debug interrupt", /* 12 */
"PC breakpoint debug interrupt", /* 13 */
"format error", /* 14 */
"uninitialized interrupt", /* 15 */
"reserved16",
"reserved17",
"reserved18",
"reserved19",
"reserved20",
"reserved21",
"reserved22",
"reserved23",
"spurious interrupt", /* 24 */
"level 1 autovector", /* 25 */
"level 2 autovector", /* 26 */
"level 3 autovector", /* 27 */
"level 4 autovector", /* 28 */
"level 5 autovector", /* 29 */
"level 6 autovector", /* 30 */
"level 7 autovector", /* 31 */
"trap #0", /* 32 */
"trap #1", /* 33 */
"trap #2", /* 34 */
"trap #3", /* 35 */
"trap #4", /* 36 */
"trap #5", /* 37 */
"trap #6", /* 38 */
"trap #7", /* 39 */
"trap #8", /* 40 */
"trap #9", /* 41 */
"trap #10" /* 42 */
"trap #11", /* 43 */
"trap #12", /* 44 */
"trap #13", /* 45 */
"trap #14", /* 46 */
"trap #15", /* 47 */
"floating point branch on unordered condition", /* 48 */
"floting point inexact result", /* 49 */
"floating point divide by zero", /* 50 */
"floating point underflow", /* 51 */
"floating point operand error", /* 52 */
"floating point overflow", /* 53 */
"floating point NaN", /* 54 */
"floating point denormalized number", /* 55 */
"reserved56", /* 56 */
"reserved57",
"reserved58",
"reserved59",
"reserved60",
"unsupported instruction", /* 61 */
"reserved62", /* 62 */
"reserved63", /* 63 */
"", "",
"edge port 1", /* 1 */
"edge port 2", /* 2 */
"edge port 3", /* 3 */
"edge port 4", /* 4 */
"edge port 5", /* 5 */
"edge port 6", /* 6 */
"edge port 7", /* 7 */
"unused8",
"unused9",
"unused10",
"unused11",
"unused12",
"unused13",
"unused14",
"USB endpoint 0", /* 15 */
"USB endpoint 1", /* 16 */
"USB endpoint 2", /* 17 */
"USB endpoint 3", /* 18 */
"USB endpoint 4", /* 19 */
"USB endpoint 5", /* 20 */
"USB endpoint 6", /* 21 */
"USB general interrupt", /* 22 */
"USB core interrupt", /* 23 */
"USB OR interrupt", /* 24 */
"DSPI over/underflow", /* 25 */
"DSPI receive FIFO overflow", /* 26 */
"DSPI receive FIFO drain", /* 27 */
"DSPI transmit FIFO underflow", /* 28 */
"DSPI transfer complete", /* 29 */
"DSPI trasmit FIFO full", /* 30 */
"DSPI end of queue", /* 31 */
"PSC3", /* 32 */
"PSC2", /* 33 */
"PSC1", /* 34 */
"PSC0", /* 35 */
"Comm timer", /* 36 */
"SEC", /* 37 */
"FEC1", /* 38 */
"FEC0", /* 39 */
"I2C", /* 40 */
"PCI arbiter", /* 41 */
"comm bus PCI", /* 42 */
"XLB PCI", /* 43 */
"not used44",
"not used45",
"not used46",
"XLB arbiter to CPU", /* 47 */
"multichannel DMA", /* 48 */
"FlexCAN 0 error", /* 49 */
"FlexCAN 0 bus off", /* 50 */
"FlexCAN 0 message buffer", /* 51 */
"not used52"
"slice timer 1", /* 53 */
"slice timer 0", /* 54 */
"FlexCAN 1 error", /* 55 */
"FlexCAN 1 bus off", /* 56 */
"FlexCAN 1 message buffer", /* 57 */
"not used58",
"GPT3", /* 59 */
"GPT2", /* 60 */
"GPT1", /* 61 */
"GPT0", /* 62 */
"not used63"
};
#endif /* DEBUG */
/*
* This routine searches the ISR table for an entry that matches
* 'vector'. If one is found, then 'handler' is executed.
@@ -218,7 +346,7 @@ bool isr_execute_handler(int vector)
{
int index;
dbg("vector = %d\r\n", vector);
dbg("vector = %d (%s)\r\n", vector, vector_to_str[vector]);
/*
* locate an interrupt service routine handler.

53
sys/mmu.c
View File

@@ -36,26 +36,6 @@
* Copyright 2013 M. Froeschle
*/
#define ACR_BA(x) ((x) & 0xffff0000)
#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
#define ACR_E(x) (((x) & 1) << 15)
#define ACR_S(x) (((x) & 3) << 13)
#define ACR_S_USERMODE 0
#define ACR_S_SUPERVISOR_MODE 1
#define ACR_S_ALL 2
#define ACR_AMM(x) (((x) & 1) << 10)
#define ACR_CM(x) (((x) & 3) << 5)
#define ACR_CM_CACHEABLE_WT 0x0
#define ACR_CM_CACHEABLE_CB 0x1
#define ACR_CM_CACHE_INH_PRECISE 0x2
#define ACR_CM_CACHE_INH_IMPRECISE 0x3
#define ACR_SP(x) (((x) & 1) << 3)
#define ACR_W(x) (((x) & 1) << 2)
#include <stdint.h>
#include "bas_printf.h"
#include "bas_types.h"
@@ -230,6 +210,9 @@ static struct virt_to_phys translation[] =
{ 0x00000000, 0x00e00000, 0x00000000 }, /* map first 14 MByte to first 14 Mb of SD ram */
{ 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */
{ 0x01000000, 0x04000000, 0x00000000 }, /* map rest of ram virt = phys */
#if 0
{ 0x04000000, 0x08000000, 0x7C000000 }, /* experimental mapping for PCI memory */
#endif
};
#elif defined(MACHINE_M54455)
/* FIXME: this is not determined yet! */
@@ -269,14 +252,14 @@ static inline uint32_t lookup_phys(int32_t virt)
* bytes size) or 8k pages (64k descriptor array size)
*/
#define NUM_PAGES (SDRAM_SIZE / SIZE_DEFAULT)
static struct mmu_page_descriptor pages[NUM_PAGES];
static struct mmu_page_descriptor_ram pages[NUM_PAGES];
int mmu_map_instruction_page(uint32_t virt, uint8_t asid)
{
const uint32_t size_mask = ~ (SIZE_DEFAULT - 1); /* pagesize */
int page_index = (virt & size_mask) / SIZE_DEFAULT; /* index into page_descriptor array */
struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
struct mmu_page_descriptor_ram *page = &pages[page_index]; /* attributes of page to map */
int ipl;
uint32_t phys = lookup_phys(virt); /* virtual to physical translation of page */
@@ -332,7 +315,7 @@ int mmu_map_data_page(uint32_t virt, uint8_t asid)
uint16_t ipl;
const uint32_t size_mask = ~ (SIZE_DEFAULT - 1); /* pagesize */
int page_index = (virt & size_mask) / SIZE_DEFAULT; /* index into page_descriptor array */
struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
struct mmu_page_descriptor_ram *page = &pages[page_index]; /* attributes of page to map */
uint32_t phys = lookup_phys(virt); /* virtual to physical translation of page */
@@ -389,7 +372,7 @@ int mmu_map_data_page(uint32_t virt, uint8_t asid)
* per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
* LRU algorithm) should be used sparsingly.
*/
uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags)
uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor_ram *flags)
{
int size_mask;
int ipl;
@@ -456,7 +439,7 @@ void mmu_init(void)
{
extern uint8_t _MMUBAR[];
uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
struct mmu_page_descriptor flags;
struct mmu_page_descriptor_ram flags;
int i;
/*
@@ -613,18 +596,21 @@ void mmu_init(void)
/* set data access attributes in ACR0 and ACR1 */
/* map PCI address space */
/* set SRAM and MBAR access */
set_acr0(ACR_W(0) | /* read and write accesses permitted */
//ACR_SP(1) | /* supervisor only access permitted */
// ACR_SP(1) | /* supervisor only access permitted */
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
ACR_AMM(0) | /* control region > 16 MB */
ACR_S(ACR_S_SUPERVISOR_MODE) | /* match addresses in supervisor mode only */
ACR_S(ACR_S_SUPERVISOR_MODE) | /* match addresses in supervisor and user mode */
ACR_E(1) | /* enable ACR */
#if defined(MACHINE_FIREBEE)
ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */
ACR_BA(PCI_MEMORY_OFFSET)); /* (equals area from 3 to 4 GB */
// ACR_BA(PCI_MEMORY_OFFSET)); /* (equals area from 3 to 4 GB */
ACR_BA(0xe0000000));
#elif defined(MACHINE_M5484LITE)
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
ACR_BA(PCI_MEMORY_OFFSET));
// ACR_BA(PCI_MEMORY_OFFSET));
ACR_BA(0xe0000000));
#elif defined(MACHINE_M54455)
ACR_ADMSK(0x7f) |
ACR_BA(0x80000000)); /* FIXME: not determined yet */
@@ -709,6 +695,10 @@ void mmu_init(void)
flags.execute = 0;
flags.locked = 1;
mmu_map_page(0x6a000000, 0x6a000000, MMU_PAGE_SIZE_1M, 0, &flags);
#elif defined(MACHINE_M54455)
#warning MMU specs for M54455 not yet determined
#else
#error Unknown machine
#endif /* MACHINE_FIREBEE */
/*
@@ -881,7 +871,7 @@ uint32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
{
const uint32_t size_mask = ~ (SIZE_DEFAULT - 1); /* pagesize */
int page_index = (virt & size_mask) / SIZE_DEFAULT; /* index into page_descriptor array */
struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
struct mmu_page_descriptor_ram *page = &pages[page_index]; /* attributes of page to map */
int i = 0;
while (page_index * SIZE_DEFAULT < virt + size)
@@ -914,7 +904,7 @@ uint32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
int curr_asid;
const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);
int page_index = (address & size_mask) / SIZE_DEFAULT; /* index into page descriptor array */
struct mmu_page_descriptor *page = &pages[page_index];
struct mmu_page_descriptor_ram *page = &pages[page_index];
curr_asid = set_asid(asid); /* set asid to the one to search for */
@@ -1000,3 +990,4 @@ uint32_t mmu_report_pagesize(void)
{
return SIZE_DEFAULT;
}

15
sys/sysinit.c
View File

@@ -53,6 +53,9 @@
#include "usb.h"
#include "video.h"
#define DEBUG
#include "debug.h"
#define UNUSED(x) (void)(x) /* Unused variable */
bool fpga_configured = false; /* for FPGA JTAG configuration */
@@ -462,6 +465,9 @@ static void init_fbcs()
MCF_FBCS3_CSMR = 0;
MCF_FBCS4_CSMR = 0;
/*
* the FireEngine needs AA for its CPLD accessed registers
*/
MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000);
MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 | /* CPLD access 16 bit wide */
MCF_FBCS_CSCR_WS(32) | /* 32 wait states */
@@ -587,6 +593,7 @@ void init_usb(void)
do
{
handle = pci_find_classcode(PCI_CLASS_SERIAL_USB | PCI_FIND_BASE_CLASS | PCI_FIND_SUB_CLASS, index++);
dbg("handle 0x%02x\r\n", handle);
if (handle > 0)
{
long id;
@@ -597,10 +604,10 @@ void init_usb(void)
PCI_DEVICE_FROM_HANDLE(handle),
PCI_FUNCTION_FROM_HANDLE(handle),
handle);
id = pci_read_config_longword(handle, PCIIDR);
pci_class = pci_read_config_longword(handle, PCIREV);
id = swpl(pci_read_config_longword(handle, PCIIDR));
pci_class = swpl(pci_read_config_longword(handle, PCIREV));
if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_EHCI)
if (pci_class == PCI_CLASS_SERIAL_USB_EHCI)
{
board = ehci_usb_pci_table;
while (board->vendor)
@@ -615,7 +622,7 @@ void init_usb(void)
board++;
}
}
if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_OHCI)
if (pci_class == PCI_CLASS_SERIAL_USB_OHCI)
{
board = ohci_usb_pci_table;
while (board->vendor)

6
tos/Makefile
View File

@@ -3,8 +3,9 @@
.PHONY: bascook
.PHONY: vmem_test
.PHONY: pci_test
.PHONY: pci_mem
.PHONY: fpga_test
tos: jtagwait bascook vmem_test pci_test fpga_test
tos: jtagwait bascook vmem_test pci_test pci_mem fpga_test
jtagwait:
$(MAKE) -C $@
@@ -18,6 +19,9 @@ vmem_test:
pci_test:
$(MAKE) -C $@
pci_mem:
$(MAKE) -C $@
fpga_test:
$(MAKE) -C $@

105
tos/pci_mem/Makefile Executable file
View File

@@ -0,0 +1,105 @@
CROSS=Y
CROSSBINDIR_IS_Y=m68k-atari-mint-
CROSSBINDIR_IS_N=
CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
UNAME := $(shell uname)
ifeq ($(CROSS), Y)
ifeq ($(UNAME),Linux)
PREFIX=m68k-atari-mint
HATARI=hatari
else
PREFIX=m68k-atari-mint
HATARI=/usr/local/bin/hatari
endif
else
PREFIX=/usr
endif
DEPEND=depend
TOPDIR = ../..
LIBCMINI=$(TOPDIR)/../libcmini/libcmini
INCLUDE=-I$(LIBCMINI)/include -nostdlib
LIBS=-lcmini -nostdlib -lgcc
CC=$(PREFIX)/bin/gcc
CC=$(CROSSBINDIR)gcc
STRIP=$(CROSSBINDIR)strip
STACK=$(CROSSBINDIR)stack
APP=pci_mem.prg
TEST_APP=$(APP)
CFLAGS=\
-O0\
-g\
-Wl,-Map,mapfile\
-Wl,--defsym -Wl,__MBAR=0xff000000\
-Wl,--defsym -Wl,__MMUBAR=0xff040000\
-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
-Wl,--defsym -Wl,__VRAM=0x60000000\
-Wall
SRCDIR=sources
INCDIR=include
INCLUDE+=-I$(INCDIR)
CSRCS=\
$(SRCDIR)/pci_mem.c
ASRCS=
COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
OBJS=$(COBJS) $(AOBJS)
TRGTDIRS=./m5475 ./m5475/mshort
OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
#
# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
#
m5475/$(APP):CFLAGS += -mcpu=5475
m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
all:$(patsubst %,%/$(APP),$(TRGTDIRS))
#
# generate pattern rules for multilib object files.
#
define CC_TEMPLATE
$(1)/objs/%.o:$(SRCDIR)/%.c
$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
$(1)/objs/%.o:$(SRCDIR)/%.S
$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
$(1)/$(APP): $$($(1)_OBJS)
$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS)
$(STRIP) $$@
endef
$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
$(DEPEND): $(ASRCS) $(CSRCS)
-rm -f $(DEPEND)
for d in $(TRGTDIRS);\
do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
done
clean:
@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
@rm -f $(DEPEND) mapfile
.PHONY: printvars
printvars:
@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
ifneq (clean,$(MAKECMDGOALS))
-include $(DEPEND)
endif

67
tos/pci_mem/include/MCF5475.h Normal file
View File

@@ -0,0 +1,67 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_H__
#define __MCF5475_H__
#include <stdint.h>
/***
* MCF5475 Derivative Memory map definitions from linker command files:
* __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
* linker symbols must be defined in the linker command file.
*/
typedef uint32_t __attribute__((__may_alias__)) uint32_t_a; /* a type to avoid gcc's complaints about pointer aliasing */
extern uint8_t _MBAR[];
extern uint8_t _MMUBAR[];
extern uint8_t _RAMBAR0[];
extern uint8_t _RAMBAR0_SIZE[];
extern uint8_t _RAMBAR1[];
extern uint8_t _RAMBAR1_SIZE[];
#define MBAR_ADDRESS (uint32_t)_MBAR
#define MMUBAR_ADDRESS (uint32_t)_MMUBAR
#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE
#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE
#include "MCF5475_SIU.h"
#include "MCF5475_MMU.h"
#include "MCF5475_SDRAMC.h"
#include "MCF5475_XLB.h"
#include "MCF5475_CLOCK.h"
#include "MCF5475_FBCS.h"
#include "MCF5475_INTC.h"
#include "MCF5475_GPT.h"
#include "MCF5475_SLT.h"
#include "MCF5475_GPIO.h"
#include "MCF5475_PAD.h"
#include "MCF5475_PCI.h"
#include "MCF5475_PCIARB.h"
#include "MCF5475_EPORT.h"
#include "MCF5475_CTM.h"
#include "MCF5475_DMA.h"
#include "MCF5475_PSC.h"
#include "MCF5475_DSPI.h"
#include "MCF5475_I2C.h"
#include "MCF5475_FEC.h"
#include "MCF5475_USB.h"
#include "MCF5475_SRAM.h"
#include "MCF5475_SEC.h"
#endif /* __MCF5475_H__ */

47
tos/pci_mem/include/MCF5475_CLOCK.h Normal file
View File

@@ -0,0 +1,47 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_CLOCK_H__
#define __MCF5475_CLOCK_H__
/*********************************************************************
*
* Clock Module (CLOCK)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300]))
/* Bit definitions and macros for MCF_CLOCK_SPCR */
#define MCF_CLOCK_SPCR_MEMEN (0x1)
#define MCF_CLOCK_SPCR_PCIEN (0x2)
#define MCF_CLOCK_SPCR_FBEN (0x4)
#define MCF_CLOCK_SPCR_CAN0EN (0x8)
#define MCF_CLOCK_SPCR_DMAEN (0x10)
#define MCF_CLOCK_SPCR_FEC0EN (0x20)
#define MCF_CLOCK_SPCR_FEC1EN (0x40)
#define MCF_CLOCK_SPCR_USBEN (0x80)
#define MCF_CLOCK_SPCR_PSCEN (0x200)
#define MCF_CLOCK_SPCR_CAN1EN (0x800)
#define MCF_CLOCK_SPCR_CRYENA (0x1000)
#define MCF_CLOCK_SPCR_CRYENB (0x2000)
#define MCF_CLOCK_SPCR_COREN (0x4000)
#define MCF_CLOCK_SPCR_PLLK (0x80000000)
#endif /* __MCF5475_CLOCK_H__ */

76
tos/pci_mem/include/MCF5475_CTM.h Normal file
View File

@@ -0,0 +1,76 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_CTM_H__
#define __MCF5475_CTM_H__
/*********************************************************************
*
* Comm Timer Module (CTM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00]))
#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04]))
#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08]))
#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10]))
#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14]))
#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18]))
#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
/* Bit definitions and macros for MCF_CTM_CTCRF */
#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0)
#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10)
#define MCF_CTM_CTCRF_S_CLK_1 (0)
#define MCF_CTM_CTCRF_S_CLK_2 (0x10000)
#define MCF_CTM_CTCRF_S_CLK_4 (0x20000)
#define MCF_CTM_CTCRF_S_CLK_8 (0x30000)
#define MCF_CTM_CTCRF_S_CLK_16 (0x40000)
#define MCF_CTM_CTCRF_S_CLK_32 (0x50000)
#define MCF_CTM_CTCRF_S_CLK_64 (0x60000)
#define MCF_CTM_CTCRF_S_CLK_128 (0x70000)
#define MCF_CTM_CTCRF_S_CLK_256 (0x80000)
#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000)
#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14)
#define MCF_CTM_CTCRF_PCT_100 (0)
#define MCF_CTM_CTCRF_PCT_50 (0x100000)
#define MCF_CTM_CTCRF_PCT_25 (0x200000)
#define MCF_CTM_CTCRF_PCT_12p5 (0x300000)
#define MCF_CTM_CTCRF_PCT_6p25 (0x400000)
#define MCF_CTM_CTCRF_PCT_OFF (0x500000)
#define MCF_CTM_CTCRF_M (0x800000)
#define MCF_CTM_CTCRF_IM (0x1000000)
#define MCF_CTM_CTCRF_I (0x80000000)
/* Bit definitions and macros for MCF_CTM_CTCRV */
#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0)
#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18)
#define MCF_CTM_CTCRV_PCT_100 (0)
#define MCF_CTM_CTCRV_PCT_50 (0x1000000)
#define MCF_CTM_CTCRV_PCT_25 (0x2000000)
#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000)
#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000)
#define MCF_CTM_CTCRV_PCT_OFF (0x5000000)
#define MCF_CTM_CTCRV_M (0x8000000)
#define MCF_CTM_CTCRV_S (0x10000000)
#endif /* __MCF5475_CTM_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_DMA_H__
#define __MCF5475_DMA_H__
/*********************************************************************
*
* Multichannel DMA (DMA)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000]))
#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004]))
#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008]))
#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C]))
#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010]))
#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014]))
#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018]))
#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C]))
#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E]))
#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020]))
#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022]))
#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024]))
#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026]))
#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028]))
#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A]))
#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C]))
#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E]))
#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030]))
#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032]))
#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034]))
#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036]))
#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038]))
#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A]))
#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C]))
#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D]))
#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E]))
#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F]))
#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040]))
#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041]))
#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042]))
#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043]))
#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044]))
#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045]))
#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046]))
#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047]))
#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048]))
#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049]))
#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A]))
#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B]))
#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C]))
#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D]))
#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E]))
#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F]))
#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050]))
#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051]))
#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052]))
#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053]))
#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054]))
#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055]))
#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056]))
#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057]))
#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058]))
#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059]))
#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A]))
#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B]))
#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C]))
#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060]))
#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064]))
#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070]))
#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074]))
#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078]))
#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
/* Bit definitions and macros for MCF_DMA_TASKBAR */
#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_CP */
#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_EP */
#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_VP */
#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_PTD */
#define MCF_DMA_PTD_PCTL0 (0x1)
#define MCF_DMA_PTD_PCTL1 (0x2)
#define MCF_DMA_PTD_PCTL13 (0x2000)
#define MCF_DMA_PTD_PCTL14 (0x4000)
#define MCF_DMA_PTD_PCTL15 (0x8000)
/* Bit definitions and macros for MCF_DMA_DIPR */
#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DIMR */
#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_TCR */
#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0)
#define MCF_DMA_TCR_HLDINITNUM (0x20)
#define MCF_DMA_TCR_HIPRITSKEN (0x40)
#define MCF_DMA_TCR_ASTRT (0x80)
#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8)
#define MCF_DMA_TCR_ALWINIT (0x2000)
#define MCF_DMA_TCR_V (0x4000)
#define MCF_DMA_TCR_EN (0x8000)
/* Bit definitions and macros for MCF_DMA_PRIOR */
#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0)
#define MCF_DMA_PRIOR_HLD (0x80)
/* Bit definitions and macros for MCF_DMA_IMCR */
#define MCF_DMA_IMCR_IMC16(x) (((x)&0x3)<<0)
#define MCF_DMA_IMCR_IMC17(x) (((x)&0x3)<<0x2)
#define MCF_DMA_IMCR_IMC18(x) (((x)&0x3)<<0x4)
#define MCF_DMA_IMCR_IMC19(x) (((x)&0x3)<<0x6)
#define MCF_DMA_IMCR_IMC20(x) (((x)&0x3)<<0x8)
#define MCF_DMA_IMCR_IMC21(x) (((x)&0x3)<<0xA)
#define MCF_DMA_IMCR_IMC22(x) (((x)&0x3)<<0xC)
#define MCF_DMA_IMCR_IMC23(x) (((x)&0x3)<<0xE)
#define MCF_DMA_IMCR_IMC24(x) (((x)&0x3)<<0x10)
#define MCF_DMA_IMCR_IMC25(x) (((x)&0x3)<<0x12)
#define MCF_DMA_IMCR_IMC26(x) (((x)&0x3)<<0x14)
#define MCF_DMA_IMCR_IMC27(x) (((x)&0x3)<<0x16)
#define MCF_DMA_IMCR_IMC28(x) (((x)&0x3)<<0x18)
#define MCF_DMA_IMCR_IMC29(x) (((x)&0x3)<<0x1A)
#define MCF_DMA_IMCR_IMC30(x) (((x)&0x3)<<0x1C)
#define MCF_DMA_IMCR_IMC31(x) (((x)&0x3)<<0x1E)
#define MCF_DMA_IMCR_IMC16_FEC0RX (0x00000000)
#define MCF_DMA_IMCR_IMC17_FEC0TX (0x00000000)
#define MCF_DMA_IMCR_IMC18_FEC0RX (0x00000020)
#define MCF_DMA_IMCR_IMC19_FEC0TX (0x00000080)
#define MCF_DMA_IMCR_IMC20_FEC1RX (0x00000100)
#define MCF_DMA_IMCR_IMC21_DREQ1 (0x00000000)
#define MCF_DMA_IMCR_IMC21_FEC1TX (0x00000400)
#define MCF_DMA_IMCR_IMC22_FEC0RX (0x00001000)
#define MCF_DMA_IMCR_IMC23_FEC0TX (0x00004000)
#define MCF_DMA_IMCR_IMC24_CTM0 (0x00010000)
#define MCF_DMA_IMCR_IMC24_FEC1RX (0x00020000)
#define MCF_DMA_IMCR_IMC25_CTM1 (0x00040000)
#define MCF_DMA_IMCR_IMC25_FEC1TX (0x00080000)
#define MCF_DMA_IMCR_IMC26_USBEP4 (0x00000000)
#define MCF_DMA_IMCR_IMC26_CTM2 (0x00200000)
#define MCF_DMA_IMCR_IMC27_USBEP5 (0x00000000)
#define MCF_DMA_IMCR_IMC27_CTM3 (0x00800000)
#define MCF_DMA_IMCR_IMC28_USBEP6 (0x00000000)
#define MCF_DMA_IMCR_IMC28_CTM4 (0x01000000)
#define MCF_DMA_IMCR_IMC28_DREQ1 (0x02000000)
#define MCF_DMA_IMCR_IMC28_PSC2RX (0x03000000)
#define MCF_DMA_IMCR_IMC29_DREQ1 (0x04000000)
#define MCF_DMA_IMCR_IMC29_CTM5 (0x08000000)
#define MCF_DMA_IMCR_IMC29_PSC2TX (0x0C000000)
#define MCF_DMA_IMCR_IMC30_FEC1RX (0x00000000)
#define MCF_DMA_IMCR_IMC30_CTM6 (0x10000000)
#define MCF_DMA_IMCR_IMC30_PSC3RX (0x30000000)
#define MCF_DMA_IMCR_IMC31_FEC1TX (0x00000000)
#define MCF_DMA_IMCR_IMC31_CTM7 (0x80000000)
#define MCF_DMA_IMCR_IMC31_PSC3TX (0xC0000000)
/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0)
#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2)
#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4)
#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6)
#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8)
#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA)
#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC)
#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE)
#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10)
#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12)
#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14)
#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16)
#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18)
#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A)
#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C)
#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0)
#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2)
#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4)
#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6)
#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8)
#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA)
#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC)
#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE)
#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10)
#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12)
#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14)
#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16)
#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18)
#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A)
#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C)
#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DBGCTL */
#define MCF_DMA_DBGCTL_I (0x2)
#define MCF_DMA_DBGCTL_E (0x4)
#define MCF_DMA_DBGCTL_AND_OR (0x80)
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8)
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB)
#define MCF_DMA_DBGCTL_B (0x4000)
#define MCF_DMA_DBGCTL_AA (0x8000)
#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10)
#endif /* __MCF5475_DMA_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_DSPI_H__
#define __MCF5475_DSPI_H__
/*********************************************************************
*
* DMA Serial Peripheral Interface (DSPI)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00]))
#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08]))
#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10]))
#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14]))
#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18]))
#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20]))
#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24]))
#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28]))
#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30]))
#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34]))
#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38]))
#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40]))
#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44]))
#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48]))
#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80]))
#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84]))
#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88]))
#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
/* Bit definitions and macros for MCF_DSPI_DMCR */
#define MCF_DSPI_DMCR_HALT (0x1)
#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8)
#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0)
#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100)
#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200)
#define MCF_DSPI_DMCR_CRXF (0x400)
#define MCF_DSPI_DMCR_CTXF (0x800)
#define MCF_DSPI_DMCR_DRXF (0x1000)
#define MCF_DSPI_DMCR_DTXF (0x2000)
#define MCF_DSPI_DMCR_CSIS0 (0x10000)
#define MCF_DSPI_DMCR_CSIS2 (0x40000)
#define MCF_DSPI_DMCR_CSIS3 (0x80000)
#define MCF_DSPI_DMCR_CSIS5 (0x200000)
#define MCF_DSPI_DMCR_ROOE (0x1000000)
#define MCF_DSPI_DMCR_PCSSE (0x2000000)
#define MCF_DSPI_DMCR_MTFE (0x4000000)
#define MCF_DSPI_DMCR_FRZ (0x8000000)
#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C)
#define MCF_DSPI_DMCR_CSCK (0x40000000)
#define MCF_DSPI_DMCR_MSTR (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DTCR */
#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_DSPI_DCTAR */
#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0)
#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4)
#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8)
#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC)
#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10)
#define MCF_DSPI_DCTAR_PBR_1CLK (0)
#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000)
#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000)
#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000)
#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12)
#define MCF_DSPI_DCTAR_PDT_1CLK (0)
#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000)
#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000)
#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000)
#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14)
#define MCF_DSPI_DCTAR_PASC_1CLK (0)
#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000)
#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000)
#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000)
#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16)
#define MCF_DSPI_DCTAR_LSBFE (0x1000000)
#define MCF_DSPI_DCTAR_CPHA (0x2000000)
#define MCF_DSPI_DCTAR_CPOL (0x4000000)
#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B)
/* Bit definitions and macros for MCF_DSPI_DSR */
#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0)
#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4)
#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8)
#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC)
#define MCF_DSPI_DSR_RFDF (0x20000)
#define MCF_DSPI_DSR_RFOF (0x80000)
#define MCF_DSPI_DSR_TFFF (0x2000000)
#define MCF_DSPI_DSR_TFUF (0x8000000)
#define MCF_DSPI_DSR_EOQF (0x10000000)
#define MCF_DSPI_DSR_TXRXS (0x40000000)
#define MCF_DSPI_DSR_TCF (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DIRSR */
#define MCF_DSPI_DIRSR_RFDFS (0x10000)
#define MCF_DSPI_DIRSR_RFDFE (0x20000)
#define MCF_DSPI_DIRSR_RFOFE (0x80000)
#define MCF_DSPI_DIRSR_TFFFS (0x1000000)
#define MCF_DSPI_DIRSR_TFFFE (0x2000000)
#define MCF_DSPI_DIRSR_TFUFE (0x8000000)
#define MCF_DSPI_DIRSR_EOQFE (0x10000000)
#define MCF_DSPI_DIRSR_TCFE (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DTFR */
#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0)
#define MCF_DSPI_DTFR_CS0 (0x10000)
#define MCF_DSPI_DTFR_CS2 (0x40000)
#define MCF_DSPI_DTFR_CS3 (0x80000)
#define MCF_DSPI_DTFR_CS5 (0x200000)
#define MCF_DSPI_DTFR_CTCNT (0x4000000)
#define MCF_DSPI_DTFR_EOQ (0x8000000)
#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C)
#define MCF_DSPI_DTFR_CONT (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DRFR */
#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_DSPI_DTFDR */
#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0)
#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_DSPI_DRFDR */
#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0)
#endif /* __MCF5475_DSPI_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_EPORT_H__
#define __MCF5475_EPORT_H__
/*********************************************************************
*
* Edge Port Module (EPORT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00]))
#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04]))
#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05]))
#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08]))
#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09]))
#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C]))
/* Bit definitions and macros for MCF_EPORT_EPPAR */
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
#define MCF_EPORT_EPPAR_LEVEL (0)
#define MCF_EPORT_EPPAR_RISING (0x1)
#define MCF_EPORT_EPPAR_FALLING (0x2)
#define MCF_EPORT_EPPAR_BOTH (0x3)
/* Bit definitions and macros for MCF_EPORT_EPDDR */
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPIER */
#define MCF_EPORT_EPIER_EPIE1 (0x2)
#define MCF_EPORT_EPIER_EPIE2 (0x4)
#define MCF_EPORT_EPIER_EPIE3 (0x8)
#define MCF_EPORT_EPIER_EPIE4 (0x10)
#define MCF_EPORT_EPIER_EPIE5 (0x20)
#define MCF_EPORT_EPIER_EPIE6 (0x40)
#define MCF_EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPDR */
#define MCF_EPORT_EPDR_EPD1 (0x2)
#define MCF_EPORT_EPDR_EPD2 (0x4)
#define MCF_EPORT_EPDR_EPD3 (0x8)
#define MCF_EPORT_EPDR_EPD4 (0x10)
#define MCF_EPORT_EPDR_EPD5 (0x20)
#define MCF_EPORT_EPDR_EPD6 (0x40)
#define MCF_EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPPDR */
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPFR */
#define MCF_EPORT_EPFR_EPF1 (0x2)
#define MCF_EPORT_EPFR_EPF2 (0x4)
#define MCF_EPORT_EPFR_EPF3 (0x8)
#define MCF_EPORT_EPFR_EPF4 (0x10)
#define MCF_EPORT_EPFR_EPF5 (0x20)
#define MCF_EPORT_EPFR_EPF6 (0x40)
#define MCF_EPORT_EPFR_EPF7 (0x80)
#endif /* __MCF5475_EPORT_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_FBCS_H__
#define __MCF5475_FBCS_H__
/*********************************************************************
*
* FlexBus Chip Select Module (FBCS)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500]))
#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504]))
#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508]))
#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C]))
#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510]))
#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514]))
#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518]))
#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C]))
#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520]))
#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524]))
#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528]))
#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C]))
#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530]))
#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534]))
#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538]))
#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C]))
#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540]))
#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544]))
#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
/* Bit definitions and macros for MCF_FBCS_CSAR */
#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
/* Bit definitions and macros for MCF_FBCS_CSMR */
#define MCF_FBCS_CSMR_V (0x1)
#define MCF_FBCS_CSMR_WP (0x100)
#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)
#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000)
#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000)
#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000)
#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000)
#define MCF_FBCS_CSMR_BAM_16M (0xFF0000)
#define MCF_FBCS_CSMR_BAM_8M (0x7F0000)
#define MCF_FBCS_CSMR_BAM_4M (0x3F0000)
#define MCF_FBCS_CSMR_BAM_2M (0x1F0000)
#define MCF_FBCS_CSMR_BAM_1M (0xF0000)
#define MCF_FBCS_CSMR_BAM_1024K (0xF0000)
#define MCF_FBCS_CSMR_BAM_512K (0x70000)
#define MCF_FBCS_CSMR_BAM_256K (0x30000)
#define MCF_FBCS_CSMR_BAM_128K (0x10000)
#define MCF_FBCS_CSMR_BAM_64K (0)
/* Bit definitions and macros for MCF_FBCS_CSCR */
#define MCF_FBCS_CSCR_BSTW (0x8)
#define MCF_FBCS_CSCR_BSTR (0x10)
#define MCF_FBCS_CSCR_BEM (0x20)
#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6)
#define MCF_FBCS_CSCR_PS_32 (0)
#define MCF_FBCS_CSCR_PS_8 (0x40)
#define MCF_FBCS_CSCR_PS_16 (0x80)
#define MCF_FBCS_CSCR_AA (0x100)
#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA)
#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10)
#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12)
#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14)
#define MCF_FBCS_CSCR_SWSEN (0x800000)
#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A)
#endif /* __MCF5475_FBCS_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_FEC_H__
#define __MCF5475_FEC_H__
/*********************************************************************
*
* Fast Ethernet Controller(FEC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004]))
#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008]))
#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024]))
#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040]))
#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044]))
#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064]))
#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084]))
#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088]))
#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4]))
#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4]))
#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8]))
#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC]))
#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118]))
#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C]))
#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120]))
#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124]))
#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144]))
#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184]))
#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188]))
#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C]))
#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190]))
#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194]))
#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198]))
#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C]))
#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0]))
#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4]))
#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8]))
#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC]))
#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0]))
#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4]))
#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8]))
#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC]))
#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0]))
#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4]))
#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8]))
#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200]))
#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204]))
#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208]))
#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C]))
#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210]))
#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214]))
#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218]))
#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C]))
#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220]))
#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224]))
#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228]))
#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C]))
#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230]))
#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234]))
#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238]))
#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C]))
#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240]))
#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244]))
#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248]))
#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C]))
#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250]))
#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254]))
#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258]))
#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C]))
#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260]))
#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264]))
#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268]))
#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C]))
#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270]))
#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274]))
#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280]))
#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284]))
#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288]))
#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C]))
#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290]))
#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294]))
#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298]))
#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C]))
#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0]))
#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4]))
#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8]))
#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC]))
#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0]))
#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4]))
#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8]))
#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC]))
#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0]))
#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4]))
#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8]))
#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC]))
#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0]))
#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4]))
#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8]))
#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC]))
#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0]))
#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804]))
#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808]))
#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824]))
#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840]))
#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844]))
#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864]))
#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884]))
#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888]))
#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4]))
#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4]))
#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8]))
#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC]))
#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918]))
#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C]))
#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920]))
#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924]))
#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944]))
#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984]))
#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988]))
#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C]))
#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990]))
#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994]))
#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998]))
#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C]))
#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0]))
#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4]))
#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8]))
#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC]))
#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0]))
#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4]))
#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8]))
#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC]))
#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0]))
#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4]))
#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8]))
#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00]))
#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04]))
#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08]))
#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10]))
#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14]))
#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18]))
#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20]))
#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24]))
#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28]))
#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30]))
#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34]))
#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38]))
#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40]))
#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44]))
#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48]))
#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50]))
#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54]))
#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58]))
#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60]))
#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64]))
#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68]))
#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70]))
#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74]))
#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80]))
#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84]))
#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88]))
#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90]))
#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94]))
#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98]))
#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
/* Bit definitions and macros for MCF_FEC_EIR */
#define MCF_FEC_EIR_RFERR (0x20000)
#define MCF_FEC_EIR_XFERR (0x40000)
#define MCF_FEC_EIR_XFUN (0x80000)
#define MCF_FEC_EIR_RL (0x100000)
#define MCF_FEC_EIR_LC (0x200000)
#define MCF_FEC_EIR_MII (0x800000)
#define MCF_FEC_EIR_TXF (0x8000000)
#define MCF_FEC_EIR_GRA (0x10000000)
#define MCF_FEC_EIR_BABT (0x20000000)
#define MCF_FEC_EIR_BABR (0x40000000)
#define MCF_FEC_EIR_HBERR (0x80000000)
#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
/* Bit definitions and macros for MCF_FEC_EIMR */
#define MCF_FEC_EIMR_RFERR (0x20000)
#define MCF_FEC_EIMR_XFERR (0x40000)
#define MCF_FEC_EIMR_XFUN (0x80000)
#define MCF_FEC_EIMR_RL (0x100000)
#define MCF_FEC_EIMR_LC (0x200000)
#define MCF_FEC_EIMR_MII (0x800000)
#define MCF_FEC_EIMR_TXF (0x8000000)
#define MCF_FEC_EIMR_GRA (0x10000000)
#define MCF_FEC_EIMR_BABT (0x20000000)
#define MCF_FEC_EIMR_BABR (0x40000000)
#define MCF_FEC_EIMR_HBERR (0x80000000)
#define MCF_FEC_EIMR_MASK_ALL (0)
#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
/* Bit definitions and macros for MCF_FEC_ECR */
#define MCF_FEC_ECR_RESET (0x1)
#define MCF_FEC_ECR_ETHER_EN (0x2)
/* Bit definitions and macros for MCF_FEC_MMFR */
#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)
#define MCF_FEC_MMFR_TA_10 (0x20000)
#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)
#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)
#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)
#define MCF_FEC_MMFR_OP_READ (0x20000000)
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)
#define MCF_FEC_MMFR_ST_01 (0x40000000)
/* Bit definitions and macros for MCF_FEC_MSCR */
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)
#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1)
#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1)
#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1)
#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1)
/* Bit definitions and macros for MCF_FEC_MIBC */
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
/* Bit definitions and macros for MCF_FEC_RCR */
#define MCF_FEC_RCR_LOOP (0x1)
#define MCF_FEC_RCR_DRT (0x2)
#define MCF_FEC_RCR_MII_MODE (0x4)
#define MCF_FEC_RCR_PROM (0x8)
#define MCF_FEC_RCR_BC_REJ (0x10)
#define MCF_FEC_RCR_FCE (0x20)
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)
/* Bit definitions and macros for MCF_FEC_RHR */
#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18)
#define MCF_FEC_RHR_MULTCAST (0x40000000)
#define MCF_FEC_RHR_FCE (0x80000000)
/* Bit definitions and macros for MCF_FEC_TCR */
#define MCF_FEC_TCR_GTS (0x1)
#define MCF_FEC_TCR_HBC (0x2)
#define MCF_FEC_TCR_FDEN (0x4)
#define MCF_FEC_TCR_TFC_PAUSE (0x8)
#define MCF_FEC_TCR_RFC_PAUSE (0x10)
/* Bit definitions and macros for MCF_FEC_PALR */
#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_PAHR */
#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_FEC_OPD */
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_FEC_IAUR */
#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IALR */
#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_GAUR */
#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_GALR */
#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFWR */
#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0)
#define MCF_FEC_FECTFWR_X_WMRK_64 (0)
#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1)
#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2)
#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3)
#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4)
#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5)
#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6)
#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7)
#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8)
#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9)
#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA)
#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB)
#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC)
#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD)
#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE)
#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF)
/* Bit definitions and macros for MCF_FEC_FECRFDR */
#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFSR */
#define MCF_FEC_FECRFSR_EMT (0x10000)
#define MCF_FEC_FECRFSR_ALARM (0x20000)
#define MCF_FEC_FECRFSR_FU (0x40000)
#define MCF_FEC_FECRFSR_FRMRDY (0x80000)
#define MCF_FEC_FECRFSR_OF (0x100000)
#define MCF_FEC_FECRFSR_UF (0x200000)
#define MCF_FEC_FECRFSR_RXW (0x400000)
#define MCF_FEC_FECRFSR_FAE (0x800000)
#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18)
#define MCF_FEC_FECRFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_FEC_FECRFCR */
#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_FECRFCR_OF_MSK (0x80000)
#define MCF_FEC_FECRFCR_UF_MSK (0x100000)
#define MCF_FEC_FECRFCR_RXW_MSK (0x200000)
#define MCF_FEC_FECRFCR_FAE_MSK (0x400000)
#define MCF_FEC_FECRFCR_IP_MSK (0x800000)
#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_FEC_FECRFCR_FRMEN (0x8000000)
#define MCF_FEC_FECRFCR_TIMER (0x10000000)
/* Bit definitions and macros for MCF_FEC_FECRLRFP */
#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRLWFP */
#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFAR */
#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFRP */
#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFWP */
#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFDR */
#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFSR */
#define MCF_FEC_FECTFSR_EMT (0x10000)
#define MCF_FEC_FECTFSR_ALARM (0x20000)
#define MCF_FEC_FECTFSR_FU (0x40000)
#define MCF_FEC_FECTFSR_FRMRDY (0x80000)
#define MCF_FEC_FECTFSR_OF (0x100000)
#define MCF_FEC_FECTFSR_UF (0x200000)
#define MCF_FEC_FECTFSR_FAE (0x800000)
#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18)
#define MCF_FEC_FECTFSR_TXW (0x40000000)
#define MCF_FEC_FECTFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_FEC_FECTFCR */
#define MCF_FEC_FECTFCR_RESERVED (0x200000)
#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000)
#define MCF_FEC_FECTFCR_TXW_MASK (0x240000)
#define MCF_FEC_FECTFCR_OF_MSK (0x280000)
#define MCF_FEC_FECTFCR_UF_MSK (0x300000)
#define MCF_FEC_FECTFCR_FAE_MSK (0x600000)
#define MCF_FEC_FECTFCR_IP_MSK (0xA00000)
#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000)
#define MCF_FEC_FECTFCR_FRMEN (0x8200000)
#define MCF_FEC_FECTFCR_TIMER (0x10200000)
#define MCF_FEC_FECTFCR_WFR (0x20200000)
#define MCF_FEC_FECTFCR_WCTL (0x40200000)
/* Bit definitions and macros for MCF_FEC_FECTLRFP */
#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTLWFP */
#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFAR */
#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFRP */
#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFWP */
#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECFRST */
#define MCF_FEC_FECFRST_RST_CTL (0x1000000)
#define MCF_FEC_FECFRST_SW_RST (0x2000000)
/* Bit definitions and macros for MCF_FEC_FECCTCWR */
#define MCF_FEC_FECCTCWR_TFCW (0x1000000)
#define MCF_FEC_FECCTCWR_CRC (0x2000000)
/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
#endif /* __MCF5475_FEC_H__ */

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tos/pci_mem/include/MCF5475_GPIO.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_GPIO_H__
#define __MCF5475_GPIO_H__
/*********************************************************************
*
* General Purpose I/O (GPIO)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00]))
#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10]))
#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20]))
#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30]))
#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01]))
#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11]))
#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21]))
#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31]))
#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02]))
#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12]))
#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22]))
#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32]))
#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04]))
#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14]))
#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24]))
#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34]))
#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05]))
#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15]))
#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25]))
#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35]))
#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06]))
#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16]))
#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26]))
#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36]))
#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07]))
#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17]))
#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27]))
#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37]))
#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08]))
#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18]))
#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28]))
#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38]))
#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09]))
#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19]))
#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29]))
#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39]))
#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A]))
#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A]))
#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A]))
#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A]))
#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C]))
#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C]))
#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C]))
#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C]))
#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D]))
#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D]))
#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D]))
#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D]))
#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E]))
#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E]))
#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E]))
#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E]))
/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1)
#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2)
#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4)
#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40)
#endif /* __MCF5475_GPIO_H__ */

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tos/pci_mem/include/MCF5475_GPT.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_GPT_H__
#define __MCF5475_GPT_H__
/*********************************************************************
*
* General Purpose Timers (GPT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800]))
#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804]))
#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808]))
#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C]))
#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810]))
#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814]))
#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818]))
#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C]))
#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820]))
#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824]))
#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828]))
#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C]))
#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830]))
#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834]))
#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838]))
#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C]))
#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)]))
#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)]))
#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)]))
#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)]))
/* Bit definitions and macros for MCF_GPT_GMS */
#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0)
#define MCF_GPT_GMS_TMS_DISABLE (0)
#define MCF_GPT_GMS_TMS_INCAPT (0x1)
#define MCF_GPT_GMS_TMS_OUTCAPT (0x2)
#define MCF_GPT_GMS_TMS_PWM (0x3)
#define MCF_GPT_GMS_TMS_GPIO (0x4)
#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4)
#define MCF_GPT_GMS_GPIO_INPUT (0)
#define MCF_GPT_GMS_GPIO_OUTLO (0x20)
#define MCF_GPT_GMS_GPIO_OUTHI (0x30)
#define MCF_GPT_GMS_IEN (0x100)
#define MCF_GPT_GMS_OD (0x200)
#define MCF_GPT_GMS_SC (0x400)
#define MCF_GPT_GMS_CE (0x1000)
#define MCF_GPT_GMS_WDEN (0x8000)
#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10)
#define MCF_GPT_GMS_ICT_ANY (0)
#define MCF_GPT_GMS_ICT_RISE (0x10000)
#define MCF_GPT_GMS_ICT_FALL (0x20000)
#define MCF_GPT_GMS_ICT_PULSE (0x30000)
#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14)
#define MCF_GPT_GMS_OCT_FRCLOW (0)
#define MCF_GPT_GMS_OCT_PULSEHI (0x100000)
#define MCF_GPT_GMS_OCT_PULSELO (0x200000)
#define MCF_GPT_GMS_OCT_TOGGLE (0x300000)
#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_GPT_GCIR */
#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0)
#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_GPT_GPWM */
#define MCF_GPT_GPWM_LOAD (0x1)
#define MCF_GPT_GPWM_PWMOP (0x100)
#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_GPT_GSR */
#define MCF_GPT_GSR_CAPT (0x1)
#define MCF_GPT_GSR_COMP (0x2)
#define MCF_GPT_GSR_PWMP (0x4)
#define MCF_GPT_GSR_TEXP (0x8)
#define MCF_GPT_GSR_PIN (0x100)
#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC)
#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10)
#endif /* __MCF5475_GPT_H__ */

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tos/pci_mem/include/MCF5475_I2C.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_I2C_H__
#define __MCF5475_I2C_H__
/*********************************************************************
*
* I2C Module (I2C)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&_MBAR[0x8F00]))
#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&_MBAR[0x8F04]))
#define MCF_I2C_I2CR (*(volatile uint8_t *)(&_MBAR[0x8F08]))
#define MCF_I2C_I2SR (*(volatile uint8_t *)(&_MBAR[0x8F0C]))
#define MCF_I2C_I2DR (*(volatile uint8_t *)(&_MBAR[0x8F10]))
#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&_MBAR[0x8F20]))
/* Bit definitions and macros for MCF_I2C_I2ADR */
#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
/* Bit definitions and macros for MCF_I2C_I2FDR */
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_I2C_I2CR */
#define MCF_I2C_I2CR_RSTA (0x4)
#define MCF_I2C_I2CR_TXAK (0x8)
#define MCF_I2C_I2CR_MTX (0x10)
#define MCF_I2C_I2CR_MSTA (0x20)
#define MCF_I2C_I2CR_IIEN (0x40)
#define MCF_I2C_I2CR_IEN (0x80)
/* Bit definitions and macros for MCF_I2C_I2SR */
#define MCF_I2C_I2SR_RXAK (0x1)
#define MCF_I2C_I2SR_IIF (0x2)
#define MCF_I2C_I2SR_SRW (0x4)
#define MCF_I2C_I2SR_IAL (0x10)
#define MCF_I2C_I2SR_IBB (0x20)
#define MCF_I2C_I2SR_IAAS (0x40)
#define MCF_I2C_I2SR_ICF (0x80)
/* Bit definitions and macros for MCF_I2C_I2DR */
#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_I2C_I2ICR */
#define MCF_I2C_I2ICR_IE (0x1)
#define MCF_I2C_I2ICR_RE (0x2)
#define MCF_I2C_I2ICR_TE (0x4)
#define MCF_I2C_I2ICR_BNBE (0x8)
#endif /* __MCF5475_I2C_H__ */

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tos/pci_mem/include/MCF5475_INTC.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_INTC_H__
#define __MCF5475_INTC_H__
/*********************************************************************
*
* Interrupt Controller (INTC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700]))
#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704]))
#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708]))
#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C]))
#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710]))
#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714]))
#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718]))
#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719]))
#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741]))
#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742]))
#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743]))
#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744]))
#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745]))
#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746]))
#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747]))
#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748]))
#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749]))
#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A]))
#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B]))
#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C]))
#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D]))
#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E]))
#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F]))
#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750]))
#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751]))
#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752]))
#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753]))
#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754]))
#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755]))
#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756]))
#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757]))
#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758]))
#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759]))
#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A]))
#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B]))
#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C]))
#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D]))
#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E]))
#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F]))
#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760]))
#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761]))
#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762]))
#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763]))
#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764]))
#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765]))
#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766]))
#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767]))
#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768]))
#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769]))
#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A]))
#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B]))
#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C]))
#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D]))
#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E]))
#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F]))
#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770]))
#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771]))
#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772]))
#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773]))
#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774]))
#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775]))
#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776]))
#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777]))
#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778]))
#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779]))
#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A]))
#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B]))
#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C]))
#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D]))
#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E]))
#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F]))
#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0]))
#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4]))
#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8]))
#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC]))
#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0]))
#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4]))
#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8]))
#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC]))
#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)]))
#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
/* Bit definitions and macros for MCF_INTC_IPRH */
#define MCF_INTC_IPRH_INT32 (0x1)
#define MCF_INTC_IPRH_INT33 (0x2)
#define MCF_INTC_IPRH_INT34 (0x4)
#define MCF_INTC_IPRH_INT35 (0x8)
#define MCF_INTC_IPRH_INT36 (0x10)
#define MCF_INTC_IPRH_INT37 (0x20)
#define MCF_INTC_IPRH_INT38 (0x40)
#define MCF_INTC_IPRH_INT39 (0x80)
#define MCF_INTC_IPRH_INT40 (0x100)
#define MCF_INTC_IPRH_INT41 (0x200)
#define MCF_INTC_IPRH_INT42 (0x400)
#define MCF_INTC_IPRH_INT43 (0x800)
#define MCF_INTC_IPRH_INT44 (0x1000)
#define MCF_INTC_IPRH_INT45 (0x2000)
#define MCF_INTC_IPRH_INT46 (0x4000)
#define MCF_INTC_IPRH_INT47 (0x8000)
#define MCF_INTC_IPRH_INT48 (0x10000)
#define MCF_INTC_IPRH_INT49 (0x20000)
#define MCF_INTC_IPRH_INT50 (0x40000)
#define MCF_INTC_IPRH_INT51 (0x80000)
#define MCF_INTC_IPRH_INT52 (0x100000)
#define MCF_INTC_IPRH_INT53 (0x200000)
#define MCF_INTC_IPRH_INT54 (0x400000)
#define MCF_INTC_IPRH_INT55 (0x800000)
#define MCF_INTC_IPRH_INT56 (0x1000000)
#define MCF_INTC_IPRH_INT57 (0x2000000)
#define MCF_INTC_IPRH_INT58 (0x4000000)
#define MCF_INTC_IPRH_INT59 (0x8000000)
#define MCF_INTC_IPRH_INT60 (0x10000000)
#define MCF_INTC_IPRH_INT61 (0x20000000)
#define MCF_INTC_IPRH_INT62 (0x40000000)
#define MCF_INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IPRL */
#define MCF_INTC_IPRL_INT1 (0x2)
#define MCF_INTC_IPRL_INT2 (0x4)
#define MCF_INTC_IPRL_INT3 (0x8)
#define MCF_INTC_IPRL_INT4 (0x10)
#define MCF_INTC_IPRL_INT5 (0x20)
#define MCF_INTC_IPRL_INT6 (0x40)
#define MCF_INTC_IPRL_INT7 (0x80)
#define MCF_INTC_IPRL_INT8 (0x100)
#define MCF_INTC_IPRL_INT9 (0x200)
#define MCF_INTC_IPRL_INT10 (0x400)
#define MCF_INTC_IPRL_INT11 (0x800)
#define MCF_INTC_IPRL_INT12 (0x1000)
#define MCF_INTC_IPRL_INT13 (0x2000)
#define MCF_INTC_IPRL_INT14 (0x4000)
#define MCF_INTC_IPRL_INT15 (0x8000)
#define MCF_INTC_IPRL_INT16 (0x10000)
#define MCF_INTC_IPRL_INT17 (0x20000)
#define MCF_INTC_IPRL_INT18 (0x40000)
#define MCF_INTC_IPRL_INT19 (0x80000)
#define MCF_INTC_IPRL_INT20 (0x100000)
#define MCF_INTC_IPRL_INT21 (0x200000)
#define MCF_INTC_IPRL_INT22 (0x400000)
#define MCF_INTC_IPRL_INT23 (0x800000)
#define MCF_INTC_IPRL_INT24 (0x1000000)
#define MCF_INTC_IPRL_INT25 (0x2000000)
#define MCF_INTC_IPRL_INT26 (0x4000000)
#define MCF_INTC_IPRL_INT27 (0x8000000)
#define MCF_INTC_IPRL_INT28 (0x10000000)
#define MCF_INTC_IPRL_INT29 (0x20000000)
#define MCF_INTC_IPRL_INT30 (0x40000000)
#define MCF_INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRH */
#define MCF_INTC_IMRH_INT_MASK32 (0x1)
#define MCF_INTC_IMRH_INT_MASK33 (0x2)
#define MCF_INTC_IMRH_INT_MASK34 (0x4)
#define MCF_INTC_IMRH_INT_MASK35 (0x8)
#define MCF_INTC_IMRH_INT_MASK36 (0x10)
#define MCF_INTC_IMRH_INT_MASK37 (0x20)
#define MCF_INTC_IMRH_INT_MASK38 (0x40)
#define MCF_INTC_IMRH_INT_MASK39 (0x80)
#define MCF_INTC_IMRH_INT_MASK40 (0x100)
#define MCF_INTC_IMRH_INT_MASK41 (0x200)
#define MCF_INTC_IMRH_INT_MASK42 (0x400)
#define MCF_INTC_IMRH_INT_MASK43 (0x800)
#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRL */
#define MCF_INTC_IMRL_MASKALL (0x1)
#define MCF_INTC_IMRL_INT_MASK1 (0x2)
#define MCF_INTC_IMRL_INT_MASK2 (0x4)
#define MCF_INTC_IMRL_INT_MASK3 (0x8)
#define MCF_INTC_IMRL_INT_MASK4 (0x10)
#define MCF_INTC_IMRL_INT_MASK5 (0x20)
#define MCF_INTC_IMRL_INT_MASK6 (0x40)
#define MCF_INTC_IMRL_INT_MASK7 (0x80)
#define MCF_INTC_IMRL_INT_MASK8 (0x100)
#define MCF_INTC_IMRL_INT_MASK9 (0x200)
#define MCF_INTC_IMRL_INT_MASK10 (0x400)
#define MCF_INTC_IMRL_INT_MASK11 (0x800)
#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCH */
#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCL */
#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IRLR */
#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
/* Bit definitions and macros for MCF_INTC_IACKLPR */
#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
/* Bit definitions and macros for MCF_INTC_ICR */
#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
/* Bit definitions and macros for MCF_INTC_SWIACK */
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_INTC_LIACK */
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
#endif /* __MCF5475_INTC_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_MMU_H__
#define __MCF5475_MMU_H__
/*********************************************************************
*
* Memory Management Unit (MMU)
*
*********************************************************************/
/* Register read/write macros */
/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */
#define MCF_MMU_MMUCR (*(volatile uint32_t_a*)(&_MMUBAR[0]))
#define MCF_MMU_MMUOR (*(volatile uint32_t_a*)(&_MMUBAR[0x4]))
#define MCF_MMU_MMUSR (*(volatile uint32_t_a*)(&_MMUBAR[0x8]))
#define MCF_MMU_MMUAR (*(volatile uint32_t_a*)(&_MMUBAR[0x10]))
#define MCF_MMU_MMUTR (*(volatile uint32_t_a*)(&_MMUBAR[0x14]))
#define MCF_MMU_MMUDR (*(volatile uint32_t_a*)(&_MMUBAR[0x18]))
/* Bit definitions and macros for MCF_MMU_MMUCR */
#define MCF_MMU_MMUCR_EN (0x1)
#define MCF_MMU_MMUCR_ASM (0x2)
/* Bit definitions and macros for MCF_MMU_MMUOR */
#define MCF_MMU_MMUOR_UAA (0x1)
#define MCF_MMU_MMUOR_ACC (0x2)
#define MCF_MMU_MMUOR_RW (0x4)
#define MCF_MMU_MMUOR_ADR (0x8)
#define MCF_MMU_MMUOR_ITLB (0x10)
#define MCF_MMU_MMUOR_CAS (0x20)
#define MCF_MMU_MMUOR_CNL (0x40)
#define MCF_MMU_MMUOR_CA (0x80)
#define MCF_MMU_MMUOR_STLB (0x100)
#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_MMU_MMUSR */
#define MCF_MMU_MMUSR_HIT (0x2)
#define MCF_MMU_MMUSR_WF (0x8)
#define MCF_MMU_MMUSR_RF (0x10)
#define MCF_MMU_MMUSR_SPF (0x20)
/* Bit definitions and macros for MCF_MMU_MMUAR */
#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_MMU_MMUTR */
#define MCF_MMU_MMUTR_V (0x1)
#define MCF_MMU_MMUTR_SG (0x2)
#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2)
#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA)
/* Bit definitions and macros for MCF_MMU_MMUDR */
#define MCF_MMU_MMUDR_LK (0x2)
#define MCF_MMU_MMUDR_X (0x4)
#define MCF_MMU_MMUDR_W (0x8)
#define MCF_MMU_MMUDR_R (0x10)
#define MCF_MMU_MMUDR_SP (0x20)
#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6)
#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8)
#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA)
#endif /* __MCF5475_MMU_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_PAD_H__
#define __MCF5475_PAD_H__
/*********************************************************************
*
* Common GPIO
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&_MBAR[0xA40]))
#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA42]))
#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&_MBAR[0xA43]))
#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&_MBAR[0xA44]))
#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&_MBAR[0xA48]))
#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&_MBAR[0xA4A]))
#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&_MBAR[0xA4C]))
#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&_MBAR[0xA4D]))
#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&_MBAR[0xA4E]))
#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&_MBAR[0xA4F]))
#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&_MBAR[0xA50]))
#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&_MBAR[0xA52]))
/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0)
#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2)
#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3)
#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4)
#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0)
#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20)
#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30)
#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40)
#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100)
#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400)
#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000)
#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000)
/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2)
#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4)
#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8)
#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10)
#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20)
/* Bit definitions and macros for MCF_PAD_PAR_DMA */
#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2)
#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3)
#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC)
#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20)
#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30)
#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80)
#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000)
/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300)
/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300)
/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4)
#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8)
#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0)
#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20)
#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30)
#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0)
#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80)
#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4)
#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8)
#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0)
#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20)
#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30)
#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0)
#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80)
#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4)
#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8)
#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0)
#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30)
#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0)
#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80)
#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4)
#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8)
#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0)
#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30)
#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0)
#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80)
#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2)
#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3)
#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8)
#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC)
#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10)
#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20)
#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30)
#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40)
#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80)
#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0)
#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200)
#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300)
#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA)
#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800)
#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00)
#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000)
/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1)
#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1)
#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4)
#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6)
#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8)
#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20)
#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30)
#endif /* __MCF5475_PAD_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_PCI_H__
#define __MCF5475_PCI_H__
/*********************************************************************
*
* PCI Bus Controller (PCI)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&_MBAR[0xB00]))
#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&_MBAR[0xB04]))
#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&_MBAR[0xB08]))
#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&_MBAR[0xB0C]))
#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&_MBAR[0xB10]))
#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&_MBAR[0xB14]))
#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&_MBAR[0xB28]))
#define MCF_PCI_PCISID (*(volatile uint32_t*)(&_MBAR[0xB2C]))
#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&_MBAR[0xB3C]))
#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&_MBAR[0xB60]))
#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&_MBAR[0xB64]))
#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&_MBAR[0xB68]))
#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&_MBAR[0xB6C]))
#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&_MBAR[0xB70]))
#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&_MBAR[0xB74]))
#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&_MBAR[0xB78]))
#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&_MBAR[0xB80]))
#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&_MBAR[0xB84]))
#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&_MBAR[0xB88]))
#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&_MBAR[0xBF8]))
#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&_MBAR[0x8400]))
#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&_MBAR[0x8404]))
#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&_MBAR[0x8408]))
#define MCF_PCI_PCITER (*(volatile uint32_t*)(&_MBAR[0x840C]))
#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&_MBAR[0x8410]))
#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&_MBAR[0x8414]))
#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&_MBAR[0x8418]))
#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&_MBAR[0x841C]))
#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&_MBAR[0x8440]))
#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&_MBAR[0x8444]))
#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&_MBAR[0x8448]))
#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&_MBAR[0x844C]))
#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&_MBAR[0x8450]))
#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&_MBAR[0x8454]))
#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&_MBAR[0x8480]))
#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&_MBAR[0x8484]))
#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&_MBAR[0x8488]))
#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&_MBAR[0x848C]))
#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&_MBAR[0x8490]))
#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&_MBAR[0x8498]))
#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&_MBAR[0x849C]))
#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&_MBAR[0x84C0]))
#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&_MBAR[0x84C4]))
#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&_MBAR[0x84C8]))
#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&_MBAR[0x84CC]))
#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&_MBAR[0x84D0]))
#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&_MBAR[0x84D4]))
/* Bit definitions and macros for MCF_PCI_PCIIDR */
#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0)
#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PCI_PCISCR */
#define MCF_PCI_PCISCR_IO (0x1)
#define MCF_PCI_PCISCR_M (0x2)
#define MCF_PCI_PCISCR_B (0x4)
#define MCF_PCI_PCISCR_SP (0x8)
#define MCF_PCI_PCISCR_MW (0x10)
#define MCF_PCI_PCISCR_V (0x20)
#define MCF_PCI_PCISCR_PER (0x40)
#define MCF_PCI_PCISCR_ST (0x80)
#define MCF_PCI_PCISCR_S (0x100)
#define MCF_PCI_PCISCR_F (0x200)
#define MCF_PCI_PCISCR_C (0x100000)
#define MCF_PCI_PCISCR_66M (0x200000)
#define MCF_PCI_PCISCR_R (0x400000)
#define MCF_PCI_PCISCR_FC (0x800000)
#define MCF_PCI_PCISCR_DP (0x1000000)
#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19)
#define MCF_PCI_PCISCR_TS (0x8000000)
#define MCF_PCI_PCISCR_TR (0x10000000)
#define MCF_PCI_PCISCR_MA (0x20000000)
#define MCF_PCI_PCISCR_SE (0x40000000)
#define MCF_PCI_PCISCR_PE (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCICCRIR */
#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0)
#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8)
/* Bit definitions and macros for MCF_PCI_PCICR1 */
#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0)
#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8)
#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
#define MCF_PCI_PCIBAR0_IOM (0x1)
#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1)
#define MCF_PCI_PCIBAR0_PREF (0x8)
#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12)
/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
#define MCF_PCI_PCIBAR1_IOM (0x1)
#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1)
#define MCF_PCI_PCIBAR1_PREF (0x8)
#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_PCI_PCICCPR */
#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCISID */
#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCICR2 */
#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0)
#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8)
#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIGSCR */
#define MCF_PCI_PCIGSCR_PR (0x1)
#define MCF_PCI_PCIGSCR_SEE (0x1000)
#define MCF_PCI_PCIGSCR_PEE (0x2000)
#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10)
#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18)
#define MCF_PCI_PCIGSCR_SE (0x10000000)
#define MCF_PCI_PCIGSCR_PE (0x20000000)
/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
#define MCF_PCI_PCITBATR0_EN (0x1)
#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12)
/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
#define MCF_PCI_PCITBATR1_EN (0x1)
#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_PCI_PCITCR */
#define MCF_PCI_PCITCR_P (0x10000)
#define MCF_PCI_PCITCR_LD (0x1000000)
/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8)
#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8)
#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8)
#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIIWCR */
#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100)
#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9)
#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800)
#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000)
#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11)
#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000)
#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19)
#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000)
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100)
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300)
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500)
#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900)
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000)
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000)
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000)
#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000)
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000)
/* Bit definitions and macros for MCF_PCI_PCIICR */
#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0)
#define MCF_PCI_PCIICR_TAE (0x1000000)
#define MCF_PCI_PCIICR_IAE (0x2000000)
#define MCF_PCI_PCIICR_REE (0x4000000)
/* Bit definitions and macros for MCF_PCI_PCIISR */
#define MCF_PCI_PCIISR_TA (0x1000000)
#define MCF_PCI_PCIISR_IA (0x2000000)
#define MCF_PCI_PCIISR_RE (0x4000000)
/* Bit definitions and macros for MCF_PCI_PCICAR */
#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2)
#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8)
#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB)
#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCICAR_E (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCITPSR */
#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PCI_PCITSAR */
#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITTCR */
#define MCF_PCI_PCITTCR_DI (0x1)
#define MCF_PCI_PCITTCR_W (0x10)
#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8)
#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCITER */
#define MCF_PCI_PCITER_NE (0x10000)
#define MCF_PCI_PCITER_IAE (0x20000)
#define MCF_PCI_PCITER_TAE (0x40000)
#define MCF_PCI_PCITER_RE (0x80000)
#define MCF_PCI_PCITER_SE (0x100000)
#define MCF_PCI_PCITER_FEE (0x200000)
#define MCF_PCI_PCITER_ME (0x1000000)
#define MCF_PCI_PCITER_BE (0x8000000)
#define MCF_PCI_PCITER_CM (0x10000000)
#define MCF_PCI_PCITER_RF (0x40000000)
#define MCF_PCI_PCITER_RC (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCITNAR */
#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITLWR */
#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITDCR */
#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0)
#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PCI_PCITSR */
#define MCF_PCI_PCITSR_IA (0x10000)
#define MCF_PCI_PCITSR_TA (0x20000)
#define MCF_PCI_PCITSR_RE (0x40000)
#define MCF_PCI_PCITSR_SE (0x80000)
#define MCF_PCI_PCITSR_FE (0x100000)
#define MCF_PCI_PCITSR_BE1 (0x200000)
#define MCF_PCI_PCITSR_BE2 (0x400000)
#define MCF_PCI_PCITSR_BE3 (0x800000)
#define MCF_PCI_PCITSR_NT (0x1000000)
/* Bit definitions and macros for MCF_PCI_PCITFDR */
#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITFSR */
#define MCF_PCI_PCITFSR_EMPTY (0x10000)
#define MCF_PCI_PCITFSR_ALARM (0x20000)
#define MCF_PCI_PCITFSR_FULL (0x40000)
#define MCF_PCI_PCITFSR_FR (0x80000)
#define MCF_PCI_PCITFSR_OF (0x100000)
#define MCF_PCI_PCITFSR_UF (0x200000)
#define MCF_PCI_PCITFSR_RXW (0x400000)
#define MCF_PCI_PCITFSR_FAE (0x800000)
#define MCF_PCI_PCITFSR_TXW (0x40000000)
#define MCF_PCI_PCITFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCITFCR */
#define MCF_PCI_PCITFCR_TXW_MASK (0x40000)
#define MCF_PCI_PCITFCR_OF_MASK (0x80000)
#define MCF_PCI_PCITFCR_UF_MASK (0x100000)
#define MCF_PCI_PCITFCR_RXW_MASK (0x200000)
#define MCF_PCI_PCITFCR_FAE_MASK (0x400000)
#define MCF_PCI_PCITFCR_IP_MASK (0x800000)
#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_PCI_PCITFCR_WFR (0x20000000)
/* Bit definitions and macros for MCF_PCI_PCITFAR */
#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITFRPR */
#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0)
/* Bit definitions and macros for MCF_PCI_PCITFWPR */
#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRPSR */
#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PCI_PCIRSAR */
#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRTCR */
#define MCF_PCI_PCIRTCR_DI (0x1)
#define MCF_PCI_PCIRTCR_W (0x10)
#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8)
#define MCF_PCI_PCIRTCR_FB (0x1000)
#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIRER */
#define MCF_PCI_PCIRER_NE (0x10000)
#define MCF_PCI_PCIRER_IAE (0x20000)
#define MCF_PCI_PCIRER_TAE (0x40000)
#define MCF_PCI_PCIRER_RE (0x80000)
#define MCF_PCI_PCIRER_SE (0x100000)
#define MCF_PCI_PCIRER_FEE (0x200000)
#define MCF_PCI_PCIRER_ME (0x1000000)
#define MCF_PCI_PCIRER_BE (0x8000000)
#define MCF_PCI_PCIRER_CM (0x10000000)
#define MCF_PCI_PCIRER_FE (0x20000000)
#define MCF_PCI_PCIRER_RF (0x40000000)
#define MCF_PCI_PCIRER_RC (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCIRNAR */
#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRDCR */
#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0)
#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PCI_PCIRSR */
#define MCF_PCI_PCIRSR_IA (0x10000)
#define MCF_PCI_PCIRSR_TA (0x20000)
#define MCF_PCI_PCIRSR_RE (0x40000)
#define MCF_PCI_PCIRSR_SE (0x80000)
#define MCF_PCI_PCIRSR_FE (0x100000)
#define MCF_PCI_PCIRSR_BE1 (0x200000)
#define MCF_PCI_PCIRSR_BE2 (0x400000)
#define MCF_PCI_PCIRSR_BE3 (0x800000)
#define MCF_PCI_PCIRSR_NT (0x1000000)
/* Bit definitions and macros for MCF_PCI_PCIRFDR */
#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRFSR */
#define MCF_PCI_PCIRFSR_EMPTY (0x10000)
#define MCF_PCI_PCIRFSR_ALARM (0x20000)
#define MCF_PCI_PCIRFSR_FULL (0x40000)
#define MCF_PCI_PCIRFSR_FR (0x80000)
#define MCF_PCI_PCIRFSR_OF (0x100000)
#define MCF_PCI_PCIRFSR_UF (0x200000)
#define MCF_PCI_PCIRFSR_RXW (0x400000)
#define MCF_PCI_PCIRFSR_FAE (0x800000)
#define MCF_PCI_PCIRFSR_TXW (0x40000000)
#define MCF_PCI_PCIRFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCIRFCR */
#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000)
#define MCF_PCI_PCIRFCR_OF_MASK (0x80000)
#define MCF_PCI_PCIRFCR_UF_MASK (0x100000)
#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000)
#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000)
#define MCF_PCI_PCIRFCR_IP_MASK (0x800000)
#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_PCI_PCIRFCR_WFR (0x20000000)
/* Bit definitions and macros for MCF_PCI_PCIRFAR */
#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0)
#endif /* __MCF5475_PCI_H__ */

43
tos/pci_mem/include/MCF5475_PCIARB.h Normal file
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@@ -0,0 +1,43 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_PCIARB_H__
#define __MCF5475_PCIARB_H__
/*********************************************************************
*
* PCI Bus Arbiter Module (PCIARB)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&_MBAR[0xC00]))
#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&_MBAR[0xC04]))
/* Bit definitions and macros for MCF_PCIARB_PACR */
#define MCF_PCIARB_PACR_INTMPRI (0x1)
#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1)
#define MCF_PCIARB_PACR_INTMINTEN (0x10000)
#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11)
#define MCF_PCIARB_PACR_DS (0x80000000)
/* Bit definitions and macros for MCF_PCIARB_PASR */
#define MCF_PCIARB_PASR_ITLMBK (0x10000)
#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11)
#endif /* __MCF5475_PCIARB_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_PSC_H__
#define __MCF5475_PSC_H__
/*********************************************************************
*
* Programmable Serial Controller (PSC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8600]))
#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8600]))
#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8604]))
#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8604]))
#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8608]))
#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C]))
#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C]))
#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8610]))
#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8610]))
#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8614]))
#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8614]))
#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8618]))
#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x861C]))
#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8634]))
#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8638]))
#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x863C]))
#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8640]))
#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8644]))
#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8648]))
#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x864C]))
#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8650]))
#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8654]))
#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8658]))
#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x865C]))
#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8660]))
#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8664]))
#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8668]))
#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x866E]))
#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8672]))
#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8676]))
#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x867A]))
#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x867E]))
#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8680]))
#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8684]))
#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8688]))
#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x868E]))
#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8692]))
#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8696]))
#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x869A]))
#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x869E]))
#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8700]))
#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8700]))
#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8704]))
#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8704]))
#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8708]))
#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C]))
#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C]))
#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8710]))
#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8710]))
#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8714]))
#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8714]))
#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8718]))
#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x871C]))
#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8734]))
#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8738]))
#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x873C]))
#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8740]))
#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8744]))
#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8748]))
#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x874C]))
#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8750]))
#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8754]))
#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8758]))
#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x875C]))
#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8760]))
#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8764]))
#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8768]))
#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x876E]))
#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8772]))
#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8776]))
#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x877A]))
#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x877E]))
#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8780]))
#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8784]))
#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8788]))
#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x878E]))
#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8792]))
#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8796]))
#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x879A]))
#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x879E]))
#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8800]))
#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8800]))
#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8804]))
#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8804]))
#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8808]))
#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C]))
#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C]))
#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8810]))
#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8810]))
#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8814]))
#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8814]))
#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8818]))
#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x881C]))
#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8834]))
#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8838]))
#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x883C]))
#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8840]))
#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8844]))
#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8848]))
#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x884C]))
#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8850]))
#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8854]))
#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8858]))
#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x885C]))
#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8860]))
#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8864]))
#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8868]))
#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x886E]))
#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8872]))
#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8876]))
#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x887A]))
#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x887E]))
#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8880]))
#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8884]))
#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8888]))
#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x888E]))
#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8892]))
#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8896]))
#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x889A]))
#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x889E]))
#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8900]))
#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8900]))
#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8904]))
#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8904]))
#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8908]))
#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C]))
#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C]))
#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8910]))
#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8910]))
#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8914]))
#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8914]))
#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8918]))
#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x891C]))
#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8934]))
#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8938]))
#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x893C]))
#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8940]))
#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8944]))
#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8948]))
#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x894C]))
#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8950]))
#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8954]))
#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8958]))
#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x895C]))
#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8960]))
#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8964]))
#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8968]))
#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x896E]))
#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8972]))
#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8976]))
#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x897A]))
#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x897E]))
#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8980]))
#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8984]))
#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8988]))
#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x898E]))
#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8992]))
#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8996]))
#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x899A]))
#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x899E]))
#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)]))
#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)]))
#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)]))
#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)]))
#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)]))
#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)]))
#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)]))
#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)]))
#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)]))
#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)]))
#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)]))
#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)]))
#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)]))
#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)]))
#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)]))
#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)]))
#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)]))
#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)]))
#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)]))
#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)]))
#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)]))
#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)]))
#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)]))
#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)]))
#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)]))
#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)]))
#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)]))
#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)]))
#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)]))
#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)]))
#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)]))
#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)]))
#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)]))
/* Bit definitions and macros for MCF_PSC_PSCMR */
#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0)
#define MCF_PSC_PSCMR_TXCTS (0x10)
#define MCF_PSC_PSCMR_TXRTS (0x20)
#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6)
#define MCF_PSC_PSCMR_CM_NORMAL (0)
#define MCF_PSC_PSCMR_CM_ECHO (0x40)
#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80)
#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0)
#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7)
#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8)
#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF)
#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C)
#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18)
#define MCF_PSC_PSCMR_PM_NONE (0x10)
#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC)
#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8)
#define MCF_PSC_PSCMR_PM_ODD (0x4)
#define MCF_PSC_PSCMR_PM_EVEN (0)
#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0)
#define MCF_PSC_PSCMR_BC_5 (0)
#define MCF_PSC_PSCMR_BC_6 (0x1)
#define MCF_PSC_PSCMR_BC_7 (0x2)
#define MCF_PSC_PSCMR_BC_8 (0x3)
#define MCF_PSC_PSCMR_PT (0x4)
#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3)
#define MCF_PSC_PSCMR_ERR (0x20)
#define MCF_PSC_PSCMR_RXIRQ_FU (0x40)
#define MCF_PSC_PSCMR_RXRTS (0x80)
/* Bit definitions and macros for MCF_PSC_PSCCSR */
#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0)
#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4)
#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D)
#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E)
#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F)
#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0)
#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0)
#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0)
/* Bit definitions and macros for MCF_PSC_PSCSR */
#define MCF_PSC_PSCSR_ERR (0x40)
#define MCF_PSC_PSCSR_CDE_DEOF (0x80)
#define MCF_PSC_PSCSR_RXRDY (0x100)
#define MCF_PSC_PSCSR_FU (0x200)
#define MCF_PSC_PSCSR_TXRDY (0x400)
#define MCF_PSC_PSCSR_TXEMP_URERR (0x800)
#define MCF_PSC_PSCSR_OE (0x1000)
#define MCF_PSC_PSCSR_PE_CRCERR (0x2000)
#define MCF_PSC_PSCSR_FE_PHYERR (0x4000)
#define MCF_PSC_PSCSR_RB_NEOF (0x8000)
/* Bit definitions and macros for MCF_PSC_PSCCR */
#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0)
#define MCF_PSC_PSCCR_RX_ENABLED (0x1)
#define MCF_PSC_PSCCR_RX_DISABLED (0x2)
#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2)
#define MCF_PSC_PSCCR_TX_ENABLED (0x4)
#define MCF_PSC_PSCCR_TX_DISABLED (0x8)
#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4)
#define MCF_PSC_PSCCR_NONE (0)
#define MCF_PSC_PSCCR_RESET_MR (0x10)
#define MCF_PSC_PSCCR_RESET_RX (0x20)
#define MCF_PSC_PSCCR_RESET_TX (0x30)
#define MCF_PSC_PSCCR_RESET_ERROR (0x40)
#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50)
#define MCF_PSC_PSCCR_START_BREAK (0x60)
#define MCF_PSC_PSCCR_STOP_BREAK (0x70)
/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0)
#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8)
#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10)
#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0)
#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8)
#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10)
#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0)
#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0)
#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
#define MCF_PSC_PSCRB_AC97_SOF (0x800)
#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC)
/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC)
/* Bit definitions and macros for MCF_PSC_PSCIPCR */
#define MCF_PSC_PSCIPCR_RESERVED (0xC)
#define MCF_PSC_PSCIPCR_CTS (0xD)
#define MCF_PSC_PSCIPCR_D_CTS (0x1C)
#define MCF_PSC_PSCIPCR_SYNC (0x8C)
/* Bit definitions and macros for MCF_PSC_PSCACR */
#define MCF_PSC_PSCACR_IEC0 (0x1)
/* Bit definitions and macros for MCF_PSC_PSCIMR */
#define MCF_PSC_PSCIMR_ERR (0x40)
#define MCF_PSC_PSCIMR_DEOF (0x80)
#define MCF_PSC_PSCIMR_TXRDY (0x100)
#define MCF_PSC_PSCIMR_RXRDY_FU (0x200)
#define MCF_PSC_PSCIMR_DB (0x400)
#define MCF_PSC_PSCIMR_IPC (0x8000)
/* Bit definitions and macros for MCF_PSC_PSCISR */
#define MCF_PSC_PSCISR_ERR (0x40)
#define MCF_PSC_PSCISR_DEOF (0x80)
#define MCF_PSC_PSCISR_TXRDY (0x100)
#define MCF_PSC_PSCISR_RXRDY_FU (0x200)
#define MCF_PSC_PSCISR_DB (0x400)
#define MCF_PSC_PSCISR_IPC (0x8000)
/* Bit definitions and macros for MCF_PSC_PSCCTUR */
#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCCTLR */
#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCIP */
#define MCF_PSC_PSCIP_CTS (0x1)
#define MCF_PSC_PSCIP_TGL (0x40)
#define MCF_PSC_PSCIP_LPWR_B (0x80)
/* Bit definitions and macros for MCF_PSC_PSCOPSET */
#define MCF_PSC_PSCOPSET_RTS (0x1)
/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
#define MCF_PSC_PSCOPRESET_RTS (0x1)
/* Bit definitions and macros for MCF_PSC_PSCSICR */
#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0)
#define MCF_PSC_PSCSICR_SIM_UART (0)
#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1)
#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2)
#define MCF_PSC_PSCSICR_SIM_AC97 (0x3)
#define MCF_PSC_PSCSICR_SIM_SIR (0x4)
#define MCF_PSC_PSCSICR_SIM_MIR (0x5)
#define MCF_PSC_PSCSICR_SIM_FIR (0x6)
#define MCF_PSC_PSCSICR_SHDIR (0x10)
#define MCF_PSC_PSCSICR_DTS1 (0x20)
#define MCF_PSC_PSCSICR_AWR (0x40)
#define MCF_PSC_PSCSICR_ACRB (0x80)
/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
#define MCF_PSC_PSCIRCR1_SPUL (0x1)
#define MCF_PSC_PSCIRCR1_SIPEN (0x2)
#define MCF_PSC_PSCIRCR1_FD (0x4)
/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
#define MCF_PSC_PSCIRCR2_NXTEOF (0x1)
#define MCF_PSC_PSCIRCR2_ABORT (0x2)
#define MCF_PSC_PSCIRCR2_SIPREQ (0x4)
/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0)
#define MCF_PSC_PSCIRMDR_FREQ (0x80)
/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRFDR */
#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRFSR */
#define MCF_PSC_PSCRFSR_EMT (0x1)
#define MCF_PSC_PSCRFSR_ALARM (0x2)
#define MCF_PSC_PSCRFSR_FU (0x4)
#define MCF_PSC_PSCRFSR_FRMRDY (0x8)
#define MCF_PSC_PSCRFSR_OF (0x10)
#define MCF_PSC_PSCRFSR_UF (0x20)
#define MCF_PSC_PSCRFSR_RXW (0x40)
#define MCF_PSC_PSCRFSR_FAE (0x80)
#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8)
#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800)
#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400)
#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200)
#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100)
#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC)
#define MCF_PSC_PSCRFSR_TXW (0x4000)
#define MCF_PSC_PSCRFSR_IP (0x8000)
/* Bit definitions and macros for MCF_PSC_PSCRFCR */
#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0)
#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000)
#define MCF_PSC_PSCRFCR_OF_MSK (0x80000)
#define MCF_PSC_PSCRFCR_UF_MSK (0x100000)
#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000)
#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000)
#define MCF_PSC_PSCRFCR_IP_MSK (0x800000)
#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_PSC_PSCRFCR_FRMEN (0x8000000)
#define MCF_PSC_PSCRFCR_TIMER (0x10000000)
/* Bit definitions and macros for MCF_PSC_PSCRFAR */
#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRFRP */
#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRFWP */
#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTFDR */
#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTFSR */
#define MCF_PSC_PSCTFSR_EMT (0x1)
#define MCF_PSC_PSCTFSR_ALARM (0x2)
#define MCF_PSC_PSCTFSR_FU (0x4)
#define MCF_PSC_PSCTFSR_FRMRDY (0x8)
#define MCF_PSC_PSCTFSR_OF (0x10)
#define MCF_PSC_PSCTFSR_UF (0x20)
#define MCF_PSC_PSCTFSR_RXW (0x40)
#define MCF_PSC_PSCTFSR_FAE (0x80)
#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8)
#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800)
#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400)
#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200)
#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100)
#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC)
#define MCF_PSC_PSCTFSR_TXW (0x4000)
#define MCF_PSC_PSCTFSR_IP (0x8000)
/* Bit definitions and macros for MCF_PSC_PSCTFCR */
#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0)
#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000)
#define MCF_PSC_PSCTFCR_OF_MSK (0x80000)
#define MCF_PSC_PSCTFCR_UF_MSK (0x100000)
#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000)
#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000)
#define MCF_PSC_PSCTFCR_IP_MSK (0x800000)
#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_PSC_PSCTFCR_FRMEN (0x8000000)
#define MCF_PSC_PSCTFCR_TIMER (0x10000000)
#define MCF_PSC_PSCTFCR_WFR (0x20000000)
/* Bit definitions and macros for MCF_PSC_PSCTFAR */
#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTFRP */
#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTFWP */
#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0)
#endif /* __MCF5475_PSC_H__ */

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tos/pci_mem/include/MCF5475_SDRAMC.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_SDRAMC_H__
#define __MCF5475_SDRAMC_H__
/*********************************************************************
*
* Synchronous DRAM Controller (SDRAMC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&_MBAR[0x4]))
#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&_MBAR[0x20]))
#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&_MBAR[0x24]))
#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&_MBAR[0x28]))
#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&_MBAR[0x2C]))
#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&_MBAR[0x100]))
#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&_MBAR[0x104]))
#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&_MBAR[0x108]))
#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&_MBAR[0x10C]))
#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)]))
/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0)
#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2)
#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4)
#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6)
#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8)
#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0)
#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1)
#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2)
#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3)
/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0)
#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0)
#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13)
#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14)
#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15)
#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16)
#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17)
#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18)
#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19)
#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A)
#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B)
#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C)
#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D)
#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E)
#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F)
#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14)
#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000)
/* Bit definitions and macros for MCF_SDRAMC_SDMR */
#define MCF_SDRAMC_SDMR_CMD (0x10000)
#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12)
#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E)
#define MCF_SDRAMC_SDMR_BK_LMR (0)
#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000)
/* Bit definitions and macros for MCF_SDRAMC_SDCR */
#define MCF_SDRAMC_SDCR_IPALL (0x2)
#define MCF_SDRAMC_SDCR_IREF (0x4)
#define MCF_SDRAMC_SDCR_BUFF (0x10)
#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8)
#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10)
#define MCF_SDRAMC_SDCR_DRIVE (0x400000)
#define MCF_SDRAMC_SDCR_AP (0x800000)
#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18)
#define MCF_SDRAMC_SDCR_REF (0x10000000)
#define MCF_SDRAMC_SDCR_DDR (0x20000000)
#define MCF_SDRAMC_SDCR_CKE (0x40000000)
#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4)
#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8)
#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC)
#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10)
#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14)
#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18)
#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C)
/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10)
#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14)
#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18)
#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C)
#endif /* __MCF5475_SDRAMC_H__ */

398
tos/pci_mem/include/MCF5475_SEC.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_SEC_H__
#define __MCF5475_SEC_H__
/*********************************************************************
*
* Integrated Security Engine (SEC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&_MBAR[0x21000]))
#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&_MBAR[0x21004]))
#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&_MBAR[0x21008]))
#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&_MBAR[0x2100C]))
#define MCF_SEC_SISRH (*(volatile uint32_t*)(&_MBAR[0x21010]))
#define MCF_SEC_SISRL (*(volatile uint32_t*)(&_MBAR[0x21014]))
#define MCF_SEC_SICRH (*(volatile uint32_t*)(&_MBAR[0x21018]))
#define MCF_SEC_SICRL (*(volatile uint32_t*)(&_MBAR[0x2101C]))
#define MCF_SEC_SIDR (*(volatile uint32_t*)(&_MBAR[0x21020]))
#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&_MBAR[0x21028]))
#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&_MBAR[0x2102C]))
#define MCF_SEC_SMCR (*(volatile uint32_t*)(&_MBAR[0x21030]))
#define MCF_SEC_MEAR (*(volatile uint32_t*)(&_MBAR[0x21038]))
#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&_MBAR[0x2200C]))
#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&_MBAR[0x22010]))
#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&_MBAR[0x22014]))
#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&_MBAR[0x22044]))
#define MCF_SEC_FR0 (*(volatile uint32_t*)(&_MBAR[0x2204C]))
#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&_MBAR[0x2300C]))
#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&_MBAR[0x23010]))
#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&_MBAR[0x23014]))
#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&_MBAR[0x23044]))
#define MCF_SEC_FR1 (*(volatile uint32_t*)(&_MBAR[0x2304C]))
#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&_MBAR[0x28018]))
#define MCF_SEC_AFSR (*(volatile uint32_t*)(&_MBAR[0x28028]))
#define MCF_SEC_AFISR (*(volatile uint32_t*)(&_MBAR[0x28030]))
#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&_MBAR[0x28038]))
#define MCF_SEC_DRCR (*(volatile uint32_t*)(&_MBAR[0x2A018]))
#define MCF_SEC_DSR (*(volatile uint32_t*)(&_MBAR[0x2A028]))
#define MCF_SEC_DISR (*(volatile uint32_t*)(&_MBAR[0x2A030]))
#define MCF_SEC_DIMR (*(volatile uint32_t*)(&_MBAR[0x2A038]))
#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&_MBAR[0x2C018]))
#define MCF_SEC_MDSR (*(volatile uint32_t*)(&_MBAR[0x2C028]))
#define MCF_SEC_MDISR (*(volatile uint32_t*)(&_MBAR[0x2C030]))
#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&_MBAR[0x2C038]))
#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&_MBAR[0x2E018]))
#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&_MBAR[0x2E028]))
#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&_MBAR[0x2E030]))
#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&_MBAR[0x2E038]))
#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&_MBAR[0x32018]))
#define MCF_SEC_AESSR (*(volatile uint32_t*)(&_MBAR[0x32028]))
#define MCF_SEC_AESISR (*(volatile uint32_t*)(&_MBAR[0x32030]))
#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&_MBAR[0x32038]))
#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)]))
#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)]))
#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)]))
#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)]))
#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)]))
/* Bit definitions and macros for MCF_SEC_EUACRH */
#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0)
#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0)
#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1)
#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2)
#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8)
#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0)
#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100)
#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200)
#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18)
#define MCF_SEC_EUACRH_RNG_NOASSIGN (0)
#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000)
#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000)
/* Bit definitions and macros for MCF_SEC_EUACRL */
#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10)
#define MCF_SEC_EUACRL_AESU_NOASSIGN (0)
#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000)
#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000)
#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SEC_SIMRH */
#define MCF_SEC_SIMRH_AERR (0x8000000)
#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000)
#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000)
#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000)
#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000)
/* Bit definitions and macros for MCF_SEC_SIMRL */
#define MCF_SEC_SIMRL_TEA (0x40)
#define MCF_SEC_SIMRL_DEU_DN (0x100)
#define MCF_SEC_SIMRL_DEU_ERR (0x200)
#define MCF_SEC_SIMRL_AESU_DN (0x1000)
#define MCF_SEC_SIMRL_AESU_ERR (0x2000)
#define MCF_SEC_SIMRL_MDEU_DN (0x10000)
#define MCF_SEC_SIMRL_MDEU_ERR (0x20000)
#define MCF_SEC_SIMRL_AFEU_DN (0x100000)
#define MCF_SEC_SIMRL_AFEU_ERR (0x200000)
#define MCF_SEC_SIMRL_RNG_DN (0x1000000)
#define MCF_SEC_SIMRL_RNG_ERR (0x2000000)
/* Bit definitions and macros for MCF_SEC_SISRH */
#define MCF_SEC_SISRH_AERR (0x8000000)
#define MCF_SEC_SISRH_CHA_0_DN (0x10000000)
#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000)
#define MCF_SEC_SISRH_CHA_1_DN (0x40000000)
#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000)
/* Bit definitions and macros for MCF_SEC_SISRL */
#define MCF_SEC_SISRL_TEA (0x40)
#define MCF_SEC_SISRL_DEU_DN (0x100)
#define MCF_SEC_SISRL_DEU_ERR (0x200)
#define MCF_SEC_SISRL_AESU_DN (0x1000)
#define MCF_SEC_SISRL_AESU_ERR (0x2000)
#define MCF_SEC_SISRL_MDEU_DN (0x10000)
#define MCF_SEC_SISRL_MDEU_ERR (0x20000)
#define MCF_SEC_SISRL_AFEU_DN (0x100000)
#define MCF_SEC_SISRL_AFEU_ERR (0x200000)
#define MCF_SEC_SISRL_RNG_DN (0x1000000)
#define MCF_SEC_SISRL_RNG_ERR (0x2000000)
/* Bit definitions and macros for MCF_SEC_SICRH */
#define MCF_SEC_SICRH_AERR (0x8000000)
#define MCF_SEC_SICRH_CHA_0_DN (0x10000000)
#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000)
#define MCF_SEC_SICRH_CHA_1_DN (0x40000000)
#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000)
/* Bit definitions and macros for MCF_SEC_SICRL */
#define MCF_SEC_SICRL_TEA (0x40)
#define MCF_SEC_SICRL_DEU_DN (0x100)
#define MCF_SEC_SICRL_DEU_ERR (0x200)
#define MCF_SEC_SICRL_AESU_DN (0x1000)
#define MCF_SEC_SICRL_AESU_ERR (0x2000)
#define MCF_SEC_SICRL_MDEU_DN (0x10000)
#define MCF_SEC_SICRL_MDEU_ERR (0x20000)
#define MCF_SEC_SICRL_AFEU_DN (0x100000)
#define MCF_SEC_SICRL_AFEU_ERR (0x200000)
#define MCF_SEC_SICRL_RNG_DN (0x1000000)
#define MCF_SEC_SICRL_RNG_ERR (0x2000000)
/* Bit definitions and macros for MCF_SEC_SIDR */
#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SEC_EUASRH */
#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0)
#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8)
#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SEC_EUASRL */
#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10)
#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SEC_SMCR */
#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4)
#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10)
#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20)
#define MCF_SEC_SMCR_SWR (0x1000000)
/* Bit definitions and macros for MCF_SEC_MEAR */
#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SEC_CCCRn */
#define MCF_SEC_CCCRn_RST (0x1)
#define MCF_SEC_CCCRn_CDIE (0x2)
#define MCF_SEC_CCCRn_NT (0x4)
#define MCF_SEC_CCCRn_NE (0x8)
#define MCF_SEC_CCCRn_WE (0x10)
#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8)
#define MCF_SEC_CCCRn_BURST_SIZE_2 (0)
#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100)
#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200)
#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300)
#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400)
#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500)
#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600)
#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700)
/* Bit definitions and macros for MCF_SEC_CCPSRHn */
#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_SEC_CCPSRLn */
#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0)
#define MCF_SEC_CCPSRLn_EUERR (0x100)
#define MCF_SEC_CCPSRLn_SERR (0x200)
#define MCF_SEC_CCPSRLn_DERR (0x400)
#define MCF_SEC_CCPSRLn_PERR (0x1000)
#define MCF_SEC_CCPSRLn_TEA (0x2000)
#define MCF_SEC_CCPSRLn_SD (0x10000)
#define MCF_SEC_CCPSRLn_PD (0x20000)
#define MCF_SEC_CCPSRLn_SRD (0x40000)
#define MCF_SEC_CCPSRLn_PRD (0x80000)
#define MCF_SEC_CCPSRLn_SG (0x100000)
#define MCF_SEC_CCPSRLn_PG (0x200000)
#define MCF_SEC_CCPSRLn_SR (0x400000)
#define MCF_SEC_CCPSRLn_PR (0x800000)
#define MCF_SEC_CCPSRLn_MO (0x1000000)
#define MCF_SEC_CCPSRLn_MI (0x2000000)
#define MCF_SEC_CCPSRLn_STAT (0x4000000)
/* Bit definitions and macros for MCF_SEC_CDPRn */
#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SEC_FRn */
#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SEC_AFRCR */
#define MCF_SEC_AFRCR_SR (0x1000000)
#define MCF_SEC_AFRCR_MI (0x2000000)
#define MCF_SEC_AFRCR_RI (0x4000000)
/* Bit definitions and macros for MCF_SEC_AFSR */
#define MCF_SEC_AFSR_RD (0x1000000)
#define MCF_SEC_AFSR_ID (0x2000000)
#define MCF_SEC_AFSR_IE (0x4000000)
#define MCF_SEC_AFSR_OFR (0x8000000)
#define MCF_SEC_AFSR_IFW (0x10000000)
#define MCF_SEC_AFSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_AFISR */
#define MCF_SEC_AFISR_DSE (0x10000)
#define MCF_SEC_AFISR_KSE (0x20000)
#define MCF_SEC_AFISR_CE (0x40000)
#define MCF_SEC_AFISR_ERE (0x80000)
#define MCF_SEC_AFISR_IE (0x100000)
#define MCF_SEC_AFISR_OFU (0x2000000)
#define MCF_SEC_AFISR_IFO (0x4000000)
#define MCF_SEC_AFISR_IFE (0x10000000)
#define MCF_SEC_AFISR_OFE (0x20000000)
#define MCF_SEC_AFISR_AE (0x40000000)
#define MCF_SEC_AFISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_AFIMR */
#define MCF_SEC_AFIMR_DSE (0x10000)
#define MCF_SEC_AFIMR_KSE (0x20000)
#define MCF_SEC_AFIMR_CE (0x40000)
#define MCF_SEC_AFIMR_ERE (0x80000)
#define MCF_SEC_AFIMR_IE (0x100000)
#define MCF_SEC_AFIMR_OFU (0x2000000)
#define MCF_SEC_AFIMR_IFO (0x4000000)
#define MCF_SEC_AFIMR_IFE (0x10000000)
#define MCF_SEC_AFIMR_OFE (0x20000000)
#define MCF_SEC_AFIMR_AE (0x40000000)
#define MCF_SEC_AFIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_DRCR */
#define MCF_SEC_DRCR_SR (0x1000000)
#define MCF_SEC_DRCR_MI (0x2000000)
#define MCF_SEC_DRCR_RI (0x4000000)
/* Bit definitions and macros for MCF_SEC_DSR */
#define MCF_SEC_DSR_RD (0x1000000)
#define MCF_SEC_DSR_ID (0x2000000)
#define MCF_SEC_DSR_IE (0x4000000)
#define MCF_SEC_DSR_OFR (0x8000000)
#define MCF_SEC_DSR_IFW (0x10000000)
#define MCF_SEC_DSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_DISR */
#define MCF_SEC_DISR_DSE (0x10000)
#define MCF_SEC_DISR_KSE (0x20000)
#define MCF_SEC_DISR_CE (0x40000)
#define MCF_SEC_DISR_ERE (0x80000)
#define MCF_SEC_DISR_IE (0x100000)
#define MCF_SEC_DISR_KPE (0x200000)
#define MCF_SEC_DISR_OFU (0x2000000)
#define MCF_SEC_DISR_IFO (0x4000000)
#define MCF_SEC_DISR_IFE (0x10000000)
#define MCF_SEC_DISR_OFE (0x20000000)
#define MCF_SEC_DISR_AE (0x40000000)
#define MCF_SEC_DISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_DIMR */
#define MCF_SEC_DIMR_DSE (0x10000)
#define MCF_SEC_DIMR_KSE (0x20000)
#define MCF_SEC_DIMR_CE (0x40000)
#define MCF_SEC_DIMR_ERE (0x80000)
#define MCF_SEC_DIMR_IE (0x100000)
#define MCF_SEC_DIMR_KPE (0x200000)
#define MCF_SEC_DIMR_OFU (0x2000000)
#define MCF_SEC_DIMR_IFO (0x4000000)
#define MCF_SEC_DIMR_IFE (0x10000000)
#define MCF_SEC_DIMR_OFE (0x20000000)
#define MCF_SEC_DIMR_AE (0x40000000)
#define MCF_SEC_DIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_MDRCR */
#define MCF_SEC_MDRCR_SR (0x1000000)
#define MCF_SEC_MDRCR_MI (0x2000000)
#define MCF_SEC_MDRCR_RI (0x4000000)
/* Bit definitions and macros for MCF_SEC_MDSR */
#define MCF_SEC_MDSR_RD (0x1000000)
#define MCF_SEC_MDSR_ID (0x2000000)
#define MCF_SEC_MDSR_IE (0x4000000)
#define MCF_SEC_MDSR_IFW (0x10000000)
#define MCF_SEC_MDSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_MDISR */
#define MCF_SEC_MDISR_DSE (0x10000)
#define MCF_SEC_MDISR_KSE (0x20000)
#define MCF_SEC_MDISR_CE (0x40000)
#define MCF_SEC_MDISR_ERE (0x80000)
#define MCF_SEC_MDISR_IE (0x100000)
#define MCF_SEC_MDISR_IFO (0x4000000)
#define MCF_SEC_MDISR_AE (0x40000000)
#define MCF_SEC_MDISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_MDIMR */
#define MCF_SEC_MDIMR_DSE (0x10000)
#define MCF_SEC_MDIMR_KSE (0x20000)
#define MCF_SEC_MDIMR_CE (0x40000)
#define MCF_SEC_MDIMR_ERE (0x80000)
#define MCF_SEC_MDIMR_IE (0x100000)
#define MCF_SEC_MDIMR_IFO (0x4000000)
#define MCF_SEC_MDIMR_AE (0x40000000)
#define MCF_SEC_MDIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_RNGRCR */
#define MCF_SEC_RNGRCR_SR (0x1000000)
#define MCF_SEC_RNGRCR_MI (0x2000000)
#define MCF_SEC_RNGRCR_RI (0x4000000)
/* Bit definitions and macros for MCF_SEC_RNGSR */
#define MCF_SEC_RNGSR_RD (0x1000000)
#define MCF_SEC_RNGSR_IE (0x4000000)
#define MCF_SEC_RNGSR_OFR (0x8000000)
#define MCF_SEC_RNGSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_RNGISR */
#define MCF_SEC_RNGISR_IE (0x100000)
#define MCF_SEC_RNGISR_OFU (0x2000000)
#define MCF_SEC_RNGISR_AE (0x40000000)
#define MCF_SEC_RNGISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_RNGIMR */
#define MCF_SEC_RNGIMR_IE (0x100000)
#define MCF_SEC_RNGIMR_OFU (0x2000000)
#define MCF_SEC_RNGIMR_AE (0x40000000)
#define MCF_SEC_RNGIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_AESRCR */
#define MCF_SEC_AESRCR_SR (0x1000000)
#define MCF_SEC_AESRCR_MI (0x2000000)
#define MCF_SEC_AESRCR_RI (0x4000000)
/* Bit definitions and macros for MCF_SEC_AESSR */
#define MCF_SEC_AESSR_RD (0x1000000)
#define MCF_SEC_AESSR_ID (0x2000000)
#define MCF_SEC_AESSR_IE (0x4000000)
#define MCF_SEC_AESSR_OFR (0x8000000)
#define MCF_SEC_AESSR_IFW (0x10000000)
#define MCF_SEC_AESSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_AESISR */
#define MCF_SEC_AESISR_DSE (0x10000)
#define MCF_SEC_AESISR_KSE (0x20000)
#define MCF_SEC_AESISR_CE (0x40000)
#define MCF_SEC_AESISR_ERE (0x80000)
#define MCF_SEC_AESISR_IE (0x100000)
#define MCF_SEC_AESISR_OFU (0x2000000)
#define MCF_SEC_AESISR_IFO (0x4000000)
#define MCF_SEC_AESISR_IFE (0x10000000)
#define MCF_SEC_AESISR_OFE (0x20000000)
#define MCF_SEC_AESISR_AE (0x40000000)
#define MCF_SEC_AESISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_AESIMR */
#define MCF_SEC_AESIMR_DSE (0x10000)
#define MCF_SEC_AESIMR_KSE (0x20000)
#define MCF_SEC_AESIMR_CE (0x40000)
#define MCF_SEC_AESIMR_ERE (0x80000)
#define MCF_SEC_AESIMR_IE (0x100000)
#define MCF_SEC_AESIMR_OFU (0x2000000)
#define MCF_SEC_AESIMR_IFO (0x4000000)
#define MCF_SEC_AESIMR_IFE (0x10000000)
#define MCF_SEC_AESIMR_OFE (0x20000000)
#define MCF_SEC_AESIMR_AE (0x40000000)
#define MCF_SEC_AESIMR_ME (0x80000000)
#endif /* __MCF5475_SEC_H__ */

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tos/pci_mem/include/MCF5475_SIU.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_SIU_H__
#define __MCF5475_SIU_H__
/*********************************************************************
*
* System Integration Unit (SIU)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SIU_SBCR (*(volatile uint32_t*)(&_MBAR[0x10]))
#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&_MBAR[0x38]))
#define MCF_SIU_RSR (*(volatile uint32_t*)(&_MBAR[0x44]))
#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&_MBAR[0x50]))
/* Bit definitions and macros for MCF_SIU_SBCR */
#define MCF_SIU_SBCR_PIN2DSPI (0x8000000)
#define MCF_SIU_SBCR_DMA2CPU (0x10000000)
#define MCF_SIU_SBCR_CPU2DMA (0x20000000)
#define MCF_SIU_SBCR_PIN2DMA (0x40000000)
#define MCF_SIU_SBCR_PIN2CPU (0x80000000)
/* Bit definitions and macros for MCF_SIU_SECSACR */
#define MCF_SIU_SECSACR_SEQEN (0x1)
/* Bit definitions and macros for MCF_SIU_RSR */
#define MCF_SIU_RSR_RST (0x1)
#define MCF_SIU_RSR_RSTWD (0x2)
#define MCF_SIU_RSR_RSTJTG (0x8)
/* Bit definitions and macros for MCF_SIU_JTAGID */
#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SIU_JTAGID */
#define MCF_SIU_JTAGID_REV (0xF0000000)
#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF)
#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D)
#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D)
#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D)
#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D)
#define MCF_SIU_JTAGID_MCF5481 (0x0801001D)
#define MCF_SIU_JTAGID_MCF5480 (0x0801101D)
#define MCF_SIU_JTAGID_MCF5475 (0x0801201D)
#define MCF_SIU_JTAGID_MCF5474 (0x0801301D)
#define MCF_SIU_JTAGID_MCF5473 (0x0801401D)
#define MCF_SIU_JTAGID_MCF5472 (0x0801501D)
#define MCF_SIU_JTAGID_MCF5471 (0x0801601D)
#define MCF_SIU_JTAGID_MCF5470 (0x0801701D)
#endif /* __MCF5475_SIU_H__ */

59
tos/pci_mem/include/MCF5475_SLT.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_SLT_H__
#define __MCF5475_SLT_H__
/*********************************************************************
*
* Slice Timers (SLT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&_MBAR[0x900]))
#define MCF_SLT0_SCR (*(volatile uint32_t*)(&_MBAR[0x904]))
#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&_MBAR[0x908]))
#define MCF_SLT0_SSR (*(volatile uint32_t*)(&_MBAR[0x90C]))
#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&_MBAR[0x910]))
#define MCF_SLT1_SCR (*(volatile uint32_t*)(&_MBAR[0x914]))
#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&_MBAR[0x918]))
#define MCF_SLT1_SSR (*(volatile uint32_t*)(&_MBAR[0x91C]))
#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)]))
#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)]))
#define MCF_SLT_SCNT(x) (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)]))
#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)]))
/* Bit definitions and macros for MCF_SLT_STCNT */
#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SLT_SCR */
#define MCF_SLT_SCR_TEN (0x1000000)
#define MCF_SLT_SCR_IEN (0x2000000)
#define MCF_SLT_SCR_RUN (0x4000000)
/* Bit definitions and macros for MCF_SLT_SCNT */
#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SLT_SSR */
#define MCF_SLT_SSR_ST (0x1000000)
#define MCF_SLT_SSR_BE (0x2000000)
#endif /* __MCF5475_SLT_H__ */

62
tos/pci_mem/include/MCF5475_SRAM.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_SRAM_H__
#define __MCF5475_SRAM_H__
/*********************************************************************
*
* System SRAM Module (SRAM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SRAM_SSCR (*(volatile uint32_t*)(&__MBAR[0x1FFC0]))
#define MCF_SRAM_TCCR (*(volatile uint32_t*)(&__MBAR[0x1FFC4]))
#define MCF_SRAM_TCCRDR (*(volatile uint32_t*)(&__MBAR[0x1FFC8]))
#define MCF_SRAM_TCCRDW (*(volatile uint32_t*)(&__MBAR[0x1FFCC]))
#define MCF_SRAM_TCCRSEC (*(volatile uint32_t*)(&__MBAR[0x1FFD0]))
/* Bit definitions and macros for MCF_SRAM_SSCR */
#define MCF_SRAM_SSCR_INLV (0x10000)
/* Bit definitions and macros for MCF_SRAM_TCCR */
#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0)
#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8)
#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10)
#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SRAM_TCCRDR */
#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0)
#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8)
#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10)
#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SRAM_TCCRDW */
#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0)
#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8)
#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10)
#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0)
#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8)
#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10)
#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18)
#endif /* __MCF5475_SRAM_H__ */

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tos/pci_mem/include/MCF5475_USB.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_USB_H__
#define __MCF5475_USB_H__
/*********************************************************************
*
* Universal Serial Bus Interface (USB)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_USB_USBAISR (*(volatile uint8_t *)(&__MBAR[0xB000]))
#define MCF_USB_USBAIMR (*(volatile uint8_t *)(&__MBAR[0xB001]))
#define MCF_USB_EPINFO (*(volatile uint8_t *)(&__MBAR[0xB003]))
#define MCF_USB_CFGR (*(volatile uint8_t *)(&__MBAR[0xB004]))
#define MCF_USB_CFGAR (*(volatile uint8_t *)(&__MBAR[0xB005]))
#define MCF_USB_SPEEDR (*(volatile uint8_t *)(&__MBAR[0xB006]))
#define MCF_USB_FRMNUMR (*(volatile uint16_t*)(&__MBAR[0xB00E]))
#define MCF_USB_EPTNR (*(volatile uint16_t*)(&__MBAR[0xB010]))
#define MCF_USB_IFUR (*(volatile uint16_t*)(&__MBAR[0xB014]))
#define MCF_USB_IFR0 (*(volatile uint16_t*)(&__MBAR[0xB040]))
#define MCF_USB_IFR1 (*(volatile uint16_t*)(&__MBAR[0xB042]))
#define MCF_USB_IFR2 (*(volatile uint16_t*)(&__MBAR[0xB044]))
#define MCF_USB_IFR3 (*(volatile uint16_t*)(&__MBAR[0xB046]))
#define MCF_USB_IFR4 (*(volatile uint16_t*)(&__MBAR[0xB048]))
#define MCF_USB_IFR5 (*(volatile uint16_t*)(&__MBAR[0xB04A]))
#define MCF_USB_IFR6 (*(volatile uint16_t*)(&__MBAR[0xB04C]))
#define MCF_USB_IFR7 (*(volatile uint16_t*)(&__MBAR[0xB04E]))
#define MCF_USB_IFR8 (*(volatile uint16_t*)(&__MBAR[0xB050]))
#define MCF_USB_IFR9 (*(volatile uint16_t*)(&__MBAR[0xB052]))
#define MCF_USB_IFR10 (*(volatile uint16_t*)(&__MBAR[0xB054]))
#define MCF_USB_IFR11 (*(volatile uint16_t*)(&__MBAR[0xB056]))
#define MCF_USB_IFR12 (*(volatile uint16_t*)(&__MBAR[0xB058]))
#define MCF_USB_IFR13 (*(volatile uint16_t*)(&__MBAR[0xB05A]))
#define MCF_USB_IFR14 (*(volatile uint16_t*)(&__MBAR[0xB05C]))
#define MCF_USB_IFR15 (*(volatile uint16_t*)(&__MBAR[0xB05E]))
#define MCF_USB_IFR16 (*(volatile uint16_t*)(&__MBAR[0xB060]))
#define MCF_USB_IFR17 (*(volatile uint16_t*)(&__MBAR[0xB062]))
#define MCF_USB_IFR18 (*(volatile uint16_t*)(&__MBAR[0xB064]))
#define MCF_USB_IFR19 (*(volatile uint16_t*)(&__MBAR[0xB066]))
#define MCF_USB_IFR20 (*(volatile uint16_t*)(&__MBAR[0xB068]))
#define MCF_USB_IFR21 (*(volatile uint16_t*)(&__MBAR[0xB06A]))
#define MCF_USB_IFR22 (*(volatile uint16_t*)(&__MBAR[0xB06C]))
#define MCF_USB_IFR23 (*(volatile uint16_t*)(&__MBAR[0xB06E]))
#define MCF_USB_IFR24 (*(volatile uint16_t*)(&__MBAR[0xB070]))
#define MCF_USB_IFR25 (*(volatile uint16_t*)(&__MBAR[0xB072]))
#define MCF_USB_IFR26 (*(volatile uint16_t*)(&__MBAR[0xB074]))
#define MCF_USB_IFR27 (*(volatile uint16_t*)(&__MBAR[0xB076]))
#define MCF_USB_IFR28 (*(volatile uint16_t*)(&__MBAR[0xB078]))
#define MCF_USB_IFR29 (*(volatile uint16_t*)(&__MBAR[0xB07A]))
#define MCF_USB_IFR30 (*(volatile uint16_t*)(&__MBAR[0xB07C]))
#define MCF_USB_IFR31 (*(volatile uint16_t*)(&__MBAR[0xB07E]))
#define MCF_USB_PPCNT (*(volatile uint16_t*)(&__MBAR[0xB080]))
#define MCF_USB_DPCNT (*(volatile uint16_t*)(&__MBAR[0xB082]))
#define MCF_USB_CRCECNT (*(volatile uint16_t*)(&__MBAR[0xB084]))
#define MCF_USB_BSECNT (*(volatile uint16_t*)(&__MBAR[0xB086]))
#define MCF_USB_PIDECNT (*(volatile uint16_t*)(&__MBAR[0xB088]))
#define MCF_USB_FRMECNT (*(volatile uint16_t*)(&__MBAR[0xB08A]))
#define MCF_USB_TXPCNT (*(volatile uint16_t*)(&__MBAR[0xB08C]))
#define MCF_USB_CNTOVR (*(volatile uint8_t *)(&__MBAR[0xB08E]))
#define MCF_USB_EP0ACR (*(volatile uint8_t *)(&__MBAR[0xB101]))
#define MCF_USB_EP0MPSR (*(volatile uint16_t*)(&__MBAR[0xB102]))
#define MCF_USB_EP0IFR (*(volatile uint8_t *)(&__MBAR[0xB104]))
#define MCF_USB_EP0SR (*(volatile uint8_t *)(&__MBAR[0xB105]))
#define MCF_USB_BMRTR (*(volatile uint8_t *)(&__MBAR[0xB106]))
#define MCF_USB_BRTR (*(volatile uint8_t *)(&__MBAR[0xB107]))
#define MCF_USB_WVALUER (*(volatile uint16_t*)(&__MBAR[0xB108]))
#define MCF_USB_WINDEXR (*(volatile uint16_t*)(&__MBAR[0xB10A]))
#define MCF_USB_WLENGTHR (*(volatile uint16_t*)(&__MBAR[0xB10C]))
#define MCF_USB_EP1OUTACR (*(volatile uint8_t *)(&__MBAR[0xB131]))
#define MCF_USB_EP1OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB132]))
#define MCF_USB_EP1OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB134]))
#define MCF_USB_EP1OUTSR (*(volatile uint8_t *)(&__MBAR[0xB135]))
#define MCF_USB_EP1OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB13E]))
#define MCF_USB_EP1INACR (*(volatile uint8_t *)(&__MBAR[0xB149]))
#define MCF_USB_EP1INMPSR (*(volatile uint16_t*)(&__MBAR[0xB14A]))
#define MCF_USB_EP1INIFR (*(volatile uint8_t *)(&__MBAR[0xB14C]))
#define MCF_USB_EP1INSR (*(volatile uint8_t *)(&__MBAR[0xB14D]))
#define MCF_USB_EP1INSFR (*(volatile uint16_t*)(&__MBAR[0xB156]))
#define MCF_USB_EP2OUTACR (*(volatile uint8_t *)(&__MBAR[0xB161]))
#define MCF_USB_EP2OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB162]))
#define MCF_USB_EP2OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB164]))
#define MCF_USB_EP2OUTSR (*(volatile uint8_t *)(&__MBAR[0xB165]))
#define MCF_USB_EP2OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB16E]))
#define MCF_USB_EP2INACR (*(volatile uint8_t *)(&__MBAR[0xB179]))
#define MCF_USB_EP2INMPSR (*(volatile uint16_t*)(&__MBAR[0xB17A]))
#define MCF_USB_EP2INIFR (*(volatile uint8_t *)(&__MBAR[0xB17C]))
#define MCF_USB_EP2INSR (*(volatile uint8_t *)(&__MBAR[0xB17D]))
#define MCF_USB_EP2INSFR (*(volatile uint16_t*)(&__MBAR[0xB186]))
#define MCF_USB_EP3OUTACR (*(volatile uint8_t *)(&__MBAR[0xB191]))
#define MCF_USB_EP3OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB192]))
#define MCF_USB_EP3OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB194]))
#define MCF_USB_EP3OUTSR (*(volatile uint8_t *)(&__MBAR[0xB195]))
#define MCF_USB_EP3OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB19E]))
#define MCF_USB_EP3INACR (*(volatile uint8_t *)(&__MBAR[0xB1A9]))
#define MCF_USB_EP3INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1AA]))
#define MCF_USB_EP3INIFR (*(volatile uint8_t *)(&__MBAR[0xB1AC]))
#define MCF_USB_EP3INSR (*(volatile uint8_t *)(&__MBAR[0xB1AD]))
#define MCF_USB_EP3INSFR (*(volatile uint16_t*)(&__MBAR[0xB1B6]))
#define MCF_USB_EP4OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1C1]))
#define MCF_USB_EP4OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1C2]))
#define MCF_USB_EP4OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1C4]))
#define MCF_USB_EP4OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1C5]))
#define MCF_USB_EP4OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1CE]))
#define MCF_USB_EP4INACR (*(volatile uint8_t *)(&__MBAR[0xB1D9]))
#define MCF_USB_EP4INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1DA]))
#define MCF_USB_EP4INIFR (*(volatile uint8_t *)(&__MBAR[0xB1DC]))
#define MCF_USB_EP4INSR (*(volatile uint8_t *)(&__MBAR[0xB1DD]))
#define MCF_USB_EP4INSFR (*(volatile uint16_t*)(&__MBAR[0xB1E6]))
#define MCF_USB_EP5OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1F1]))
#define MCF_USB_EP5OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1F2]))
#define MCF_USB_EP5OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1F4]))
#define MCF_USB_EP5OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1F5]))
#define MCF_USB_EP5OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1FE]))
#define MCF_USB_EP5INACR (*(volatile uint8_t *)(&__MBAR[0xB209]))
#define MCF_USB_EP5INMPSR (*(volatile uint16_t*)(&__MBAR[0xB20A]))
#define MCF_USB_EP5INIFR (*(volatile uint8_t *)(&__MBAR[0xB20C]))
#define MCF_USB_EP5INSR (*(volatile uint8_t *)(&__MBAR[0xB20D]))
#define MCF_USB_EP5INSFR (*(volatile uint16_t*)(&__MBAR[0xB216]))
#define MCF_USB_EP6OUTACR (*(volatile uint8_t *)(&__MBAR[0xB221]))
#define MCF_USB_EP6OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB222]))
#define MCF_USB_EP6OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB224]))
#define MCF_USB_EP6OUTSR (*(volatile uint8_t *)(&__MBAR[0xB225]))
#define MCF_USB_EP6OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB22E]))
#define MCF_USB_EP6INACR (*(volatile uint8_t *)(&__MBAR[0xB239]))
#define MCF_USB_EP6INMPSR (*(volatile uint16_t*)(&__MBAR[0xB23A]))
#define MCF_USB_EP6INIFR (*(volatile uint8_t *)(&__MBAR[0xB23C]))
#define MCF_USB_EP6INSR (*(volatile uint8_t *)(&__MBAR[0xB23D]))
#define MCF_USB_EP6INSFR (*(volatile uint16_t*)(&__MBAR[0xB246]))
#define MCF_USB_USBSR (*(volatile uint32_t*)(&__MBAR[0xB400]))
#define MCF_USB_USBCR (*(volatile uint32_t*)(&__MBAR[0xB404]))
#define MCF_USB_DRAMCR (*(volatile uint32_t*)(&__MBAR[0xB408]))
#define MCF_USB_DRAMDR (*(volatile uint32_t*)(&__MBAR[0xB40C]))
#define MCF_USB_USBISR (*(volatile uint32_t*)(&__MBAR[0xB410]))
#define MCF_USB_USBIMR (*(volatile uint32_t*)(&__MBAR[0xB414]))
#define MCF_USB_EP0STAT (*(volatile uint32_t*)(&__MBAR[0xB440]))
#define MCF_USB_EP0ISR (*(volatile uint32_t*)(&__MBAR[0xB444]))
#define MCF_USB_EP0IMR (*(volatile uint32_t*)(&__MBAR[0xB448]))
#define MCF_USB_EP0FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB44C]))
#define MCF_USB_EP0FDR (*(volatile uint32_t*)(&__MBAR[0xB450]))
#define MCF_USB_EP0FSR (*(volatile uint32_t*)(&__MBAR[0xB454]))
#define MCF_USB_EP0FCR (*(volatile uint32_t*)(&__MBAR[0xB458]))
#define MCF_USB_EP0FAR (*(volatile uint32_t*)(&__MBAR[0xB45C]))
#define MCF_USB_EP0FRP (*(volatile uint32_t*)(&__MBAR[0xB460]))
#define MCF_USB_EP0FWP (*(volatile uint32_t*)(&__MBAR[0xB464]))
#define MCF_USB_EP0LRFP (*(volatile uint32_t*)(&__MBAR[0xB468]))
#define MCF_USB_EP0LWFP (*(volatile uint32_t*)(&__MBAR[0xB46C]))
#define MCF_USB_EP1STAT (*(volatile uint32_t*)(&__MBAR[0xB470]))
#define MCF_USB_EP1ISR (*(volatile uint32_t*)(&__MBAR[0xB474]))
#define MCF_USB_EP1IMR (*(volatile uint32_t*)(&__MBAR[0xB478]))
#define MCF_USB_EP1FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB47C]))
#define MCF_USB_EP1FDR (*(volatile uint32_t*)(&__MBAR[0xB480]))
#define MCF_USB_EP1FSR (*(volatile uint32_t*)(&__MBAR[0xB484]))
#define MCF_USB_EP1FCR (*(volatile uint32_t*)(&__MBAR[0xB488]))
#define MCF_USB_EP1FAR (*(volatile uint32_t*)(&__MBAR[0xB48C]))
#define MCF_USB_EP1FRP (*(volatile uint32_t*)(&__MBAR[0xB490]))
#define MCF_USB_EP1FWP (*(volatile uint32_t*)(&__MBAR[0xB494]))
#define MCF_USB_EP1LRFP (*(volatile uint32_t*)(&__MBAR[0xB498]))
#define MCF_USB_EP1LWFP (*(volatile uint32_t*)(&__MBAR[0xB49C]))
#define MCF_USB_EP2STAT (*(volatile uint32_t*)(&__MBAR[0xB4A0]))
#define MCF_USB_EP2ISR (*(volatile uint32_t*)(&__MBAR[0xB4A4]))
#define MCF_USB_EP2IMR (*(volatile uint32_t*)(&__MBAR[0xB4A8]))
#define MCF_USB_EP2FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4AC]))
#define MCF_USB_EP2FDR (*(volatile uint32_t*)(&__MBAR[0xB4B0]))
#define MCF_USB_EP2FSR (*(volatile uint32_t*)(&__MBAR[0xB4B4]))
#define MCF_USB_EP2FCR (*(volatile uint32_t*)(&__MBAR[0xB4B8]))
#define MCF_USB_EP2FAR (*(volatile uint32_t*)(&__MBAR[0xB4BC]))
#define MCF_USB_EP2FRP (*(volatile uint32_t*)(&__MBAR[0xB4C0]))
#define MCF_USB_EP2FWP (*(volatile uint32_t*)(&__MBAR[0xB4C4]))
#define MCF_USB_EP2LRFP (*(volatile uint32_t*)(&__MBAR[0xB4C8]))
#define MCF_USB_EP2LWFP (*(volatile uint32_t*)(&__MBAR[0xB4CC]))
#define MCF_USB_EP3STAT (*(volatile uint32_t*)(&__MBAR[0xB4D0]))
#define MCF_USB_EP3ISR (*(volatile uint32_t*)(&__MBAR[0xB4D4]))
#define MCF_USB_EP3IMR (*(volatile uint32_t*)(&__MBAR[0xB4D8]))
#define MCF_USB_EP3FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4DC]))
#define MCF_USB_EP3FDR (*(volatile uint32_t*)(&__MBAR[0xB4E0]))
#define MCF_USB_EP3FSR (*(volatile uint32_t*)(&__MBAR[0xB4E4]))
#define MCF_USB_EP3FCR (*(volatile uint32_t*)(&__MBAR[0xB4E8]))
#define MCF_USB_EP3FAR (*(volatile uint32_t*)(&__MBAR[0xB4EC]))
#define MCF_USB_EP3FRP (*(volatile uint32_t*)(&__MBAR[0xB4F0]))
#define MCF_USB_EP3FWP (*(volatile uint32_t*)(&__MBAR[0xB4F4]))
#define MCF_USB_EP3LRFP (*(volatile uint32_t*)(&__MBAR[0xB4F8]))
#define MCF_USB_EP3LWFP (*(volatile uint32_t*)(&__MBAR[0xB4FC]))
#define MCF_USB_EP4STAT (*(volatile uint32_t*)(&__MBAR[0xB500]))
#define MCF_USB_EP4ISR (*(volatile uint32_t*)(&__MBAR[0xB504]))
#define MCF_USB_EP4IMR (*(volatile uint32_t*)(&__MBAR[0xB508]))
#define MCF_USB_EP4FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB50C]))
#define MCF_USB_EP4FDR (*(volatile uint32_t*)(&__MBAR[0xB510]))
#define MCF_USB_EP4FSR (*(volatile uint32_t*)(&__MBAR[0xB514]))
#define MCF_USB_EP4FCR (*(volatile uint32_t*)(&__MBAR[0xB518]))
#define MCF_USB_EP4FAR (*(volatile uint32_t*)(&__MBAR[0xB51C]))
#define MCF_USB_EP4FRP (*(volatile uint32_t*)(&__MBAR[0xB520]))
#define MCF_USB_EP4FWP (*(volatile uint32_t*)(&__MBAR[0xB524]))
#define MCF_USB_EP4LRFP (*(volatile uint32_t*)(&__MBAR[0xB528]))
#define MCF_USB_EP4LWFP (*(volatile uint32_t*)(&__MBAR[0xB52C]))
#define MCF_USB_EP5STAT (*(volatile uint32_t*)(&__MBAR[0xB530]))
#define MCF_USB_EP5ISR (*(volatile uint32_t*)(&__MBAR[0xB534]))
#define MCF_USB_EP5IMR (*(volatile uint32_t*)(&__MBAR[0xB538]))
#define MCF_USB_EP5FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB53C]))
#define MCF_USB_EP5FDR (*(volatile uint32_t*)(&__MBAR[0xB540]))
#define MCF_USB_EP5FSR (*(volatile uint32_t*)(&__MBAR[0xB544]))
#define MCF_USB_EP5FCR (*(volatile uint32_t*)(&__MBAR[0xB548]))
#define MCF_USB_EP5FAR (*(volatile uint32_t*)(&__MBAR[0xB54C]))
#define MCF_USB_EP5FRP (*(volatile uint32_t*)(&__MBAR[0xB550]))
#define MCF_USB_EP5FWP (*(volatile uint32_t*)(&__MBAR[0xB554]))
#define MCF_USB_EP5LRFP (*(volatile uint32_t*)(&__MBAR[0xB558]))
#define MCF_USB_EP5LWFP (*(volatile uint32_t*)(&__MBAR[0xB55C]))
#define MCF_USB_EP6STAT (*(volatile uint32_t*)(&__MBAR[0xB560]))
#define MCF_USB_EP6ISR (*(volatile uint32_t*)(&__MBAR[0xB564]))
#define MCF_USB_EP6IMR (*(volatile uint32_t*)(&__MBAR[0xB568]))
#define MCF_USB_EP6FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB56C]))
#define MCF_USB_EP6FDR (*(volatile uint32_t*)(&__MBAR[0xB570]))
#define MCF_USB_EP6FSR (*(volatile uint32_t*)(&__MBAR[0xB574]))
#define MCF_USB_EP6FCR (*(volatile uint32_t*)(&__MBAR[0xB578]))
#define MCF_USB_EP6FAR (*(volatile uint32_t*)(&__MBAR[0xB57C]))
#define MCF_USB_EP6FRP (*(volatile uint32_t*)(&__MBAR[0xB580]))
#define MCF_USB_EP6FWP (*(volatile uint32_t*)(&__MBAR[0xB584]))
#define MCF_USB_EP6LRFP (*(volatile uint32_t*)(&__MBAR[0xB588]))
#define MCF_USB_EP6LWFP (*(volatile uint32_t*)(&__MBAR[0xB58C]))
#define MCF_USB_IFR(x) (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)]))
#define MCF_USB_EPOUTACR(x) (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTSR(x) (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
#define MCF_USB_EPINACR(x) (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
#define MCF_USB_EPINMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
#define MCF_USB_EPINIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
#define MCF_USB_EPINSR(x) (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
#define MCF_USB_EPINSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
#define MCF_USB_EPSTAT(x) (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)]))
#define MCF_USB_EPISR(x) (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)]))
#define MCF_USB_EPIMR(x) (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)]))
#define MCF_USB_EPFRCFGR(x) (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)]))
#define MCF_USB_EPFDR(x) (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)]))
#define MCF_USB_EPFSR(x) (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)]))
#define MCF_USB_EPFCR(x) (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)]))
#define MCF_USB_EPFAR(x) (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)]))
#define MCF_USB_EPFRP(x) (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)]))
#define MCF_USB_EPFWP(x) (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)]))
#define MCF_USB_EPLRFP(x) (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)]))
#define MCF_USB_EPLWFP(x) (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)]))
/* Bit definitions and macros for MCF_USB_USBAISR */
#define MCF_USB_USBAISR_SETUP (0x1)
#define MCF_USB_USBAISR_IN (0x2)
#define MCF_USB_USBAISR_OUT (0x4)
#define MCF_USB_USBAISR_EPHALT (0x8)
#define MCF_USB_USBAISR_TRANSERR (0x10)
#define MCF_USB_USBAISR_ACK (0x20)
#define MCF_USB_USBAISR_CTROVFL (0x40)
#define MCF_USB_USBAISR_EPSTALL (0x80)
/* Bit definitions and macros for MCF_USB_USBAIMR */
#define MCF_USB_USBAIMR_SETUPEN (0x1)
#define MCF_USB_USBAIMR_INEN (0x2)
#define MCF_USB_USBAIMR_OUTEN (0x4)
#define MCF_USB_USBAIMR_EPHALTEN (0x8)
#define MCF_USB_USBAIMR_TRANSERREN (0x10)
#define MCF_USB_USBAIMR_ACKEN (0x20)
#define MCF_USB_USBAIMR_CTROVFLEN (0x40)
#define MCF_USB_USBAIMR_EPSTALLEN (0x80)
/* Bit definitions and macros for MCF_USB_EPINFO */
#define MCF_USB_EPINFO_EPDIR (0x1)
#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1)
/* Bit definitions and macros for MCF_USB_CFGR */
#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_CFGAR */
#define MCF_USB_CFGAR_RESERVED (0xA0)
#define MCF_USB_CFGAR_RMTWKEUP (0xE0)
/* Bit definitions and macros for MCF_USB_SPEEDR */
#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0)
/* Bit definitions and macros for MCF_USB_FRMNUMR */
#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPTNR */
#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0)
#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2)
#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4)
#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6)
#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8)
#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA)
#define MCF_USB_EPTNR_EPnT1 (0)
#define MCF_USB_EPTNR_EPnT2 (0x1)
#define MCF_USB_EPTNR_EPnT3 (0x2)
/* Bit definitions and macros for MCF_USB_IFUR */
#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0)
#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8)
/* Bit definitions and macros for MCF_USB_IFR */
#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0)
#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8)
/* Bit definitions and macros for MCF_USB_PPCNT */
#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_DPCNT */
#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_CRCECNT */
#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_BSECNT */
#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_PIDECNT */
#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_FRMECNT */
#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_TXPCNT */
#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_CNTOVR */
#define MCF_USB_CNTOVR_PPCNT (0x1)
#define MCF_USB_CNTOVR_DPCNT (0x2)
#define MCF_USB_CNTOVR_CRCECNT (0x4)
#define MCF_USB_CNTOVR_BSECNT (0x8)
#define MCF_USB_CNTOVR_PIDECNT (0x10)
#define MCF_USB_CNTOVR_FRMECNT (0x20)
#define MCF_USB_CNTOVR_TXPCNT (0x40)
/* Bit definitions and macros for MCF_USB_EP0ACR */
#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0)
#define MCF_USB_EP0ACR_TTYPE_CTRL (0)
#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1)
#define MCF_USB_EP0ACR_TTYPE_BULK (0x2)
#define MCF_USB_EP0ACR_TTYPE_INT (0x3)
/* Bit definitions and macros for MCF_USB_EP0MPSR */
#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
/* Bit definitions and macros for MCF_USB_EP0IFR */
#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_EP0SR */
#define MCF_USB_EP0SR_HALT (0x1)
#define MCF_USB_EP0SR_ACTIVE (0x2)
#define MCF_USB_EP0SR_PSTALL (0x4)
#define MCF_USB_EP0SR_CCOMP (0x8)
#define MCF_USB_EP0SR_TXZERO (0x20)
#define MCF_USB_EP0SR_INT (0x80)
/* Bit definitions and macros for MCF_USB_BMRTR */
#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0)
#define MCF_USB_BMRTR_REC_DEVICE (0)
#define MCF_USB_BMRTR_REC_INTERFACE (0x1)
#define MCF_USB_BMRTR_REC_ENDPOINT (0x2)
#define MCF_USB_BMRTR_REC_OTHER (0x3)
#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5)
#define MCF_USB_BMRTR_TYPE_STANDARD (0)
#define MCF_USB_BMRTR_TYPE_CLASS (0x20)
#define MCF_USB_BMRTR_TYPE_VENDOR (0x40)
#define MCF_USB_BMRTR_DIR (0x80)
/* Bit definitions and macros for MCF_USB_BRTR */
#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_WVALUER */
#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_WINDEXR */
#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_WLENGTHR */
#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPOUTACR */
#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0)
#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1)
#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2)
#define MCF_USB_EPOUTACR_TTYPE_INT (0x3)
/* Bit definitions and macros for MCF_USB_EPOUTMPSR */
#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
/* Bit definitions and macros for MCF_USB_EPOUTIFR */
#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_EPOUTSR */
#define MCF_USB_EPOUTSR_HALT (0x1)
#define MCF_USB_EPOUTSR_ACTIVE (0x2)
#define MCF_USB_EPOUTSR_PSTALL (0x4)
#define MCF_USB_EPOUTSR_CCOMP (0x8)
#define MCF_USB_EPOUTSR_TXZERO (0x20)
#define MCF_USB_EPOUTSR_INT (0x80)
/* Bit definitions and macros for MCF_USB_EPOUTSFR */
#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0)
/* Bit definitions and macros for MCF_USB_EPINACR */
#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0)
#define MCF_USB_EPINACR_TTYPE_ISOC (0x1)
#define MCF_USB_EPINACR_TTYPE_BULK (0x2)
#define MCF_USB_EPINACR_TTYPE_INT (0x3)
/* Bit definitions and macros for MCF_USB_EPINMPSR */
#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
/* Bit definitions and macros for MCF_USB_EPINIFR */
#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_EPINSR */
#define MCF_USB_EPINSR_HALT (0x1)
#define MCF_USB_EPINSR_ACTIVE (0x2)
#define MCF_USB_EPINSR_PSTALL (0x4)
#define MCF_USB_EPINSR_CCOMP (0x8)
#define MCF_USB_EPINSR_TXZERO (0x20)
#define MCF_USB_EPINSR_INT (0x80)
/* Bit definitions and macros for MCF_USB_EPINSFR */
#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0)
/* Bit definitions and macros for MCF_USB_USBSR */
#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0)
#define MCF_USB_USBSR_SUSP (0x80)
/* Bit definitions and macros for MCF_USB_USBCR */
#define MCF_USB_USBCR_RESUME (0x1)
#define MCF_USB_USBCR_APPLOCK (0x2)
#define MCF_USB_USBCR_RST (0x4)
#define MCF_USB_USBCR_RAMEN (0x8)
#define MCF_USB_USBCR_RAMSPLIT (0x20)
/* Bit definitions and macros for MCF_USB_DRAMCR */
#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0)
#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10)
#define MCF_USB_DRAMCR_BSY (0x40000000)
#define MCF_USB_DRAMCR_START (0x80000000)
/* Bit definitions and macros for MCF_USB_DRAMDR */
#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_USBISR */
#define MCF_USB_USBISR_ISOERR (0x1)
#define MCF_USB_USBISR_FTUNLCK (0x2)
#define MCF_USB_USBISR_SUSP (0x4)
#define MCF_USB_USBISR_RES (0x8)
#define MCF_USB_USBISR_UPDSOF (0x10)
#define MCF_USB_USBISR_RSTSTOP (0x20)
#define MCF_USB_USBISR_SOF (0x40)
#define MCF_USB_USBISR_MSOF (0x80)
/* Bit definitions and macros for MCF_USB_USBIMR */
#define MCF_USB_USBIMR_ISOERR (0x1)
#define MCF_USB_USBIMR_FTUNLCK (0x2)
#define MCF_USB_USBIMR_SUSP (0x4)
#define MCF_USB_USBIMR_RES (0x8)
#define MCF_USB_USBIMR_UPDSOF (0x10)
#define MCF_USB_USBIMR_RSTSTOP (0x20)
#define MCF_USB_USBIMR_SOF (0x40)
#define MCF_USB_USBIMR_MSOF (0x80)
/* Bit definitions and macros for MCF_USB_EPSTAT */
#define MCF_USB_EPSTAT_RST (0x1)
#define MCF_USB_EPSTAT_FLUSH (0x2)
#define MCF_USB_EPSTAT_DIR (0x80)
#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10)
/* Bit definitions and macros for MCF_USB_EPISR */
#define MCF_USB_EPISR_EOF (0x1)
#define MCF_USB_EPISR_EOT (0x4)
#define MCF_USB_EPISR_FIFOLO (0x10)
#define MCF_USB_EPISR_FIFOHI (0x20)
#define MCF_USB_EPISR_ERR (0x40)
#define MCF_USB_EPISR_EMT (0x80)
#define MCF_USB_EPISR_FU (0x100)
/* Bit definitions and macros for MCF_USB_EPIMR */
#define MCF_USB_EPIMR_EOF (0x1)
#define MCF_USB_EPIMR_EOT (0x4)
#define MCF_USB_EPIMR_FIFOLO (0x10)
#define MCF_USB_EPIMR_FIFOHI (0x20)
#define MCF_USB_EPIMR_ERR (0x40)
#define MCF_USB_EPIMR_EMT (0x80)
#define MCF_USB_EPIMR_FU (0x100)
/* Bit definitions and macros for MCF_USB_EPFRCFGR */
#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0)
#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10)
/* Bit definitions and macros for MCF_USB_EPFDR */
#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPFSR */
#define MCF_USB_EPFSR_EMT (0x10000)
#define MCF_USB_EPFSR_ALRM (0x20000)
#define MCF_USB_EPFSR_FU (0x40000)
#define MCF_USB_EPFSR_FR (0x80000)
#define MCF_USB_EPFSR_OF (0x100000)
#define MCF_USB_EPFSR_UF (0x200000)
#define MCF_USB_EPFSR_RXW (0x400000)
#define MCF_USB_EPFSR_FAE (0x800000)
#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18)
#define MCF_USB_EPFSR_TXW (0x40000000)
#define MCF_USB_EPFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_USB_EPFCR */
#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0)
#define MCF_USB_EPFCR_TXWMSK (0x40000)
#define MCF_USB_EPFCR_OFMSK (0x80000)
#define MCF_USB_EPFCR_UFMSK (0x100000)
#define MCF_USB_EPFCR_RXWMSK (0x200000)
#define MCF_USB_EPFCR_FAEMSK (0x400000)
#define MCF_USB_EPFCR_IPMSK (0x800000)
#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_USB_EPFCR_FRM (0x8000000)
#define MCF_USB_EPFCR_TMR (0x10000000)
#define MCF_USB_EPFCR_WFR (0x20000000)
#define MCF_USB_EPFCR_SHAD (0x80000000)
/* Bit definitions and macros for MCF_USB_EPFAR */
#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPFRP */
#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPFWP */
#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPLRFP */
#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPLWFP */
#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0)
#endif /* __MCF5475_USB_H__ */

101
tos/pci_mem/include/MCF5475_XLB.h Normal file
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@@ -0,0 +1,101 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_XLB_H__
#define __MCF5475_XLB_H__
/*********************************************************************
*
* XL Bus Arbiter (XLB)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_XLB_XARB_CFG (*(volatile uint32_t*)(&_MBAR[0x240]))
#define MCF_XLB_XARB_VER (*(volatile uint32_t*)(&_MBAR[0x244]))
#define MCF_XLB_XARB_SR (*(volatile uint32_t*)(&_MBAR[0x248]))
#define MCF_XLB_XARB_IMR (*(volatile uint32_t*)(&_MBAR[0x24C]))
#define MCF_XLB_XARB_ADRCAP (*(volatile uint32_t*)(&_MBAR[0x250]))
#define MCF_XLB_XARB_SIGCAP (*(volatile uint32_t*)(&_MBAR[0x254]))
#define MCF_XLB_XARB_ADRTO (*(volatile uint32_t*)(&_MBAR[0x258]))
#define MCF_XLB_XARB_DATTO (*(volatile uint32_t*)(&_MBAR[0x25C]))
#define MCF_XLB_XARB_BUSTO (*(volatile uint32_t*)(&_MBAR[0x260]))
#define MCF_XLB_XARB_PRIEN (*(volatile uint32_t*)(&_MBAR[0x264]))
#define MCF_XLB_XARB_PRI (*(volatile uint32_t*)(&_MBAR[0x268]))
/* Bit definitions and macros for MCF_XLB_XARB_CFG */
#define MCF_XLB_XARB_CFG_AT (0x2)
#define MCF_XLB_XARB_CFG_DT (0x4)
#define MCF_XLB_XARB_CFG_BA (0x8)
#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5)
#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8)
#define MCF_XLB_XARB_CFG_PLDIS (0x80000000)
/* Bit definitions and macros for MCF_XLB_XARB_VER */
#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_XLB_XARB_SR */
#define MCF_XLB_XARB_SR_AT (0x1)
#define MCF_XLB_XARB_SR_DT (0x2)
#define MCF_XLB_XARB_SR_BA (0x4)
#define MCF_XLB_XARB_SR_TTM (0x8)
#define MCF_XLB_XARB_SR_ECW (0x10)
#define MCF_XLB_XARB_SR_TTR (0x20)
#define MCF_XLB_XARB_SR_TTA (0x40)
#define MCF_XLB_XARB_SR_MM (0x80)
#define MCF_XLB_XARB_SR_SEA (0x100)
/* Bit definitions and macros for MCF_XLB_XARB_IMR */
#define MCF_XLB_XARB_IMR_ATE (0x1)
#define MCF_XLB_XARB_IMR_DTE (0x2)
#define MCF_XLB_XARB_IMR_BAE (0x4)
#define MCF_XLB_XARB_IMR_TTME (0x8)
#define MCF_XLB_XARB_IMR_ECWE (0x10)
#define MCF_XLB_XARB_IMR_TTRE (0x20)
#define MCF_XLB_XARB_IMR_TTAE (0x40)
#define MCF_XLB_XARB_IMR_MME (0x80)
#define MCF_XLB_XARB_IMR_SEAE (0x100)
/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */
#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */
#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0)
#define MCF_XLB_XARB_SIGCAP_TBST (0x20)
#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7)
/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */
#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0)
/* Bit definitions and macros for MCF_XLB_XARB_DATTO */
#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0)
/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */
#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */
#define MCF_XLB_XARB_PRIEN_M0 (0x1)
#define MCF_XLB_XARB_PRIEN_M2 (0x4)
#define MCF_XLB_XARB_PRIEN_M3 (0x8)
/* Bit definitions and macros for MCF_XLB_XARB_PRI */
#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0)
#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8)
#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC)
#endif /* __MCF5475_XLB_H__ */

47
tos/pci_mem/include/bas_string.h Normal file
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@@ -0,0 +1,47 @@
/*
* bas_string.h
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 26.02.2013
* Author: Markus Fröschle
*/
#ifndef BAS_STRING_H_
#define BAS_STRING_H_
#include <stddef.h>
extern int strncmp(const char *s1, const char *s2, size_t max);
extern char *strcpy(char *dst, const char *src);
char *strncpy(char *dst, const char *src, size_t max);
extern int strcmp(const char *s1, const char *s2);
extern size_t strlen(const char *str);
extern char *strcat(char *dst, const char *src);
extern char *strncat(char *dst, const char *src, size_t max);
extern int atoi(const char *c);
extern void *memcpy(void *dst, const void *src, size_t n);
extern void *memset(void *s, int c, size_t n);
extern int memcmp(const void *s1, const void *s2, size_t max);
extern void bzero(void *s, size_t n);
#define isdigit(c) (((c) >= '0') && ((c) <= '9'))
#define isupper(c) ((c) >= 'A' && ((c) <= 'Z'))
#define islower(c) ((c) >= 'a' && ((c) <= 'z'))
#define isalpha(c) (isupper((c)) || islower(c))
#define tolower(c) (isupper(c) ? ((c) + 'a' - 'A') : (c))
#endif /* BAS_STRING_H_ */

28
tos/pci_test/include/bas_printf.h → tos/pci_mem/include/bas_types.h
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@@ -1,4 +1,8 @@
/*
* bas_types.h
*
* Created on: 17.11.2012
* Author: mfro
*
* This file is part of BaS_gcc.
*
@@ -15,21 +19,17 @@
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2011 - 2012 V. Riviere
* Copyright 2012 M. Froeschle
*
*/
#ifndef _BAS_PRINTF_H_
#define _BAS_PRINTF_H_
#include <stdarg.h>
#include <stddef.h>
#ifndef BAS_TYPES_H_
#define BAS_TYPES_H_
extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va);
extern void xvprintf(const char *fmt, va_list va);
extern void xprintf(const char *fmt, ...);
extern void xsnprintf(char *str, size_t size, const char *fmt, ...);
extern void xputchar(int c);
extern int sprintf(char *str, const char *format, ...);
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h> /* for sizeof() etc. */
extern void display_progress(void);
extern void hexdump(uint8_t buffer[], int size);
#endif /* _BAS_PRINTF_H_ */
#endif /* BAS_TYPES_H_ */

319
tos/pci_mem/include/driver_vec.h Normal file
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@@ -0,0 +1,319 @@
/*
* driver_vec.h
*
* Interface for exposure of BaS drivers to the OS
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 24.10.2013
* Author: Markus Fröschle
*/
#ifndef _DRIVER_VEC_H_
#define _DRIVER_VEC_H_
#include "pci.h"
enum driver_type
{
BLOCKDEV_DRIVER,
CHARDEV_DRIVER,
XHDI_DRIVER,
MCD_DRIVER,
VIDEO_DRIVER,
PCI_DRIVER,
MMU_DRIVER,
PCI_NATIVE_DRIVER,
END_OF_DRIVERS = 0xffffffffL, /* marks end of driver list */
};
struct generic_driver_interface
{
uint32_t (*init)(void);
uint32_t (*read)(void *buf, size_t count);
uint32_t (*write)(const void *buf, size_t count);
uint32_t (*ioctl)(uint32_t request, ...);
};
struct dma_driver_interface
{
int32_t version;
int32_t magic;
int (*dma_set_initiator)(int initiator);
uint32_t (*dma_get_initiator)(int requestor);
void (*dma_free_initiator)(int requestor);
int (*dma_set_channel)(int requestor, void (*handler)(void));
int (*dma_get_channel)(int requestor);
void (*dma_free_channel)(int requestor);
void (*dma_clear_channel)(int channel);
int (*MCD_startDma)(long channel,
int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr,
unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority,
unsigned int flags, unsigned int funcDesc);
int32_t (*MCD_dmaStatus)(int32_t channel);
int32_t (*MCD_XferProgrQuery)(int32_t channel, /* MCD_XferProg */ void *progRep);
int32_t (*MCD_killDma)(int32_t channel);
int32_t (*MCD_continDma)(int32_t channel);
int32_t (*MCD_pauseDma)(int32_t channel);
int32_t (*MCD_resumeDma)(int32_t channel);
int32_t (*MCD_csumQuery)(int32_t channel, uint32_t *csum);
void *(*dma_malloc)(uint32_t amount);
int32_t (*dma_free)(void *addr);
};
struct xhdi_driver_interface
{
uint32_t (*xhdivec)();
};
/*
* Interpretation of offset for color fields: All offsets are from the right,
* inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
* can use the offset as right argument to <<). A pixel afterwards is a bit
* stream and is written to video memory as that unmodified. This implies
* big-endian byte order if bits_per_pixel is greater than 8.
*/
struct fb_bitfield
{
unsigned long offset; /* beginning of bitfield */
unsigned long length; /* length of bitfield */
unsigned long msb_right; /* != 0 : Most significant bit is */
/* right */
};
/*
* the following structures define the interface to the BaS-builtin-framebuffer video driver
*/
struct fb_var_screeninfo
{
unsigned long xres; /* visible resolution */
unsigned long yres;
unsigned long xres_virtual; /* virtual resolution */
unsigned long yres_virtual;
unsigned long xoffset; /* offset from virtual to visible */
unsigned long yoffset; /* resolution */
unsigned long bits_per_pixel; /* guess what */
unsigned long grayscale; /* != 0 Graylevels instead of colors */
struct fb_bitfield red; /* bitfield in fb mem if true color, */
struct fb_bitfield green; /* else only length is significant */
struct fb_bitfield blue;
struct fb_bitfield transp; /* transparency */
unsigned long nonstd; /* != 0 Non standard pixel format */
unsigned long activate; /* see FB_ACTIVATE_* */
unsigned long height; /* height of picture in mm */
unsigned long width; /* width of picture in mm */
unsigned long accel_flags; /* (OBSOLETE) see fb_info.flags */
/* Timing: All values in pixclocks, except pixclock (of course) */
unsigned long pixclock; /* pixel clock in ps (pico seconds) */
unsigned long left_margin; /* time from sync to picture */
unsigned long right_margin; /* time from picture to sync */
unsigned long upper_margin; /* time from sync to picture */
unsigned long lower_margin;
unsigned long hsync_len; /* length of horizontal sync */
unsigned long vsync_len; /* length of vertical sync */
unsigned long sync; /* see FB_SYNC_* */
unsigned long vmode; /* see FB_VMODE_* */
unsigned long rotate; /* angle we rotate counter clockwise */
unsigned long refresh;
unsigned long reserved[4]; /* Reserved for future compatibility */
};
struct fb_fix_screeninfo
{
char id[16]; /* identification string eg "TT Builtin" */
unsigned long smem_start; /* Start of frame buffer mem */
/* (physical address) */
unsigned long smem_len; /* Length of frame buffer mem */
unsigned long type; /* see FB_TYPE_* */
unsigned long type_aux; /* Interleave for interleaved Planes */
unsigned long visual; /* see FB_VISUAL_* */
unsigned short xpanstep; /* zero if no hardware panning */
unsigned short ypanstep; /* zero if no hardware panning */
unsigned short ywrapstep; /* zero if no hardware ywrap */
unsigned long line_length; /* length of a line in bytes */
unsigned long mmio_start; /* Start of Memory Mapped I/O */
/* (physical address) */
unsigned long mmio_len; /* Length of Memory Mapped I/O */
unsigned long accel; /* Indicate to driver which */
/* specific chip/card we have */
unsigned short reserved[3]; /* Reserved for future compatibility */
};
struct fb_chroma
{
unsigned long redx; /* in fraction of 1024 */
unsigned long greenx;
unsigned long bluex;
unsigned long whitex;
unsigned long redy;
unsigned long greeny;
unsigned long bluey;
unsigned long whitey;
};
struct fb_monspecs
{
struct fb_chroma chroma;
struct fb_videomode *modedb; /* mode database */
unsigned char manufacturer[4]; /* Manufacturer */
unsigned char monitor[14]; /* Monitor String */
unsigned char serial_no[14]; /* Serial Number */
unsigned char ascii[14]; /* ? */
unsigned long modedb_len; /* mode database length */
unsigned long model; /* Monitor Model */
unsigned long serial; /* Serial Number - Integer */
unsigned long year; /* Year manufactured */
unsigned long week; /* Week Manufactured */
unsigned long hfmin; /* hfreq lower limit (Hz) */
unsigned long hfmax; /* hfreq upper limit (Hz) */
unsigned long dclkmin; /* pixelclock lower limit (Hz) */
unsigned long dclkmax; /* pixelclock upper limit (Hz) */
unsigned short input; /* display type - see FB_DISP_* */
unsigned short dpms; /* DPMS support - see FB_DPMS_ */
unsigned short signal; /* Signal Type - see FB_SIGNAL_* */
unsigned short vfmin; /* vfreq lower limit (Hz) */
unsigned short vfmax; /* vfreq upper limit (Hz) */
unsigned short gamma; /* Gamma - in fractions of 100 */
unsigned short gtf : 1; /* supports GTF */
unsigned short misc; /* Misc flags - see FB_MISC_* */
unsigned char version; /* EDID version... */
unsigned char revision; /* ...and revision */
unsigned char max_x; /* Maximum horizontal size (cm) */
unsigned char max_y; /* Maximum vertical size (cm) */
};
struct framebuffer_driver_interface
{
struct fb_info **framebuffer_info; /* pointer to an fb_info struct (defined in include/fb.h) */
};
struct pci_bios_interface
{
uint32_t subjar;
uint32_t version;
/* Although we declare this functions as standard gcc functions (cdecl),
* they expect parameters inside registers (fastcall) unsupported by gcc m68k.
* Caller will take care of parameters passing convention.
*/
int32_t (*find_pci_device)(uint32_t id, uint16_t index);
int32_t (*find_pci_classcode)(uint32_t class, uint16_t index);
int32_t (*read_config_byte)(int32_t handle, uint16_t reg, uint8_t *address);
int32_t (*read_config_word)(int32_t handle, uint16_t reg, uint16_t *address);
int32_t (*read_config_longword)(int32_t handle, uint16_t reg, uint32_t *address);
uint8_t (*fast_read_config_byte)(int32_t handle, uint16_t reg);
uint16_t (*fast_read_config_word)(int32_t handle, uint16_t reg);
uint32_t (*fast_read_config_longword)(int32_t handle, uint16_t reg);
int32_t (*write_config_byte)(int32_t handle, uint16_t reg, uint16_t val);
int32_t (*write_config_word)(int32_t handle, uint16_t reg, uint16_t val);
int32_t (*write_config_longword)(int32_t handle, uint16_t reg, uint32_t val);
int32_t (*hook_interrupt)(int32_t handle, uint32_t *routine, uint32_t *parameter);
int32_t (*unhook_interrupt)(int32_t handle);
int32_t (*special_cycle)(uint16_t bus, uint32_t data);
int32_t (*get_routing)(int32_t handle);
int32_t (*set_interrupt)(int32_t handle);
int32_t (*get_resource)(int32_t handle);
int32_t (*get_card_used)(int32_t handle, uint32_t *address);
int32_t (*set_card_used)(int32_t handle, uint32_t *callback);
int32_t (*read_mem_byte)(int32_t handle, uint32_t offset, uint8_t *address);
int32_t (*read_mem_word)(int32_t handle, uint32_t offset, uint16_t *address);
int32_t (*read_mem_longword)(int32_t handle, uint32_t offset, uint32_t *address);
uint8_t (*fast_read_mem_byte)(int32_t handle, uint32_t offset);
uint16_t (*fast_read_mem_word)(int32_t handle, uint32_t offset);
uint32_t (*fast_read_mem_longword)(int32_t handle, uint32_t offset);
int32_t (*write_mem_byte)(int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_mem_word)(int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_mem_longword)(int32_t handle, uint32_t offset, uint32_t val);
int32_t (*read_io_byte)(int32_t handle, uint32_t offset, uint8_t *address);
int32_t (*read_io_word)(int32_t handle, uint32_t offset, uint16_t *address);
int32_t (*read_io_longword)(int32_t handle, uint32_t offset, uint32_t *address);
uint8_t (*fast_read_io_byte)(int32_t handle, uint32_t offset);
uint16_t (*fast_read_io_word)(int32_t handle, uint32_t offset);
uint32_t (*fast_read_io_longword)(int32_t handle, uint32_t offset);
int32_t (*write_io_byte)(int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_io_word)(int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_io_longword)(int32_t handle, uint32_t offset, uint32_t val);
int32_t (*get_machine_id)(void);
int32_t (*get_pagesize)(void);
int32_t (*virt_to_bus)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*bus_to_virt)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*virt_to_phys)(uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*phys_to_virt)(uint32_t address, PCI_CONV_ADR *pointer);
// int32_t reserved[2];
};
struct mmu_driver_interface
{
int32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
int32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
int32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
uint32_t (*report_pagesize)(void);
};
struct pci_native_driver_interface
{
uint32_t (*pci_read_config_longword)(int32_t handle, int offset);
uint16_t (*pci_read_config_word)(int32_t handle, int offset);
uint8_t (*pci_read_config_byte)(int32_t handle, int offset);
int32_t (*pci_write_config_longword)(int32_t handle, int offset, uint32_t value);
int32_t (*pci_write_config_word)(int32_t handle, int offset, uint16_t value);
int32_t (*pci_write_config_byte)(int32_t handle, int offset, uint8_t value);
int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter);
int32_t (*pci_unhook_interrupt)(int32_t handle);
int32_t (*pci_find_device)(uint16_t device_id, uint16_t vendor_id, int index);
int32_t (*pci_find_classcode)(uint32_t classcode, int index);
struct pci_rd * (*pci_get_resource)(int32_t handle);
};
union interface
{
struct generic_driver_interface *gdi;
struct xhdi_driver_interface *xhdi;
struct dma_driver_interface *dma;
struct framebuffer_driver_interface *fb;
struct pci_bios_interface *pci;
struct mmu_driver_interface *mmu;
struct pci_native_driver_interface *pci_native;
};
struct generic_interface
{
enum driver_type type;
char name[16];
char description[64];
int version;
int revision;
union interface interface;
};
struct driver_table
{
uint32_t bas_version;
uint32_t bas_revision;
void (*remove_handler)(void); /* calling this will disable the BaS' hook into trap #0 */
struct generic_interface *interfaces;
};
#endif /* _DRIVER_VEC_H_ */

360
tos/pci_mem/include/pci.h Normal file
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@@ -0,0 +1,360 @@
#ifndef _PCI_H_
#define _PCI_H_
/*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 26.02.2013
* Author: Markus Fröschle
*/
#include <bas_types.h>
#include "util.h" /* for swpX() */
#define PCI_MEMORY_OFFSET 0x80000000
#define PCI_MEMORY_SIZE 0x40000000 /* 1 GByte PCI memory window */
#define PCI_IO_OFFSET 0xD0000000
#define PCI_IO_SIZE 0x10000000 /* 256 MByte PCI I/O window */
#define PCI_LANESWAP_B(x) (x ^ 3)
#define PCI_LANESWAP_W(x) (x ^ 2)
#define PCI_LANESWAP_L(x) (x) /* for completeness only */
/*
* Note: the byte offsets are in little endian format, so for pci_xxx_config_byte()
* accesses to hit the right offset, you'll need to wrap them into PCI_LANESWAP_B()
* and for pci_xxx_config_word() into PCI_LANESWAP_W()
*/
#define PCIIDR 0x00 /* PCI Configuration ID Register */
#define PCICSR 0x04 /* PCI Command/Status Register */
#define PCICR 0x06 /* PCI Command Register */
#define PCISR 0x04 /* PCI Status Register */
#define PCIREV 0x0B /* PCI Revision ID Register */
#define PCICCR 0x08 /* PCI Class Code Register */
#define PCICLSR 0x0F /* PCI Cache Line Size Register */
#define PCILTR 0x0E /* PCI Latency Timer Register */
#define PCIHTR 0x0D /* PCI Header Type Register */
#define PCIBISTR 0x0C /* PCI Build-In Self Test Register */
#define PCIBAR0 0x10 /* PCI Base Address Register for Memory
Accesses to Local, Runtime, and DMA */
#define PCIBAR1 0x14 /* PCI Base Address Register for I/O
Accesses to Local, Runtime, and DMA */
#define PCIBAR2 0x18 /* PCI Base Address Register for Memory
Accesses to Local Address Space 0 */
#define PCIBAR3 0x1C /* PCI Base Address Register for Memory
Accesses to Local Address Space 1 */
#define PCIBAR4 0x20 /* PCI Base Address Register, reserved */
#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */
#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/
#define PCISVID 0x2E /* PCI Subsystem Vendor ID */
#define PCISID 0x2D /* PCI Subsystem ID */
#define PCIERBAR 0x30 /* PCI Expansion ROM Base Register */
#define CAP_PTR 0x34 /* New Capability Pointer */
#define PCIILR 0x3F /* PCI Interrupt Line Register */
#define PCIIPR 0x3E /* PCI Interrupt Pin Register */
#define PCIMGR 0x3D /* PCI Min_Gnt Register */
#define PCIMLR 0x3C /* PCI Max_Lat Register */
#define PMCAPID 0x40 /* Power Management Capability ID */
#define PMNEXT 0x41 /* Power Management Next Capability
Pointer */
#define PMC 0x42 /* Power Management Capabilities */
#define PMCSR 0x44 /* Power Management Control/Status */
#define PMCSR_BSE 0x46 /* PMCSR Bridge Support Extensions */
#define PMDATA 0x47 /* Power Management Data */
#define HS_CNTL 0x48 /* Hot Swap Control */
#define HS_NEXT 0x49 /* Hot Swap Next Capability Pointer */
#define HS_CSR 0x4A /* Hot Swap Control/Status */
#define PVPDCNTL 0x4C /* PCI Vital Product Data Control */
#define PVPD_NEXT 0x4D /* PCI Vital Product Data Next
Capability Pointer */
#define PVPDAD 0x4E /* PCI Vital Product Data Address */
#define PVPDATA 0x50 /* PCI VPD Data */
/*
* bit definitions for PCICSR lower half (Command Register)
*/
#define PCICR_IO (1 << 0) /* if set: device responds to I/O space accesses */
#define PCICR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */
#define PCICR_MASTER (1 << 2) /* if set: device is master */
#define PCICR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */
#define PCICR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */
#define PCICR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */
#define PCICR_PERR (1 << 6) /* if set: reacts to parity errors */
#define PCICR_STEPPING (1 << 7) /* if set: stepping enabled */
#define PCICR_SERR (1 << 8) /* if set: SERR pin enabled */
#define PCICR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
#define PCICR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */
/*
* bit definitions for PCICSR upper half (Status Register)
*/
#define PCISR_INTERRUPT (1 << 3) /* device requested interrupt */
#define PCISR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */
#define PCISR_66MHZ (1 << 5) /* 66 MHz capable */
#define PCISR_UDF (1 << 6) /* UDF supported */
#define PCISR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
#define PCISR_DPARITY_ERROR (1 << 8) /* data parity error detected */
#define PCISR_T_ABORT_S (1 << 11) /* target abort signaled */
#define PCISR_T_ABORT_R (1 << 12) /* target abort received */
#define PCISR_M_ABORT_R (1 << 13) /* master abort received */
#define PCISR_S_ERROR_S (1 << 14) /* system error signaled */
#define PCISR_PARITY_ERR (1 << 15) /* data parity error */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x1B /* Primary bus number */
#define PCI_SECONDARY_BUS 0x1A /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x19 /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x18 /* Latency timer for secondary interface */
#define PCI_IO_BASE 0x1C /* I/O range behind the bridge */
#define PCI_IO_LIMIT 0x1D
#define PCI_SEC_STATUS 0x1C /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT 0x26
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32 0x2C
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16 0x32
#define PCI_BRIDGE_CONTROL 0x3E /* Bridge Control */
struct pci_rd /* structure of resource descriptor */
{
unsigned short next; /* length of the following structure */
unsigned short flags; /* type of resource and misc. flags */
unsigned long start; /* start-address of resource */
unsigned long length; /* length of resource */
unsigned long offset; /* offset PCI to phys. CPU Address */
unsigned long dmaoffset; /* offset for DMA-transfers */
};
typedef struct /* structure of address conversion */
{
unsigned long adr; /* calculated address (CPU<->PCI) */
unsigned long len; /* length of memory range */
} PCI_CONV_ADR;
/******************************************************************************/
/* PCI-BIOS Error Codes */
/******************************************************************************/
#define PCI_SUCCESSFUL 0 /* everything's fine */
#define PCI_FUNC_NOT_SUPPORTED -2 /* function not supported */
#define PCI_BAD_VENDOR_ID -3 /* wrong Vendor ID */
#define PCI_DEVICE_NOT_FOUND -4 /* PCI-Device not found */
#define PCI_BAD_REGISTER_NUMBER -5 /* wrong register number */
#define PCI_SET_FAILED -6 /* reserved for later use */
#define PCI_BUFFER_TOO_SMALL -7 /* reserved for later use */
#define PCI_GENERAL_ERROR -8 /* general BIOS error code */
#define PCI_BAD_HANDLE -9 /* wrong/unknown PCI-handle */
/******************************************************************************/
/* Flags used in Resource-Descriptor */
/******************************************************************************/
#define FLG_IO 0x4000 /* Ressource in IO range */
#define FLG_ROM 0x2000 /* Expansion ROM */
#define FLG_LAST 0x8000 /* last ressource */
#define FLG_8BIT 0x0100 /* 8 bit accesses allowed */
#define FLG_16BIT 0x0200 /* 16 bit accesses allowed */
#define FLG_32BIT 0x0400 /* 32 bit accesses allowed */
#define FLG_ENDMASK 0x000F /* mask for byte ordering */
/******************************************************************************/
/* Values used in FLG_ENDMASK for Byte Ordering */
/******************************************************************************/
#define ORD_MOTOROLA 0 /* Motorola (big endian) */
#define ORD_INTEL_AS 1 /* Intel (little endian), addr.swapped */
#define ORD_INTEL_LS 2 /* Intel (little endian), lane swapped */
#define ORD_UNKNOWN 15 /* unknown (BIOS-calls allowed only) */
/******************************************************************************/
/* Status Info used in Device-Descriptor */
/******************************************************************************/
#define DEVICE_FREE 0 /* Device is not used */
#define DEVICE_USED 1 /* Device is used by another driver */
#define DEVICE_CALLBACK 2 /* used, but driver can be cancelled */
#define DEVICE_AVAILABLE 3 /* used, not available */
#define NO_DEVICE -1 /* no device detected */
/* PCI configuration space macros */
/* register 0x00 macros */
#define PCI_DEVICE_ID(i) (uint16_t)(((i) & 0xffff0000) >> 16)
#define PCI_VENDOR_ID(i) (uint16_t) ((i) & 0xffff)
/* register 0x04 macros */
#define PCI_STATUS(i) ((i) & 0xffff)
#define PCI_COMMAND(i) (((i) >> 16) & 0xffff)
/* register 0x08 macros */
#define PCI_CLASS_CODE(i) (((i) & 0xff000000) >> 24)
#define PCI_SUBCLASS(i) (((i) & 0x00ff0000) >> 16)
#define PCI_PROG_IF(i) (((i) & 0x0000ff00) >> 8)
#define PCI_REVISION_ID(i) (((i) & 0x000000ff))
/* register 0x0c macros */
#define PCI_BIST(i) (((i) & 0xff000000) >> 24)
#define PCI_HEADER_TYPE(i) (((i) & 0x00ff0000) >> 16)
#define PCI_LAT_TIMER(i) (((i) & 0x0000ff00) >> 8)
#define PCI_CACHELINE_SIZE(i) (((i) & 0x000000ff))
/* register 0x2c macros */
#define PCI_SUBSYS_ID(i) ((i) & 0xffff0000) >> 16)
#define PCI_SUBSYS_VID(i) ((i) & 0xffff))
/* register 0x34 macros */
#define PCI_CAPABILITIES(i) ((i) & 0xff)
/* register 0x3c macros */
#define PCI_MAX_LATENCY(i) (((i) & 0xff000000) >> 24)
#define PCI_MIN_GRANT(i) (((i) & 0xff0000) >> 16)
#define PCI_INTERRUPT_PIN(i) (((i) & 0xff00) >> 8)
#define PCI_INTERRUPT_LINE(i) (((i)) & 0xff)
#define IS_PCI_MEM_BAR(i) ((i) & 1) == 0
#define IS_PCI_IO_BAR(i) ((i) & 1) == 1
#define PCI_MEMBAR_TYPE(i) (((i) & 0x6) >> 1)
#define PCI_IOBAR_ADR(i) (((i) & 0xfffffffc))
#define PCI_MEMBAR_ADR(i) (((i) & 0xfffffff0))
extern void init_eport(void);
extern void init_xlbus_arbiter(void);
extern void init_pci(void);
extern int pci_handle2index(int32_t handle);
extern int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index);
extern int32_t pci_find_classcode(uint32_t classcode, int index);
extern int32_t pci_get_interrupt_cause(void);
extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data);
/*
* match bits for pci_find_classcode()
*/
#define PCI_FIND_BASE_CLASS (1 << 26)
#define PCI_FIND_SUB_CLASS (1 << 25)
#define PCI_FIND_PROG_IF (1 << 24)
extern uint32_t pci_read_config_longword(int32_t handle, int offset);
extern uint16_t pci_read_config_word(int32_t handle, int offset);
extern uint8_t pci_read_config_byte(int32_t handle, int offset);
extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value);
extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value);
extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value);
typedef int (*pci_interrupt_handler)(int param);
extern int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter);
extern int32_t pci_unhook_interrupt(int32_t handle);
extern struct pci_rd *pci_get_resource(int32_t handle);
/*
* Not implemented PCI_BIOS functions
*/
extern uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg);
extern uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg);
extern uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg);
extern int32_t pci_special_cycle(uint16_t bus, uint32_t data);
extern int32_t pci_get_routing(int32_t handle);
extern int32_t pci_set_interrupt(int32_t handle);
extern int32_t pci_get_card_used(int32_t handle, uint32_t *address);
extern int32_t pci_set_card_used(int32_t handle, uint32_t *callback);
extern int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset);
extern uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset);
extern uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset);
extern int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset);
extern uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset);
extern uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset);
extern int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t pci_get_machine_id(void);
extern int32_t pci_get_pagesize(void);
extern int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
/*
* prototypes for PCI wrapper routines
*/
extern int32_t wrapper_find_pci_device(uint32_t id, uint16_t index);
extern int32_t wrapper_find_pci_classcode(uint32_t class, uint16_t index);
extern int32_t wrapper_read_config_byte(int32_t handle, uint16_t reg, uint8_t *address);
extern int32_t wrapper_read_config_word(int32_t handle, uint16_t reg, uint16_t *address);
extern int32_t wrapper_read_config_longword(int32_t handle, uint16_t reg, uint32_t *address);
extern uint8_t wrapper_fast_read_config_byte(int32_t handle, uint16_t reg);
extern uint16_t wrapper_fast_read_config_word(int32_t handle, uint16_t reg);
extern uint32_t wrapper_fast_read_config_longword(int32_t handle, uint16_t reg);
extern int32_t wrapper_write_config_byte(int32_t handle, uint16_t reg, uint16_t val);
extern int32_t wrapper_write_config_word(int32_t handle, uint16_t reg, uint16_t val);
extern int32_t wrapper_write_config_longword(int32_t handle, uint16_t reg, uint32_t val);
extern int32_t wrapper_hook_interrupt(int32_t handle, uint32_t *routine, uint32_t *parameter);
extern int32_t wrapper_unhook_interrupt(int32_t handle);
extern int32_t wrapper_special_cycle(uint16_t bus, uint32_t data);
extern int32_t wrapper_get_routing(int32_t handle);
extern int32_t wrapper_set_interrupt(int32_t handle);
extern int32_t wrapper_get_resource(int32_t handle);
extern int32_t wrapper_get_card_used(int32_t handle, uint32_t *address);
extern int32_t wrapper_set_card_used(int32_t handle, uint32_t *callback);
extern int32_t wrapper_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t wrapper_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t wrapper_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t wrapper_fast_read_mem_byte(int32_t handle, uint32_t offset);
extern uint16_t wrapper_fast_read_mem_word(int32_t handle, uint32_t offset);
extern uint32_t wrapper_fast_read_mem_longword(int32_t handle, uint32_t offset);
extern int32_t wrapper_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t wrapper_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t wrapper_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t wrapper_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t wrapper_fast_read_io_byte(int32_t handle, uint32_t offset);
extern uint16_t wrapper_fast_read_io_word(int32_t handle, uint32_t offset);
extern uint32_t wrapper_fast_read_io_longword(int32_t handle, uint32_t offset);
extern int32_t wrapper_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t wrapper_get_machine_id(void);
extern int32_t wrapper_get_pagesize(void);
extern int32_t wrapper_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \
((bus) << 16) | \
((device << 8) | \
(function))
#define PCI_HANDLE(bus, slot, function) (0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
#define PCI_BUS_FROM_HANDLE(h) (((h) & 0xff00) >> 10)
#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3)
#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7))
extern void pci_dump_registers(int32_t handle);
#endif /* _PCI_H_ */

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/*
* util.h
*
* Byteswapping macros lend from EmuTOS sources
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 27.10.2013
* Author: mfro
*/
#ifndef UTIL_H_
#define UTIL_H_
#include <bas_types.h>
#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
/*
* uint16_t swpw(uint16_t val);
* swap endianess of val, 16 bits only.
*/
static inline uint16_t swpw(uint16_t w)
{
return (w << 8) | (w >> 8);
}
/*
* uint32_t swpl(uint32_t val);
* swap endianess of val, 32 bits only.
* e.g. ABCD => DCBA
*/
static inline uint32_t swpl(uint32_t l)
{
return ((l & 0xff000000) >> 24) | ((l & 0x00ff0000) >> 8) |
((l & 0x0000ff00) << 8) | (l << 24);
}
/*
* WORD swpw2(ULONG val);
* swap endianness of val, treated as two 16-bit words.
* e.g. ABCD => BADC
*/
#define swpw2(a) \
__extension__ \
({unsigned long _tmp; \
__asm__ __volatile__ \
("move.b (%1),%0\n\t" \
"move.b 1(%1),(%1)\n\t" \
"move.b %0,1(%1)\n\t" \
"move.b 2(%1),%0\n\t" \
"move.b 3(%1),2(%1)\n\t" \
"move.b %0,3(%1)" \
: "=d"(_tmp) /* outputs */ \
: "a"(&a) /* inputs */ \
: "cc", "memory" /* clobbered */ \
); \
})
/*
* WORD set_sr(WORD new);
* sets sr to the new value, and return the old sr value
*/
#define set_sr(a) \
__extension__ \
({short _r, _a = (a); \
__asm__ __volatile__ \
("move.w sr,%0\n\t" \
"move.w %1,sr" \
: "=&d"(_r) /* outputs */ \
: "nd"(_a) /* inputs */ \
: "cc", "memory" /* clobbered */ \
); \
_r; \
})
/*
* WORD get_sr(void);
* returns the current value of sr.
*/
#define get_sr() \
__extension__ \
({short _r; \
__asm__ volatile \
("move.w sr,%0" \
: "=dm"(_r) /* outputs */ \
: /* inputs */ \
: "cc", "memory" /* clobbered */ \
); \
_r; \
})
/*
* void regsafe_call(void *addr)
* Saves all registers to the stack, calls the function
* that addr points to, and restores the registers afterwards.
*/
#define regsafe_call(addr) \
__extension__ \
({__asm__ volatile ("lea -60(sp),sp\n\t" \
"movem.l d0-d7/a0-a6,(sp)"); \
((void (*) (void)) addr)(); \
__asm__ volatile ("movem.l (sp),d0-d7/a0-a6\n\t" \
"lea 60(sp),sp"); \
})
#endif /* UTIL_H_ */

1
tos/pci_mem/pci_mem.config Normal file
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// ADD PREDEFINED MACROS HERE!

1
tos/pci_mem/pci_mem.creator Normal file
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[General]

6
tos/pci_mem/pci_mem.files Normal file
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include/driver_vec.h
Makefile
sources/bas_printf.c
sources/bas_string.c
sources/printf_helper.S
sources/pci_mem.c

2
tos/pci_mem/pci_mem.includes Normal file
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include
/usr/m68k-atari-mint/include

181
tos/pci_mem/sources/pci_mem.c Normal file
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#include <stdio.h>
#include <string.h>
#include <mint/osbind.h>
#include <stdint.h>
#include <stdbool.h>
#include "MCF5475.h"
#include "driver_vec.h"
#include "pci.h"
#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
#define SYSCLK 132000
int i;
void add_mem(struct pci_native_driver_interface *pci)
{
int32_t handle;
int16_t index = 0;
#define PCI_READ_CONFIG_LONGWORD(a, b) (*pci->pci_read_config_longword)(a, b)
#define PCI_WRITE_CONFIG_LONGWORD(a, b) (*pci->pci_write_config_longword)(a, b)
#define PCI_FIND_DEVICE(a, b, c) (*pci->pci_find_device)(a, b, c)
#define PCI_GET_RESOURCE(a) (*pci->pci_get_resource)(a)
printf("find ATI graphics card\r\n");
handle = PCI_FIND_DEVICE(0x5159, 0x1002, index);
if (handle > 0)
{
struct pci_rd *rd;
printf("ATI device with handle 0x%02x found\r\n", handle);
rd = PCI_GET_RESOURCE(handle); /* get resource descriptor for ATI graphics card */
printf("rd=%p\r\n", rd);
printf("start=%lx, length=%lx, flags=%x\r\n", rd->start, rd->length, rd->flags);
if (rd != NULL)
{
if (rd->start != 0L && rd->length > 0x04000000 &&
!(rd->flags & FLG_IO) && !(rd->flags & FLG_ROM))
{
int32_t err;
if ((err = Maddalt(0x04000000 /* rd->start + 0x7C000000UL */, rd->length)) > 0)
{
printf("%ld MBytes of additional memory added to system at %p\r\n",
rd->length / 1024 / 1024, 0x04000000 /* rd->start + 0x7C000000 */);
return;
}
else
{
fprintf(stderr, "Maddalt() returned error code %ld\r\n", err);
exit(1);
}
}
}
else
{
fprintf(stderr, "no resource descriptor for handle 0x%02x found", handle);
exit(1);
}
}
else
{
fprintf(stderr, "no ATI graphics card found\r\n");
exit(1);
}
}
/*
* temporarily replace the trap 0 handler with this so we can avoid
* getting caught by BaS versions that don't understand the driver interface
* exposure call.
* If we get here, we have a BaS version that doesn't support the trap 0 interface
*/
static void __attribute__((interrupt)) trap0_catcher(void)
{
__asm__ __volatile__(
" clr.l d0 \n\t" // return 0 to indicate not supported
:
:
:
);
}
struct driver_table *get_bas_drivers(void)
{
struct driver_table *ret = NULL;
void *old_vector;
old_vector = Setexc(0x20, trap0_catcher); /* set our own temporarily */
__asm__ __volatile__(
" bra.s do_trap \n\t"
" .dc.l 0x5f424153 \n\t" // '_BAS'
"do_trap: trap #0 \n\t"
" move.l d0,%[ret] \n\t"
: [ret] "=m" (ret) /* output */
: /* no inputs */
: /* clobbered */
);
(void) Setexc(0x20, old_vector); /* restore original vector */
return ret;
}
void pci_mem(void)
{
struct driver_table *bas_drivers;
struct generic_interface *ifc;
bool pci_driver_found = false;
struct pci_native_driver_interface *pci_driver = NULL;
bas_drivers = get_bas_drivers();
/*
* trap0_catcher should return 0L on failure, for some reason FireTOS
* returns -1L on a trap #0. Anyway, ...
*/
if (bas_drivers != NULL && bas_drivers != (void *) -1L)
{
printf("BaS driver vector: %p\r\n", bas_drivers);
printf("BaS version: %ld.%02ld\r\n", (long) bas_drivers->bas_version, (long) bas_drivers->bas_revision);
}
else
{
printf("BaS driver retrieval not supported\r\n");
printf("(old BaS version or FireTOS?)\r\n");
exit(1);
}
ifc = bas_drivers->interfaces;
do {
struct generic_interface *pci_driver_interface = NULL;
printf("interface type: %ld\r\n", (long) ifc[i].type);
printf("interface version: %ld.%02ld\r\n", (long) ifc[i].version, (long) ifc[i].revision);
printf("interface name: %s\r\n", ifc[i].name);
printf("interface description: %s\r\n", ifc[i].description);
if (ifc[i].type == PCI_NATIVE_DRIVER)
{
pci_driver_found = true;
if (!pci_driver_interface || (ifc[i].version > pci_driver_interface->version ||
(ifc[i].version == pci_driver_interface->version && ifc[i].revision > pci_driver_interface->revision)))
{
/*
* either no PCI driver interface found yet or with lower version or with lower version and higher revision
*
* replace it
*/
pci_driver = ifc[i].interface.pci_native;
pci_driver_interface = &ifc[i];
printf("PCI native driver interface v%d.%02d found\r\n", pci_driver_interface->version, pci_driver_interface->revision);
printf("replaced old with newer driver version\r\n");
}
}
} while (ifc[++i].type != END_OF_DRIVERS);
if (pci_driver_found)
{
add_mem(pci_driver);
}
}
int main(int argc, char *argv[])
{
printf("PCI Memory Adder\r\n");
printf("\xbd 2016 M. Fr\x94schle\r\n");
Supexec(pci_mem);
return 0; /* just to make the compiler happy, we will never return */
}

5
tos/pci_test/Makefile
View File

@@ -50,10 +50,9 @@ INCDIR=include
INCLUDE+=-I$(INCDIR)
CSRCS=\
$(SRCDIR)/pci_test.c \
$(SRCDIR)/bas_printf.c
$(SRCDIR)/pci_test.c
ASRCS=$(SRCDIR)/printf_helper.S
ASRCS=
COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))

35
tos/pci_test/include/bas_types.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* bas_types.h
*
* Created on: 17.11.2012
* Author: mfro
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2011 - 2012 V. Riviere
* Copyright 2012 M. Froeschle
*
*/
#ifndef BAS_TYPES_H_
#define BAS_TYPES_H_
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h> /* for sizeof() etc. */
#endif /* BAS_TYPES_H_ */

228
tos/pci_test/include/pci.h
View File

@@ -21,26 +21,33 @@
* Author: Markus Fröschle
*/
#include <bas_types.h>
#include "util.h" /* for swpX() */
#define PCI_MEMORY_OFFSET 0x80000000
#define PCI_MEMORY_SIZE 0x40000000 /* 1 GByte PCI memory window */
#define PCI_IO_OFFSET 0xD0000000
#define PCI_IO_SIZE 0x10000000 /* 128 MByte PCI I/O window */
#define PCI_IO_SIZE 0x10000000 /* 256 MByte PCI I/O window */
#define PCI_LANESWAP_B(x) (x ^ 3)
#define PCI_LANESWAP_W(x) (x ^ 2)
#define PCI_LANESWAP_L(x) (x) /* for completeness only */
/*
* Note: the byte offsets are in little endian format, so you can't use them
* on byteswapped (Motorola format) values!
* Note: the byte offsets are in little endian format, so for pci_xxx_config_byte()
* accesses to hit the right offset, you'll need to wrap them into PCI_LANESWAP_B()
* and for pci_xxx_config_word() into PCI_LANESWAP_W()
*/
#define PCIIDR 0x00 /* PCI Configuration ID Register */
#define PCICSR 0x04 /* PCI Command/Status Register */
#define PCICR 0x04 /* PCI Command Register */
#define PCISR 0x06 /* PCI Status Register */
#define PCIREV 0x08 /* PCI Revision ID Register */
#define PCICCR 0x0B /* PCI Class Code Register */
#define PCICLSR 0x0C /* PCI Cache Line Size Register */
#define PCILTR 0x0D /* PCI Latency Timer Register */
#define PCIHTR 0x0E /* PCI Header Type Register */
#define PCIBISTR 0x0F /* PCI Build-In Self Test Register */
#define PCICR 0x06 /* PCI Command Register */
#define PCISR 0x04 /* PCI Status Register */
#define PCIREV 0x0B /* PCI Revision ID Register */
#define PCICCR 0x08 /* PCI Class Code Register */
#define PCICLSR 0x0F /* PCI Cache Line Size Register */
#define PCILTR 0x0E /* PCI Latency Timer Register */
#define PCIHTR 0x0D /* PCI Header Type Register */
#define PCIBISTR 0x0C /* PCI Build-In Self Test Register */
#define PCIBAR0 0x10 /* PCI Base Address Register for Memory
Accesses to Local, Runtime, and DMA */
#define PCIBAR1 0x14 /* PCI Base Address Register for I/O
@@ -53,13 +60,13 @@
#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */
#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/
#define PCISVID 0x2E /* PCI Subsystem Vendor ID */
#define PCISID 0x2E /* PCI Subsystem ID */
#define PCISID 0x2D /* PCI Subsystem ID */
#define PCIERBAR 0x30 /* PCI Expansion ROM Base Register */
#define CAP_PTR 0x34 /* New Capability Pointer */
#define PCIILR 0x3C /* PCI Interrupt Line Register */
#define PCIIPR 0x3D /* PCI Interrupt Pin Register */
#define PCIMGR 0x3E /* PCI Min_Gnt Register */
#define PCIMLR 0x3F /* PCI Max_Lat Register */
#define PCIILR 0x3F /* PCI Interrupt Line Register */
#define PCIIPR 0x3E /* PCI Interrupt Pin Register */
#define PCIMGR 0x3D /* PCI Min_Gnt Register */
#define PCIMLR 0x3C /* PCI Max_Lat Register */
#define PMCAPID 0x40 /* Power Management Capability ID */
#define PMNEXT 0x41 /* Power Management Next Capability
Pointer */
@@ -79,41 +86,41 @@
/*
* bit definitions for PCICSR lower half (Command Register)
*/
#define PCICSR_IO (1 << 0) /* if set: device responds to I/O space accesses */
#define PCICSR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */
#define PCICSR_MASTER (1 << 2) /* if set: device is master */
#define PCICSR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */
#define PCICSR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */
#define PCICSR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */
#define PCICSR_PERR (1 << 6) /* if set: reacts to parity errors */
#define PCICSR_STEPPING (1 << 7) /* if set: stepping enabled */
#define PCICSR_SERR (1 << 8) /* if set: SERR pin enabled */
#define PCICSR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
#define PCICSR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */
#define PCICR_IO (1 << 0) /* if set: device responds to I/O space accesses */
#define PCICR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */
#define PCICR_MASTER (1 << 2) /* if set: device is master */
#define PCICR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */
#define PCICR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */
#define PCICR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */
#define PCICR_PERR (1 << 6) /* if set: reacts to parity errors */
#define PCICR_STEPPING (1 << 7) /* if set: stepping enabled */
#define PCICR_SERR (1 << 8) /* if set: SERR pin enabled */
#define PCICR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
#define PCICR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */
/*
* bit definitions for PCICSR upper half (Status Register)
*/
#define PCICSR_INTERRUPT (1 << 3) /* device requested interrupt */
#define PCICSR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */
#define PCICSR_66MHZ (1 << 5) /* 66 MHz capable */
#define PCICSR_UDF (1 << 6) /* UDF supported */
#define PCICSR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
#define PCICSR_DPARITY_ERROR (1 << 8) /* data parity error detected */
#define PCISR_INTERRUPT (1 << 3) /* device requested interrupt */
#define PCISR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */
#define PCISR_66MHZ (1 << 5) /* 66 MHz capable */
#define PCISR_UDF (1 << 6) /* UDF supported */
#define PCISR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
#define PCISR_DPARITY_ERROR (1 << 8) /* data parity error detected */
#define PCICSR_T_ABORT_S (1 << 11) /* target abort signaled */
#define PCICSR_T_ABORT_R (1 << 12) /* target abort received */
#define PCICSR_M_ABORT_R (1 << 13) /* master abort received */
#define PCICSR_S_ERROR_S (1 << 14) /* system error signaled */
#define PCICSR_PARITY_ERR (1 << 15) /* data parity error */
#define PCISR_T_ABORT_S (1 << 11) /* target abort signaled */
#define PCISR_T_ABORT_R (1 << 12) /* target abort received */
#define PCISR_M_ABORT_R (1 << 13) /* master abort received */
#define PCISR_S_ERROR_S (1 << 14) /* system error signaled */
#define PCISR_PARITY_ERR (1 << 15) /* data parity error */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x1A /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x1B /* Latency timer for secondary interface */
#define PCI_PRIMARY_BUS 0x1B /* Primary bus number */
#define PCI_SECONDARY_BUS 0x1A /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x19 /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x18 /* Latency timer for secondary interface */
#define PCI_IO_BASE 0x1C /* I/O range behind the bridge */
#define PCI_IO_LIMIT 0x1D
#define PCI_SEC_STATUS 0x1E /* Secondary status register, only bit 14 used */
#define PCI_SEC_STATUS 0x1C /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
@@ -184,28 +191,28 @@ typedef struct /* structure of address conversion */
/* PCI configuration space macros */
/* register 0x00 macros */
#define PCI_VENDOR_ID(i) swpw((uint16_t)(((i) & 0xffff0000) >> 16))
#define PCI_DEVICE_ID(i) swpw((uint16_t) ((i) & 0xffff))
#define PCI_DEVICE_ID(i) (uint16_t)(((i) & 0xffff0000) >> 16)
#define PCI_VENDOR_ID(i) (uint16_t) ((i) & 0xffff)
/* register 0x04 macros */
#define PCI_STATUS(i) ((i) & 0xffff)
#define PCI_COMMAND(i) (((i) >> 16) & 0xffff)
/* register 0x08 macros */
#define PCI_CLASS_CODE(i) ((swpl((i)) & 0xff000000) >> 24)
#define PCI_SUBCLASS(i) ((swpl((i)) & 0xffff0000) >> 16)
#define PCI_PROG_IF(i) ((swpl((i)) & 0x0000ff00) >> 8)
#define PCI_REVISION_ID(i) ((swpl((i)) & 0x000000ff))
#define PCI_CLASS_CODE(i) (((i) & 0xff000000) >> 24)
#define PCI_SUBCLASS(i) (((i) & 0x00ff0000) >> 16)
#define PCI_PROG_IF(i) (((i) & 0x0000ff00) >> 8)
#define PCI_REVISION_ID(i) (((i) & 0x000000ff))
/* register 0x0c macros */
#define PCI_BIST(i) ((swpl((i)) & 0xff000000) >> 24)
#define PCI_HEADER_TYPE(i) ((swpl((i)) & 0x00ff0000) >> 16)
#define PCI_LAT_TIMER(i) ((swpl((i)) & 0x0000ff00) >> 8)
#define PCI_CACHELINE_SIZE(i) ((swpl((i)) & 0x000000ff))
#define PCI_BIST(i) (((i) & 0xff000000) >> 24)
#define PCI_HEADER_TYPE(i) (((i) & 0x00ff0000) >> 16)
#define PCI_LAT_TIMER(i) (((i) & 0x0000ff00) >> 8)
#define PCI_CACHELINE_SIZE(i) (((i) & 0x000000ff))
/* register 0x2c macros */
#define PCI_SUBSYS_ID(i) (((i) & 0xffff0000) >> 16)
#define PCI_SUBSYS_VID(i) (((i) & 0xffff))
#define PCI_SUBSYS_ID(i) ((i) & 0xffff0000) >> 16)
#define PCI_SUBSYS_VID(i) ((i) & 0xffff))
/* register 0x34 macros */
#define PCI_CAPABILITIES(i) ((i) & 0xff)
@@ -222,6 +229,17 @@ typedef struct /* structure of address conversion */
#define PCI_IOBAR_ADR(i) (((i) & 0xfffffffc))
#define PCI_MEMBAR_ADR(i) (((i) & 0xfffffff0))
extern void init_eport(void);
extern void init_xlbus_arbiter(void);
extern void init_pci(void);
extern int pci_handle2index(int32_t handle);
extern int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index);
extern int32_t pci_find_classcode(uint32_t classcode, int index);
extern int32_t pci_get_interrupt_cause(void);
extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data);
/*
* match bits for pci_find_classcode()
*/
@@ -229,6 +247,104 @@ typedef struct /* structure of address conversion */
#define PCI_FIND_SUB_CLASS (1 << 25)
#define PCI_FIND_PROG_IF (1 << 24)
extern uint32_t pci_read_config_longword(int32_t handle, int offset);
extern uint16_t pci_read_config_word(int32_t handle, int offset);
extern uint8_t pci_read_config_byte(int32_t handle, int offset);
extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value);
extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value);
extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value);
typedef int (*pci_interrupt_handler)(int param);
extern int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter);
extern int32_t pci_unhook_interrupt(int32_t handle);
extern struct pci_rd *pci_get_resource(int32_t handle);
/*
* Not implemented PCI_BIOS functions
*/
extern uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg);
extern uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg);
extern uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg);
extern int32_t pci_special_cycle(uint16_t bus, uint32_t data);
extern int32_t pci_get_routing(int32_t handle);
extern int32_t pci_set_interrupt(int32_t handle);
extern int32_t pci_get_card_used(int32_t handle, uint32_t *address);
extern int32_t pci_set_card_used(int32_t handle, uint32_t *callback);
extern int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset);
extern uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset);
extern uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset);
extern int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset);
extern uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset);
extern uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset);
extern int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t pci_get_machine_id(void);
extern int32_t pci_get_pagesize(void);
extern int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
/*
* prototypes for PCI wrapper routines
*/
extern int32_t wrapper_find_pci_device(uint32_t id, uint16_t index);
extern int32_t wrapper_find_pci_classcode(uint32_t class, uint16_t index);
extern int32_t wrapper_read_config_byte(int32_t handle, uint16_t reg, uint8_t *address);
extern int32_t wrapper_read_config_word(int32_t handle, uint16_t reg, uint16_t *address);
extern int32_t wrapper_read_config_longword(int32_t handle, uint16_t reg, uint32_t *address);
extern uint8_t wrapper_fast_read_config_byte(int32_t handle, uint16_t reg);
extern uint16_t wrapper_fast_read_config_word(int32_t handle, uint16_t reg);
extern uint32_t wrapper_fast_read_config_longword(int32_t handle, uint16_t reg);
extern int32_t wrapper_write_config_byte(int32_t handle, uint16_t reg, uint16_t val);
extern int32_t wrapper_write_config_word(int32_t handle, uint16_t reg, uint16_t val);
extern int32_t wrapper_write_config_longword(int32_t handle, uint16_t reg, uint32_t val);
extern int32_t wrapper_hook_interrupt(int32_t handle, uint32_t *routine, uint32_t *parameter);
extern int32_t wrapper_unhook_interrupt(int32_t handle);
extern int32_t wrapper_special_cycle(uint16_t bus, uint32_t data);
extern int32_t wrapper_get_routing(int32_t handle);
extern int32_t wrapper_set_interrupt(int32_t handle);
extern int32_t wrapper_get_resource(int32_t handle);
extern int32_t wrapper_get_card_used(int32_t handle, uint32_t *address);
extern int32_t wrapper_set_card_used(int32_t handle, uint32_t *callback);
extern int32_t wrapper_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t wrapper_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t wrapper_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t wrapper_fast_read_mem_byte(int32_t handle, uint32_t offset);
extern uint16_t wrapper_fast_read_mem_word(int32_t handle, uint32_t offset);
extern uint32_t wrapper_fast_read_mem_longword(int32_t handle, uint32_t offset);
extern int32_t wrapper_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t wrapper_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t wrapper_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t wrapper_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t wrapper_fast_read_io_byte(int32_t handle, uint32_t offset);
extern uint16_t wrapper_fast_read_io_word(int32_t handle, uint32_t offset);
extern uint32_t wrapper_fast_read_io_longword(int32_t handle, uint32_t offset);
extern int32_t wrapper_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t wrapper_get_machine_id(void);
extern int32_t wrapper_get_pagesize(void);
extern int32_t wrapper_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \
((bus) << 16) | \
((device << 8) | \
@@ -239,4 +355,6 @@ typedef struct /* structure of address conversion */
#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3)
#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7))
extern void pci_dump_registers(int32_t handle);
#endif /* _PCI_H_ */

128
tos/pci_test/include/util.h Normal file
View File

@@ -0,0 +1,128 @@
/*
* util.h
*
* Byteswapping macros lend from EmuTOS sources
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 27.10.2013
* Author: mfro
*/
#ifndef UTIL_H_
#define UTIL_H_
#include <bas_types.h>
#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
/*
* uint16_t swpw(uint16_t val);
* swap endianess of val, 16 bits only.
*/
static inline uint16_t swpw(uint16_t w)
{
return (w << 8) | (w >> 8);
}
/*
* uint32_t swpl(uint32_t val);
* swap endianess of val, 32 bits only.
* e.g. ABCD => DCBA
*/
static inline uint32_t swpl(uint32_t l)
{
return ((l & 0xff000000) >> 24) | ((l & 0x00ff0000) >> 8) |
((l & 0x0000ff00) << 8) | (l << 24);
}
/*
* WORD swpw2(ULONG val);
* swap endianness of val, treated as two 16-bit words.
* e.g. ABCD => BADC
*/
#define swpw2(a) \
__extension__ \
({unsigned long _tmp; \
__asm__ __volatile__ \
("move.b (%1),%0\n\t" \
"move.b 1(%1),(%1)\n\t" \
"move.b %0,1(%1)\n\t" \
"move.b 2(%1),%0\n\t" \
"move.b 3(%1),2(%1)\n\t" \
"move.b %0,3(%1)" \
: "=d"(_tmp) /* outputs */ \
: "a"(&a) /* inputs */ \
: "cc", "memory" /* clobbered */ \
); \
})
/*
* WORD set_sr(WORD new);
* sets sr to the new value, and return the old sr value
*/
#define set_sr(a) \
__extension__ \
({short _r, _a = (a); \
__asm__ __volatile__ \
("move.w sr,%0\n\t" \
"move.w %1,sr" \
: "=&d"(_r) /* outputs */ \
: "nd"(_a) /* inputs */ \
: "cc", "memory" /* clobbered */ \
); \
_r; \
})
/*
* WORD get_sr(void);
* returns the current value of sr.
*/
#define get_sr() \
__extension__ \
({short _r; \
__asm__ volatile \
("move.w sr,%0" \
: "=dm"(_r) /* outputs */ \
: /* inputs */ \
: "cc", "memory" /* clobbered */ \
); \
_r; \
})
/*
* void regsafe_call(void *addr)
* Saves all registers to the stack, calls the function
* that addr points to, and restores the registers afterwards.
*/
#define regsafe_call(addr) \
__extension__ \
({__asm__ volatile ("lea -60(sp),sp\n\t" \
"movem.l d0-d7/a0-a6,(sp)"); \
((void (*) (void)) addr)(); \
__asm__ volatile ("movem.l (sp),d0-d7/a0-a6\n\t" \
"lea 60(sp),sp"); \
})
#endif /* UTIL_H_ */

456
tos/pci_test/sources/bas_printf.c
View File

@@ -1,456 +0,0 @@
/*
* tc.printf.c: A public-domain, minimal printf/sprintf routine that prints
* through the putchar() routine. Feel free to use for
* anything... -- 7/17/87 Paul Placeway
*/
/*-
* Copyright (c) 1980, 1991 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <stdarg.h>
#include "MCF5475.h"
#include "bas_printf.h"
#include "bas_string.h"
/*
* Lexical definitions.
*
* All lexical space is allocated dynamically.
* The eighth/sixteenth bit of characters is used to prevent recognition,
* and eventually stripped.
*/
#define META 0200
#define ASCII 0177
#define QUOTE ((char) 0200) /* Eighth char bit used for 'ing */
#define TRIM 0177 /* Mask to strip quote bit */
#define UNDER 0000000 /* No extra bits to do both */
#define BOLD 0000000 /* Bold flag */
#define STANDOUT META /* Standout flag */
#define LITERAL 0000000 /* Literal character flag */
#define ATTRIBUTES 0200 /* The bits used for attributes */
#define CHAR 0000177 /* Mask to mask out the character */
#define INF 32766 /* should be bigger than any field to print */
static char snil[] = "(nil)";
void xputchar(int c)
{
__asm__ __volatile__
(
".extern printf_helper\n\t"
"move.b %0,d0\n\t"
"bsr printf_helper\n\t"
/* output */:
/* input */: "r" (c)
/* clobber */: "d0","d2","a0","memory"
);
}
static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap)
{
char buf[128];
char *bp;
const char *f;
float flt;
long l;
unsigned long u;
int i;
int fmt;
unsigned char pad = ' ';
int flush_left = 0;
int f_width = 0;
int prec = INF;
int hash = 0;
int do_long = 0;
int sign = 0;
int attributes = 0;
f = sfmt;
for (; *f; f++)
{
if (*f != '%')
{
/* then just out the char */
(*addchar)((int) (((unsigned char) *f) | attributes));
}
else
{
f++; /* skip the % */
if (*f == '-')
{ /* minus: flush left */
flush_left = 1;
f++;
}
if (*f == '0' || *f == '.')
{
/* padding with 0 rather than blank */
pad = '0';
f++;
}
if (*f == '*')
{
/* field width */
f_width = va_arg(ap, int);
f++;
}
else if (isdigit((unsigned char)*f))
{
f_width = atoi(f);
while (isdigit((unsigned char)*f))
f++; /* skip the digits */
}
if (*f == '.')
{ /* precision */
f++;
if (*f == '*')
{
prec = va_arg(ap, int);
f++;
}
else if (isdigit((unsigned char)*f))
{
prec = atoi(f);
while (isdigit((unsigned char)*f))
f++; /* skip the digits */
}
}
if (*f == '#')
{ /* alternate form */
hash = 1;
f++;
}
if (*f == 'l')
{ /* long format */
do_long++;
f++;
if (*f == 'l')
{
do_long++;
f++;
}
}
fmt = (unsigned char) *f;
if (fmt != 'S' && fmt != 'Q' && isupper(fmt))
{
do_long = 1;
fmt = tolower(fmt);
}
bp = buf;
switch (fmt)
{ /* do the format */
case 'd':
switch (do_long)
{
case 0:
l = (long) (va_arg(ap, int));
break;
case 1:
default:
l = va_arg(ap, long);
break;
}
if (l < 0)
{
sign = 1;
l = -l;
}
do
{
*bp++ = (char) (l % 10) + '0';
} while ((l /= 10) > 0);
if (sign)
*bp++ = '-';
f_width = f_width - (int) (bp - buf);
if (!flush_left)
while (f_width-- > 0)
(*addchar)((int) (pad | attributes));
for (bp--; bp >= buf; bp--)
(*addchar)((int) (((unsigned char) *bp) | attributes));
if (flush_left)
while (f_width-- > 0)
(*addchar)((int) (' ' | attributes));
break;
case 'f':
/* this is actually more than stupid, but does work for now */
flt = (float) (va_arg(ap, double)); /* beware: va_arg() extends float to double! */
if (flt < 0)
{
sign = 1;
flt = -flt;
}
{
int quotient, remainder;
quotient = (int) flt;
remainder = (flt - quotient) * 10E5;
for (i = 0; i < 6; i++)
{
*bp++ = (char) (remainder % 10) + '0';
remainder /= 10;
}
*bp++ = '.';
do
{
*bp++ = (char) (quotient % 10) + '0';
} while ((quotient /= 10) > 0);
if (sign)
*bp++ = '-';
f_width = f_width - (int) (bp - buf);
if (!flush_left)
while (f_width-- > 0)
(*addchar)((int) (pad | attributes));
for (bp--; bp >= buf; bp--)
(*addchar)((int) (((unsigned char) *bp) | attributes));
if (flush_left)
while (f_width-- > 0)
(*addchar)((int) (' ' | attributes));
}
break;
case 'p':
do_long = 1;
hash = 1;
fmt = 'x';
/* no break */
case 'o':
case 'x':
case 'u':
switch (do_long)
{
case 0:
u = (unsigned long) (va_arg(ap, unsigned int));
break;
case 1:
default:
u = va_arg(ap, unsigned long);
break;
}
if (fmt == 'u')
{ /* unsigned decimal */
do
{
*bp++ = (char) (u % 10) + '0';
} while ((u /= 10) > 0);
}
else if (fmt == 'o')
{ /* octal */
do
{
*bp++ = (char) (u % 8) + '0';
} while ((u /= 8) > 0);
if (hash)
*bp++ = '0';
}
else if (fmt == 'x')
{ /* hex */
do
{
i = (int) (u % 16);
if (i < 10)
*bp++ = i + '0';
else
*bp++ = i - 10 + 'a';
} while ((u /= 16) > 0);
if (hash)
{
*bp++ = 'x';
*bp++ = '0';
}
}
i = f_width - (int) (bp - buf);
if (!flush_left)
while (i-- > 0)
(*addchar)((int) (pad | attributes));
for (bp--; bp >= buf; bp--)
(*addchar)((int) (((unsigned char) *bp) | attributes));
if (flush_left)
while (i-- > 0)
(*addchar)((int) (' ' | attributes));
break;
case 'c':
i = va_arg(ap, int);
(*addchar)((int) (i | attributes));
break;
case 'S':
case 'Q':
case 's':
case 'q':
bp = va_arg(ap, char *);
if (!bp)
bp = snil;
f_width = f_width - strlen((char *) bp);
if (!flush_left)
while (f_width-- > 0)
(*addchar)((int) (pad | attributes));
for (i = 0; *bp && i < prec; i++)
{
if (fmt == 'q' && (*bp & QUOTE))
(*addchar)((int) ('\\' | attributes));
(*addchar)(
(int) (((unsigned char) *bp & TRIM) | attributes));
bp++;
}
if (flush_left)
while (f_width-- > 0)
(*addchar)((int) (' ' | attributes));
break;
case 'a':
attributes = va_arg(ap, int);
break;
case '%':
(*addchar)((int) ('%' | attributes));
break;
default:
break;
}
flush_left = 0, f_width = 0, prec = INF, hash = 0, do_long = 0;
sign = 0;
pad = ' ';
}
}
}
static char *xstring, *xestring;
void xaddchar(int c)
{
if (xestring == xstring)
*xstring = '\0';
else
*xstring++ = (char) c;
}
int sprintf(char *str, const char *format, ...)
{
va_list va;
va_start(va, format);
xstring = str;
doprnt(xaddchar, format, va);
va_end(va);
*xstring++ = '\0';
return 0;
}
void xsnprintf(char *str, size_t size, const char *fmt, ...)
{
va_list va;
va_start(va, fmt);
xstring = str;
xestring = str + size - 1;
doprnt(xaddchar, fmt, va);
va_end(va);
*xstring++ = '\0';
}
void xprintf(const char *fmt, ...)
{
va_list va;
va_start(va, fmt);
doprnt(xputchar, fmt, va);
va_end(va);
}
void xvprintf(const char *fmt, va_list va)
{
doprnt(xputchar, fmt, va);
}
void xvsnprintf(char *str, size_t size, const char *fmt, va_list va)
{
xstring = str;
xestring = str + size - 1;
doprnt(xaddchar, fmt, va);
*xstring++ = '\0';
}
void display_progress()
{
static int _progress_index;
char progress_char[] = "|/-\\";
xputchar(progress_char[_progress_index++ % strlen(progress_char)]);
xputchar('\r');
}
void hexdump(uint8_t buffer[], int size)
{
int i;
int line = 0;
uint8_t *bp = buffer;
while (bp < buffer + size) {
uint8_t *lbp = bp;
xprintf("%08x ", line);
for (i = 0; i < 16; i++) {
if (bp + i > buffer + size) {
break;
}
xprintf("%02x ", (uint8_t) *lbp++);
}
lbp = bp;
for (i = 0; i < 16; i++) {
int8_t c = *lbp++;
if (bp + i > buffer + size) {
break;
}
if (c > ' ' && c < '~') {
xprintf("%c", c);
} else {
xprintf(".");
}
}
xprintf("\r\n");
bp += 16;
line += 16;
}
}

156
tos/pci_test/sources/bas_string.c
View File

@@ -1,156 +0,0 @@
/*
* bas_string.c
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 26.02.2013
* Author: Markus Fröschle
*/
#include "bas_types.h"
#include <stdint.h>
#include "bas_string.h"
void *memcpy(void *dst, const void *src, size_t n)
{
uint8_t *to = dst;
while (to < (uint8_t *) dst + n)
*to++ = * (uint8_t *) src++;
return dst;
}
void bzero(void *s, size_t n)
{
size_t i;
for (i = 0; i < n; i++)
((unsigned char *) s)[i] = '\0';
}
void *memset(void *s, int c, size_t n)
{
uint8_t *dst = s;
do
{
*dst++ = c;
} while ((dst - (uint8_t *) s) < n);
return s;
}
int memcmp(const void *s1, const void *s2, size_t max)
{
int i;
int cmp;
for (i = 0; i < max; i++)
{
cmp = (* (const char *) s1 - * (const char *) s2);
if (cmp != 0) return cmp;
}
return cmp;
}
int strcmp(const char *s1, const char *s2)
{
int i;
int cmp;
for (i = 0; *s1++ && *s2++; i++)
{
cmp = (*s1 - *s2);
if (cmp != 0) return cmp;
}
return cmp;
}
int strncmp(const char *s1, const char *s2, size_t max)
{
int i;
int cmp;
for (i = 0; i < max && *s1++ && *s2++; i++);
{
cmp = (*s1 - *s2);
if (cmp != 0) return cmp;
}
return cmp;
}
char *strcpy(char *dst, const char *src)
{
char *ptr = dst;
while ((*dst++ = *src++) != '\0');
return ptr;
}
char *strncpy(char *dst, const char *src, size_t max)
{
char *ptr = dst;
while ((*dst++ = *src++) != '\0' && max-- >= 0);
return ptr;
}
int atoi(const char *c)
{
int value = 0;
while (isdigit(*c))
{
value *= 10;
value += (int) (*c - '0');
c++;
}
return value;
}
size_t strlen(const char *s)
{
const char *start = s;
while (*s++);
return s - start - 1;
}
char *strcat(char *dst, const char *src)
{
char *ret = dst;
dst = &dst[strlen(dst)];
while ((*dst++ = *src++) != '\0');
return ret;
}
char *strncat(char *dst, const char *src, size_t max)
{
size_t i;
char *ret = dst;
dst = &dst[strlen(dst)];
for (i = 0; i < max && *src; i++)
{
*dst++ = *src++;
}
*dst++ = '\0';
return ret;
}

159
tos/pci_test/sources/pci_test.c
View File

@@ -1,9 +1,9 @@
#include <stdio.h>
#include <string.h>
#include <mint/osbind.h>
#include <stdint.h>
#include <stdbool.h>
#include "bas_printf.h"
#include "MCF5475.h"
#include "driver_vec.h"
#include "pci.h"
@@ -15,17 +15,97 @@
volatile int32_t time, start, end;
int i;
#define swpw(a) ((a) >> 8 | (a) << 8)
/*
* PCI device class descriptions displayed during PCI bus scan
*/
static struct pci_class
{
int classcode;
char *description;
} pci_classes[] =
{
{ 0x00, "device was built prior definition of the class code field" },
{ 0x01, "Mass Storage Controller" },
{ 0x02, "Network Controller" },
{ 0x03, "Display Controller" },
{ 0x04, "Multimedia Controller" },
{ 0x05, "Memory Controller" },
{ 0x06, "Bridge Device" },
{ 0x07, "Simple Communication Controller" },
{ 0x08, "Base System Peripherial" },
{ 0x09, "Input Device" },
{ 0x0a, "Docking Station" },
{ 0x0b, "Processor" },
{ 0x0c, "Serial Bus Controller" },
{ 0x0d, "Wireless Controller" },
{ 0x0e, "Intelligent I/O Controller" },
{ 0x0f, "Satellite Communication Controller" },
{ 0x10, "Encryption/Decryption Controller" },
{ 0x11, "Data Acquisition and Signal Processing Controller" },
{ 0xff, "Device does not fit any defined class" },
};
static int num_pci_classes = sizeof(pci_classes) / sizeof(struct pci_class);
/*
* retrieve device class (in cleartext) for a PCI classcode
*/
static char *device_class(int classcode)
{
int i;
for (i = 0; i < num_pci_classes; i++)
{
if (pci_classes[i].classcode == classcode)
{
return pci_classes[i].description;
}
}
return "unknown device class";
}
void hexdump(uint8_t buffer[], int size)
{
int i;
int line = 0;
uint8_t *bp = buffer;
while (bp < buffer + size) {
uint8_t *lbp = bp;
printf("%08lx ", (uintptr_t) buffer + line);
for (i = 0; i < 16; i++) {
if (bp + i > buffer + size) {
break;
}
printf("%02x ", (uint8_t) *lbp++);
}
lbp = bp;
for (i = 0; i < 16; i++) {
int8_t c = *lbp++;
if (bp + i > buffer + size) {
break;
}
if (c > ' ' && c < '~') {
printf("%c", c);
} else {
printf(".");
}
}
printf("\r\n");
bp += 16;
line += 16;
}
}
void do_tests(struct pci_native_driver_interface *pci)
{
#define PCI_READ_CONFIG_LONGWORD(a, b) pci->pci_read_config_longword(a, b)
#define PCI_WRITE_CONFIG_LONGWORD(a, b) pci->pci_write_config_longword(a, b)
start = MCF_SLT0_SCNT;
hexdump((uint8_t *) 0, 64);
end = MCF_SLT0_SCNT;
time = (start - end) / (SYSCLK / 1000) / 1000;
printf("enumerate PCI devices\r\n");
@@ -42,20 +122,69 @@ void do_tests(struct pci_native_driver_interface *pci)
{
uint32_t value;
value = (*pci->pci_read_config_longword)(handle, PCIIDR);
value = swpl((*pci->pci_read_config_longword)(handle, PCIIDR));
printf(" %02x | %02x | %02x |%04x|%04x|%04x| (0x%02x)\r\n",
(char) PCI_BUS_FROM_HANDLE(handle),
(char) PCI_DEVICE_FROM_HANDLE(handle),
(char) PCI_FUNCTION_FROM_HANDLE(handle),
(short) PCI_VENDOR_ID(value), (short) PCI_DEVICE_ID(value),
(unsigned char) handle,
(char) (*pci->pci_read_config_byte)(handle, PCICCR));
printf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x, 0x%04x)\r\n",
PCI_BUS_FROM_HANDLE(handle),
PCI_DEVICE_FROM_HANDLE(handle),
PCI_FUNCTION_FROM_HANDLE(handle),
PCI_VENDOR_ID(value), PCI_DEVICE_ID(value),
handle,
device_class((*pci->pci_read_config_byte)(handle, PCI_LANESWAP_B(PCICCR))),
(*pci->pci_read_config_byte)(handle, PCI_LANESWAP_B(PCICCR)),
(*pci->pci_read_config_word)(handle, PCI_LANESWAP_W(PCICCR)));
handle = (*pci->pci_find_device)(0x0, 0xFFFF, ++index);
}
struct pci_rd *rd;
int flags;
handle = 0xa0;
rd = (*pci->pci_get_resource)(handle); /* get resource descriptor for ATI graphics card */
if (rd != NULL)
{
do
{
flags = rd->flags;
printf("Start address: 0x%08lx\r\n", rd->start);
printf("Length: 0x%08lx\r\n", rd->length);
printf("Offset: 0x%08lx\r\n", rd->offset);
printf("DMA offset: 0x%08lx\r\n", rd->dmaoffset);
printf("FLAGS: %s%s%s%s%s%s%s\r\n",
flags & FLG_IO ? "FLG_IO, " : "",
flags & FLG_ROM ? "FLG_ROM, " : "",
flags & FLG_8BIT ? "FLG_8BIT, " : "",
flags & FLG_16BIT ? "FLG_16BIT, " : "",
flags & FLG_32BIT ? "FLG_32BIT, " : "",
(flags & FLG_ENDMASK) == ORD_MOTOROLA ? "ORD_MOTOROLA" :
(flags & FLG_ENDMASK) == ORD_INTEL_AS ? "ORD_INTEL_AS" :
(flags & FLG_ENDMASK) == ORD_INTEL_LS ? "ORD_INTEL_LS" :
(flags & FLG_ENDMASK) == ORD_UNKNOWN ? "ORD_UNKNOWN" :
"", "");
printf("\r\n");
if (rd->start != 0L)
{
hexdump((uint8_t *) rd->start + rd->offset, 128);
memset((uint8_t *) rd-> start + rd->offset, 0, 128);
printf("memory cleared\r\n");
hexdump((uint8_t *) rd->start + rd->offset, 128);
}
rd = (struct pci_rd *) (((uintptr_t) rd) + (uintptr_t) rd->next);
} while (!(flags & FLG_LAST));
}
else
{
printf("resource descriptor for handle 0x%02x not found\r\n", handle);
}
printf("\r\n...finished\r\n");
printf("finished (took %f seconds).\r\n", time / 1000.0);
}
/*

10
usb/usb.c
View File

@@ -54,14 +54,8 @@
#include "usb.h"
#include "usb_hub.h"
#define DEBUG_USB
#ifdef DEBUG_USB
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DEBUG_USB */
#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0)
#define info(format, arg...) do { xprintf("INFO: %s(): " format, __FUNCTION__, ##arg); } while (0)
#define DEBUG
#include "debug.h"
struct hci
{

25
video/fbmem.c
View File

@@ -148,25 +148,14 @@ int fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
*/
struct fb_info *framebuffer_alloc(unsigned long size)
{
struct fb_info *info = driver_mem_alloc(sizeof(struct fb_info));
/* changed for BaS_gcc:
* we do not allocate anything here anymore, info_fb is statically allocated in video.c
* This leads to the (not really existing) limitation that we only support one Radeon
* card in the system
*/
extern struct fb_info *info_fb;
if (info == NULL)
{
dbg("%s: could not allocate fb_info structure\r\n", __FUNCTION__);
return 0;
}
memset(info, 0, sizeof(struct fb_info));
if (size)
{
char *p = driver_mem_alloc(size);
if (!p)
return NULL;
memset(p, 0, size);
info->par = p;
}
return info;
return info_fb;
}
/**

34
video/video.c
View File

@@ -7,13 +7,8 @@
#include "fb.h"
#include "radeonfb.h"
#define DBG_VIDEO
#ifdef DBG_VIDEO
#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
#else
#define dbg(format, arg...) do {;} while (0)
#endif /* DBG_VIDEO */
#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0)
// #define DEBUG
#include "debug.h"
#ifdef _USE_VIDEL_
#define MON_ALL -1 /* code used in VMODE_ENTRY for match on mode only */
@@ -277,7 +272,13 @@ void videl_screen_init(void)
#endif /* _USE_VIDEL_ */
static struct fb_info fb;
static struct radeonfb_info rfb;
static struct fb_info fb =
{
.par = &rfb
};
struct fb_info *info_fb = &fb;
const char monitor_layout[1024] = "CRT,CRT";
@@ -345,18 +346,15 @@ void video_init(void)
dbg("matched\r\n");
xprintf("not registering RADEON card\r\n");
xprintf("registering RADEON card with PCI handle 0x%02x\r\n", handle);
if (0)
if (radeonfb_pci_register(handle, board) >= 0)
{
if (radeonfb_pci_register(handle, board) >= 0)
{
xprintf("RADEON video card found and registered\r\n");
}
else
{
dbg("failed to register RADEON PCI video card\r\n");
}
xprintf("RADEON video card found and registered\r\n");
}
else
{
dbg("failed to register RADEON PCI video card\r\n");
}
return;
}

66
x86emu/x86biosemu.c
View File

@@ -10,6 +10,7 @@
#include "pci_ids.h"
#include "x86pcibios.h"
#define DEBUG
#include "debug.h"
#define USE_SDRAM
@@ -42,7 +43,7 @@ typedef struct
struct rom_header
{
uint16_t signature;
uint16_t signature;
uint8_t size;
uint8_t init[3];
uint8_t reserved[0x12];
@@ -63,7 +64,7 @@ struct pci_data
uint16_t irevision;
uint8_t type;
uint8_t indicator;
uint16_t reserved_2;
uint16_t reserved_2;
};
static struct radeonfb_info *rinfo_biosemu;
@@ -72,8 +73,6 @@ uint32_t offset_mem;
static uint32_t offset_io;
static uint32_t config_address_reg;
extern int x86_pcibios_emulator();
//X86EMU_sysEnv _X86EMU_env;
/* general software interrupt handler */
@@ -102,46 +101,42 @@ int run_bios_int(struct X86EMU *emu, int num)
return 1;
}
uint8_t inb(uint16_t port)
static uint8_t inb(struct X86EMU *emu, uint16_t port)
{
uint8_t val = 0;
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
val = * (uint8_t *) (offset_io + (uint32_t) port);
//dbg("%s: inb(0x%x) = 0x%x\r\n", __FUNCTION__, port, val);
}
return val;
}
uint16_t inw(uint16_t port)
uint16_t inw(struct X86EMU *emu, uint16_t port)
{
uint16_t val = 0;
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
val = swpw(*(uint16_t *)(offset_io + (uint32_t) port));
//dbg("inw(0x%x) = 0x%x\r\n", port, val);
}
return val;
}
uint32_t inl(uint16_t port)
uint32_t inl(struct X86EMU *emu, uint16_t port)
{
uint32_t val = 0;
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
val = swpl(*(uint32_t *)(offset_io + (uint32_t) port));
//dbg("0x%x) = 0x%x\r\n", port, val);
}
else if (port == 0xCF8)
{
val = config_address_reg;
dbg("inl(0x%x) = 0x%x\r\n", port, val);
}
else if ((port == 0xCFC) && ((config_address_reg & 0x80000000) != 0))
{
dbg("%s: PCI BIOS access to register %x\r\n", __FUNCTION__, config_address_reg);
dbg("PCI BIOS access to register %x\r\n", config_address_reg);
switch (config_address_reg & 0xFC)
{
case PCIIDR:
@@ -161,34 +156,30 @@ uint32_t inl(uint16_t port)
return val;
}
void outb(uint8_t val, uint16_t port)
void outb(struct X86EMU *emu, uint16_t port, uint8_t val)
{
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
//dbg("outb(0x%x, 0x%x)\r\n", port, val);
*(uint8_t *)(offset_io + (uint32_t) port) = val;
}
}
void outw(uint16_t val, uint16_t port)
void outw(struct X86EMU *emu, uint16_t port, uint16_t val)
{
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
//dbg("outw(0x%x, 0x%x)\r\n", port, val);
*(uint16_t *)(offset_io + (uint32_t) port) = swpw(val);
}
}
void outl(uint32_t val, uint16_t port)
void outl(struct X86EMU *emu, uint16_t port, uint32_t val)
{
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
//dbg("outl(0x%x, 0x%x)\r\n", port, val);
*(uint32_t *)(offset_io + (uint32_t) port) = swpl(val);
}
else if (port == 0xCF8)
{
dbg("outl(0x%x, 0x%x)\r\n", port, val);
config_address_reg = val;
}
else if ((port == 0xCFC) && ((config_address_reg & 0x80000000) !=0))
@@ -209,6 +200,8 @@ void do_int(struct X86EMU *emu, int num)
{
int ret = 0;
dbg("int %02xh\r\n", num);
switch (num)
{
#ifndef _PC
@@ -275,9 +268,17 @@ void run_bios(struct radeonfb_info *rinfo)
unsigned short initialip;
unsigned short devfn = (unsigned short) rinfo->handle;
struct X86EMU emu;
struct X86EMU emu = {0};
X86EMU_init_default(&emu);
emu.emu_inb = inb;
emu.emu_inw = inw;
emu.emu_inl = inl;
emu.emu_outb = outb;
emu.emu_outw = outw;
emu.emu_outl = outl;
if ((rinfo->mmio_base == NULL) || (rinfo->io_base == NULL))
{
@@ -301,19 +302,20 @@ void run_bios(struct radeonfb_info *rinfo)
if (BIOS_IN8((long) &rom_data->type) != 0)
{
dbg("%s: ROM data type = 0x%x\r\n", __FUNCTION__, BIOS_IN8((long) &rom_data->type));
dbg("unknown ROM data type = 0x%x\r\n", BIOS_IN8((long) &rom_data->type));
return;
}
rom_size = (unsigned long) BIOS_IN8((long) &rom_header->size) * 512;
dbg("ROM size = 0x%lx\r\n", rom_size);
if (PCI_CLASS_DISPLAY_VGA == BIOS_IN16((long) &rom_data->class_hi))
{
memset((char *) biosmem, 0, SIZE_EMU);
setup_system_bios((char *) biosmem);
dbg("%s: Copying VGA ROM Image from %p to %p (0x%lx bytes)\r\n",
__FUNCTION__, (long) rinfo->bios_seg + (long) rom_header,
dbg("Copying VGA ROM Image from %p to %p (0x%lx bytes)\r\n",
(long) rinfo->bios_seg + (long) rom_header,
biosmem + PCI_VGA_RAM_IMAGE_START, rom_size);
{
long bytes_align = (long) rom_header & 3;
@@ -335,7 +337,7 @@ void run_bios(struct radeonfb_info *rinfo)
memset((char *) biosmem, 0, SIZE_EMU);
setup_system_bios((char *) biosmem);
dbg("%s: Copying non-VGA ROM Image from %p to %p (0x%lx bytes)\r\n", __FUNCTION__,
dbg("Copying non-VGA ROM Image from %p to %p (0x%lx bytes)\r\n",
(long) rinfo->bios_seg + (long) rom_header,
biosmem + PCI_RAM_IMAGE_START,
rom_size);
@@ -367,16 +369,16 @@ void run_bios(struct radeonfb_info *rinfo)
}
{
/* FixME: move PIT init to its own file */
outb(0x36, 0x43);
outb(0x00, 0x40);
outb(0x00, 0x40);
outb(&emu, 0x36, 0x43);
outb(&emu, 0x00, 0x40);
outb(&emu, 0x00, 0x40);
}
// setup_int_vect();
/* cpu setup */
emu.x86.R_AX = devfn ? devfn : 0xff;
emu.x86.R_DX = 0x80;
emu.x86.R_EIP = initialip;
emu.x86.R_IP = initialip;
emu.x86.R_CS = initialcs;
/* Initialize stack and data segment */
@@ -398,16 +400,12 @@ void run_bios(struct radeonfb_info *rinfo)
// pushw(0xb890); /* nop, mov ax,#0x13 */
pushw(&emu, emu.x86.R_SS);
pushw(&emu, emu.x86.R_SP + 2);
#ifdef DBG_X86EMU
X86EMU_trace_on();
X86EMU_set_debug(DEBUG_DECODE_F | DEBUG_TRACE_F);
#endif
dbg("%s: X86EMU entering emulator\r\n", __FUNCTION__);
dbg("X86EMU entering emulator\r\n");
//*vblsem = 0;
X86EMU_exec(&emu);
//*vblsem = 1;
dbg("%s: X86EMU halted\r\n", __FUNCTION__);
dbg("X86EMU halted\r\n");
// biosfn_set_video_mode(0x13); /* 320 x 200 x 256 colors */
memset((char *) biosmem, 0, SIZE_EMU);
}

2893
x86emu/x86emu.c
View File

File diff suppressed because it is too large Load Diff

54
x86emu/x86emu_util.c
View File

@@ -79,11 +79,11 @@ Reads a byte value from the emulator memory.
****************************************************************************/
static uint8_t rdb(struct X86EMU *emu, uint32_t addr)
{
if (addr > emu->mem_size - 1)
if (addr > emu->mem_size - 1)
{
X86EMU_halt_sys(emu);
X86EMU_halt_sys(emu);
}
return emu->mem_base[addr];
return emu->mem_base[addr];
}
/****************************************************************************
@@ -98,11 +98,11 @@ Reads a word value from the emulator memory.
****************************************************************************/
static uint16_t rdw(struct X86EMU *emu, uint32_t addr)
{
if (addr > emu->mem_size - 2)
if (addr > emu->mem_size - 2)
{
X86EMU_halt_sys(emu);
X86EMU_halt_sys(emu);
}
return le16dec(emu->mem_base + addr);
return le16dec(emu->mem_base + addr);
}
/****************************************************************************
@@ -116,11 +116,11 @@ Reads a long value from the emulator memory.
****************************************************************************/
static uint32_t rdl(struct X86EMU *emu, uint32_t addr)
{
if (addr > emu->mem_size - 4)
if (addr > emu->mem_size - 4)
{
X86EMU_halt_sys(emu);
X86EMU_halt_sys(emu);
}
return le32dec(emu->mem_base + addr);
return le32dec(emu->mem_base + addr);
}
/****************************************************************************
@@ -133,11 +133,11 @@ Writes a byte value to emulator memory.
****************************************************************************/
static void wrb(struct X86EMU *emu, uint32_t addr, uint8_t val)
{
if (addr > emu->mem_size - 1)
if (addr > emu->mem_size - 1)
{
X86EMU_halt_sys(emu);
X86EMU_halt_sys(emu);
}
emu->mem_base[addr] = val;
emu->mem_base[addr] = val;
}
/****************************************************************************
@@ -150,11 +150,11 @@ Writes a word value to emulator memory.
****************************************************************************/
static void wrw(struct X86EMU *emu, uint32_t addr, uint16_t val)
{
if (addr > emu->mem_size - 2)
if (addr > emu->mem_size - 2)
{
X86EMU_halt_sys(emu);
X86EMU_halt_sys(emu);
}
le16enc(emu->mem_base + addr, val);
le16enc(emu->mem_base + addr, val);
}
/****************************************************************************
PARAMETERS:
@@ -166,28 +166,28 @@ Writes a long value to emulator memory.
****************************************************************************/
static void wrl(struct X86EMU *emu, uint32_t addr, uint32_t val)
{
if (addr > emu->mem_size - 4)
if (addr > emu->mem_size - 4)
{
X86EMU_halt_sys(emu);
X86EMU_halt_sys(emu);
}
le32enc(emu->mem_base + addr, val);
le32enc(emu->mem_base + addr, val);
}
/*----------------------------- Setup -------------------------------------*/
void X86EMU_init_default(struct X86EMU *emu)
{
int i;
int i;
emu->emu_rdb = rdb;
emu->emu_rdw = rdw;
emu->emu_rdl = rdl;
emu->emu_wrb = wrb;
emu->emu_wrw = wrw;
emu->emu_wrl = wrl;
emu->emu_rdb = rdb;
emu->emu_rdw = rdw;
emu->emu_rdl = rdl;
emu->emu_wrb = wrb;
emu->emu_wrw = wrw;
emu->emu_wrl = wrl;
for (i = 0; i < 256; i++)
for (i = 0; i < 256; i++)
{
emu->_X86EMU_intrTab[i] = NULL;
emu->_X86EMU_intrTab[i] = NULL;
}
}

10
x86emu/x86pcibios.c
View File

@@ -6,14 +6,8 @@
#include "bas_printf.h"
extern unsigned short offset_port;
#define DBG_PCIBIOS
#ifdef DBG_PCIBIOS
#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
#else
#define dbg(format, arg...) do {;} while (0)
#endif /* DBG_PCIBIOS */
#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0);
#define DEBUG
#include "debug.h"
int x86_pcibios_handler(struct X86EMU *emu)
{