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PCI memory access working

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This commit is contained in:
Markus Fröschle
2016-10-15 21:26:49 +00:00
parent 369cc9dc0a
commit 42729fa2ea
68 changed files with 14798 additions and 2460 deletions
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7
sys/BaS.c
View File

@@ -295,9 +295,10 @@ NIF nif2;
bool spurious_interrupt_handler(void *arg1, void *arg2)
{
dbg("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL);
dbg("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL);
dbg("IRLR=%x\r\n", MCF_INTC_IRLR);
err("spurious interrupt\r\n");
err("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL);
err("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL);
err("IRLR=%x\r\n", MCF_INTC_IRLR);
return true;
}

146
sys/interrupts.c
View File

@@ -37,14 +37,8 @@
#include "dma.h"
#include "pci.h"
// #define IRQ_DEBUG
#if defined(IRQ_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
#define err(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
// #define DEBUG
#include "debug.h"
#ifndef MAX_ISR_ENTRY
#define MAX_ISR_ENTRY (20)
@@ -206,6 +200,140 @@ void isr_remove_handler(bool (*handler)(void *, void *))
dbg("no such handler registered (handler=%p\r\n", handler);
}
#ifdef DEBUG
static char *vector_to_str[] =
{
"initial stack pointer", /* 0 */
"initial program counter", /* 1 */
"access error", /* 2 */
"address error", /* 3 */
"illegal instruction", /* 4 */
"divide by zero", /* 5 */
"reserved6", /* 6 */
"reserved7", /* 7 */
"privilege violation", /* 8 */
"trace", /* 9 */
"unimplemented line-a opcode", /* 10 */
"unimplemented line-f opcode", /* 11 */
"non-PC breakpoint debug interrupt", /* 12 */
"PC breakpoint debug interrupt", /* 13 */
"format error", /* 14 */
"uninitialized interrupt", /* 15 */
"reserved16",
"reserved17",
"reserved18",
"reserved19",
"reserved20",
"reserved21",
"reserved22",
"reserved23",
"spurious interrupt", /* 24 */
"level 1 autovector", /* 25 */
"level 2 autovector", /* 26 */
"level 3 autovector", /* 27 */
"level 4 autovector", /* 28 */
"level 5 autovector", /* 29 */
"level 6 autovector", /* 30 */
"level 7 autovector", /* 31 */
"trap #0", /* 32 */
"trap #1", /* 33 */
"trap #2", /* 34 */
"trap #3", /* 35 */
"trap #4", /* 36 */
"trap #5", /* 37 */
"trap #6", /* 38 */
"trap #7", /* 39 */
"trap #8", /* 40 */
"trap #9", /* 41 */
"trap #10" /* 42 */
"trap #11", /* 43 */
"trap #12", /* 44 */
"trap #13", /* 45 */
"trap #14", /* 46 */
"trap #15", /* 47 */
"floating point branch on unordered condition", /* 48 */
"floting point inexact result", /* 49 */
"floating point divide by zero", /* 50 */
"floating point underflow", /* 51 */
"floating point operand error", /* 52 */
"floating point overflow", /* 53 */
"floating point NaN", /* 54 */
"floating point denormalized number", /* 55 */
"reserved56", /* 56 */
"reserved57",
"reserved58",
"reserved59",
"reserved60",
"unsupported instruction", /* 61 */
"reserved62", /* 62 */
"reserved63", /* 63 */
"", "",
"edge port 1", /* 1 */
"edge port 2", /* 2 */
"edge port 3", /* 3 */
"edge port 4", /* 4 */
"edge port 5", /* 5 */
"edge port 6", /* 6 */
"edge port 7", /* 7 */
"unused8",
"unused9",
"unused10",
"unused11",
"unused12",
"unused13",
"unused14",
"USB endpoint 0", /* 15 */
"USB endpoint 1", /* 16 */
"USB endpoint 2", /* 17 */
"USB endpoint 3", /* 18 */
"USB endpoint 4", /* 19 */
"USB endpoint 5", /* 20 */
"USB endpoint 6", /* 21 */
"USB general interrupt", /* 22 */
"USB core interrupt", /* 23 */
"USB OR interrupt", /* 24 */
"DSPI over/underflow", /* 25 */
"DSPI receive FIFO overflow", /* 26 */
"DSPI receive FIFO drain", /* 27 */
"DSPI transmit FIFO underflow", /* 28 */
"DSPI transfer complete", /* 29 */
"DSPI trasmit FIFO full", /* 30 */
"DSPI end of queue", /* 31 */
"PSC3", /* 32 */
"PSC2", /* 33 */
"PSC1", /* 34 */
"PSC0", /* 35 */
"Comm timer", /* 36 */
"SEC", /* 37 */
"FEC1", /* 38 */
"FEC0", /* 39 */
"I2C", /* 40 */
"PCI arbiter", /* 41 */
"comm bus PCI", /* 42 */
"XLB PCI", /* 43 */
"not used44",
"not used45",
"not used46",
"XLB arbiter to CPU", /* 47 */
"multichannel DMA", /* 48 */
"FlexCAN 0 error", /* 49 */
"FlexCAN 0 bus off", /* 50 */
"FlexCAN 0 message buffer", /* 51 */
"not used52"
"slice timer 1", /* 53 */
"slice timer 0", /* 54 */
"FlexCAN 1 error", /* 55 */
"FlexCAN 1 bus off", /* 56 */
"FlexCAN 1 message buffer", /* 57 */
"not used58",
"GPT3", /* 59 */
"GPT2", /* 60 */
"GPT1", /* 61 */
"GPT0", /* 62 */
"not used63"
};
#endif /* DEBUG */
/*
* This routine searches the ISR table for an entry that matches
* 'vector'. If one is found, then 'handler' is executed.
@@ -218,7 +346,7 @@ bool isr_execute_handler(int vector)
{
int index;
dbg("vector = %d\r\n", vector);
dbg("vector = %d (%s)\r\n", vector, vector_to_str[vector]);
/*
* locate an interrupt service routine handler.

53
sys/mmu.c
View File

@@ -36,26 +36,6 @@
* Copyright 2013 M. Froeschle
*/
#define ACR_BA(x) ((x) & 0xffff0000)
#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
#define ACR_E(x) (((x) & 1) << 15)
#define ACR_S(x) (((x) & 3) << 13)
#define ACR_S_USERMODE 0
#define ACR_S_SUPERVISOR_MODE 1
#define ACR_S_ALL 2
#define ACR_AMM(x) (((x) & 1) << 10)
#define ACR_CM(x) (((x) & 3) << 5)
#define ACR_CM_CACHEABLE_WT 0x0
#define ACR_CM_CACHEABLE_CB 0x1
#define ACR_CM_CACHE_INH_PRECISE 0x2
#define ACR_CM_CACHE_INH_IMPRECISE 0x3
#define ACR_SP(x) (((x) & 1) << 3)
#define ACR_W(x) (((x) & 1) << 2)
#include <stdint.h>
#include "bas_printf.h"
#include "bas_types.h"
@@ -230,6 +210,9 @@ static struct virt_to_phys translation[] =
{ 0x00000000, 0x00e00000, 0x00000000 }, /* map first 14 MByte to first 14 Mb of SD ram */
{ 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */
{ 0x01000000, 0x04000000, 0x00000000 }, /* map rest of ram virt = phys */
#if 0
{ 0x04000000, 0x08000000, 0x7C000000 }, /* experimental mapping for PCI memory */
#endif
};
#elif defined(MACHINE_M54455)
/* FIXME: this is not determined yet! */
@@ -269,14 +252,14 @@ static inline uint32_t lookup_phys(int32_t virt)
* bytes size) or 8k pages (64k descriptor array size)
*/
#define NUM_PAGES (SDRAM_SIZE / SIZE_DEFAULT)
static struct mmu_page_descriptor pages[NUM_PAGES];
static struct mmu_page_descriptor_ram pages[NUM_PAGES];
int mmu_map_instruction_page(uint32_t virt, uint8_t asid)
{
const uint32_t size_mask = ~ (SIZE_DEFAULT - 1); /* pagesize */
int page_index = (virt & size_mask) / SIZE_DEFAULT; /* index into page_descriptor array */
struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
struct mmu_page_descriptor_ram *page = &pages[page_index]; /* attributes of page to map */
int ipl;
uint32_t phys = lookup_phys(virt); /* virtual to physical translation of page */
@@ -332,7 +315,7 @@ int mmu_map_data_page(uint32_t virt, uint8_t asid)
uint16_t ipl;
const uint32_t size_mask = ~ (SIZE_DEFAULT - 1); /* pagesize */
int page_index = (virt & size_mask) / SIZE_DEFAULT; /* index into page_descriptor array */
struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
struct mmu_page_descriptor_ram *page = &pages[page_index]; /* attributes of page to map */
uint32_t phys = lookup_phys(virt); /* virtual to physical translation of page */
@@ -389,7 +372,7 @@ int mmu_map_data_page(uint32_t virt, uint8_t asid)
* per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
* LRU algorithm) should be used sparsingly.
*/
uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags)
uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor_ram *flags)
{
int size_mask;
int ipl;
@@ -456,7 +439,7 @@ void mmu_init(void)
{
extern uint8_t _MMUBAR[];
uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
struct mmu_page_descriptor flags;
struct mmu_page_descriptor_ram flags;
int i;
/*
@@ -613,18 +596,21 @@ void mmu_init(void)
/* set data access attributes in ACR0 and ACR1 */
/* map PCI address space */
/* set SRAM and MBAR access */
set_acr0(ACR_W(0) | /* read and write accesses permitted */
//ACR_SP(1) | /* supervisor only access permitted */
// ACR_SP(1) | /* supervisor only access permitted */
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
ACR_AMM(0) | /* control region > 16 MB */
ACR_S(ACR_S_SUPERVISOR_MODE) | /* match addresses in supervisor mode only */
ACR_S(ACR_S_SUPERVISOR_MODE) | /* match addresses in supervisor and user mode */
ACR_E(1) | /* enable ACR */
#if defined(MACHINE_FIREBEE)
ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */
ACR_BA(PCI_MEMORY_OFFSET)); /* (equals area from 3 to 4 GB */
// ACR_BA(PCI_MEMORY_OFFSET)); /* (equals area from 3 to 4 GB */
ACR_BA(0xe0000000));
#elif defined(MACHINE_M5484LITE)
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
ACR_BA(PCI_MEMORY_OFFSET));
// ACR_BA(PCI_MEMORY_OFFSET));
ACR_BA(0xe0000000));
#elif defined(MACHINE_M54455)
ACR_ADMSK(0x7f) |
ACR_BA(0x80000000)); /* FIXME: not determined yet */
@@ -709,6 +695,10 @@ void mmu_init(void)
flags.execute = 0;
flags.locked = 1;
mmu_map_page(0x6a000000, 0x6a000000, MMU_PAGE_SIZE_1M, 0, &flags);
#elif defined(MACHINE_M54455)
#warning MMU specs for M54455 not yet determined
#else
#error Unknown machine
#endif /* MACHINE_FIREBEE */
/*
@@ -881,7 +871,7 @@ uint32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
{
const uint32_t size_mask = ~ (SIZE_DEFAULT - 1); /* pagesize */
int page_index = (virt & size_mask) / SIZE_DEFAULT; /* index into page_descriptor array */
struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
struct mmu_page_descriptor_ram *page = &pages[page_index]; /* attributes of page to map */
int i = 0;
while (page_index * SIZE_DEFAULT < virt + size)
@@ -914,7 +904,7 @@ uint32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
int curr_asid;
const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);
int page_index = (address & size_mask) / SIZE_DEFAULT; /* index into page descriptor array */
struct mmu_page_descriptor *page = &pages[page_index];
struct mmu_page_descriptor_ram *page = &pages[page_index];
curr_asid = set_asid(asid); /* set asid to the one to search for */
@@ -1000,3 +990,4 @@ uint32_t mmu_report_pagesize(void)
{
return SIZE_DEFAULT;
}

15
sys/sysinit.c
View File

@@ -53,6 +53,9 @@
#include "usb.h"
#include "video.h"
#define DEBUG
#include "debug.h"
#define UNUSED(x) (void)(x) /* Unused variable */
bool fpga_configured = false; /* for FPGA JTAG configuration */
@@ -462,6 +465,9 @@ static void init_fbcs()
MCF_FBCS3_CSMR = 0;
MCF_FBCS4_CSMR = 0;
/*
* the FireEngine needs AA for its CPLD accessed registers
*/
MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000);
MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 | /* CPLD access 16 bit wide */
MCF_FBCS_CSCR_WS(32) | /* 32 wait states */
@@ -587,6 +593,7 @@ void init_usb(void)
do
{
handle = pci_find_classcode(PCI_CLASS_SERIAL_USB | PCI_FIND_BASE_CLASS | PCI_FIND_SUB_CLASS, index++);
dbg("handle 0x%02x\r\n", handle);
if (handle > 0)
{
long id;
@@ -597,10 +604,10 @@ void init_usb(void)
PCI_DEVICE_FROM_HANDLE(handle),
PCI_FUNCTION_FROM_HANDLE(handle),
handle);
id = pci_read_config_longword(handle, PCIIDR);
pci_class = pci_read_config_longword(handle, PCIREV);
id = swpl(pci_read_config_longword(handle, PCIIDR));
pci_class = swpl(pci_read_config_longword(handle, PCIREV));
if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_EHCI)
if (pci_class == PCI_CLASS_SERIAL_USB_EHCI)
{
board = ehci_usb_pci_table;
while (board->vendor)
@@ -615,7 +622,7 @@ void init_usb(void)
board++;
}
}
if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_OHCI)
if (pci_class == PCI_CLASS_SERIAL_USB_OHCI)
{
board = ohci_usb_pci_table;
while (board->vendor)