PCI memory access working
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@@ -30,8 +30,8 @@
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/*
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* ACR register handling macros
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*/
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#define ACR_BA(x) ((x) & 0xffff0000)
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#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
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#define ACR_BA(x) ((x) & 0xff000000)
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#define ACR_ADMSK(x) (((x) & 0xff) << 16)
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#define ACR_E(x) (((x) & 1) << 15)
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#define ACR_S(x) (((x) & 3) << 13)
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@@ -45,6 +45,17 @@
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#define ACR_SUPERVISOR_PROTECT(x) (((x) & 1) << 3)
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#define ACR_WRITE_PROTECT(x) (((x) & 1) << 2)
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#define ACR_AMM(x) (((x) & 1) << 10)
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#define ACR_CM(x) (((x) & 3) << 5)
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#define ACR_CM_CACHEABLE_WT 0x0
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#define ACR_CM_CACHEABLE_CB 0x1
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#define ACR_CM_CACHE_INH_PRECISE 0x2
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#define ACR_CM_CACHE_INH_IMPRECISE 0x3
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#define ACR_SP(x) (((x) & 1) << 3)
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#define ACR_W(x) (((x) & 1) << 2)
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/*
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* MMU register handling macros
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@@ -98,7 +109,7 @@ enum mmu_page_size
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extern long video_tlb;
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extern long video_sbt;
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struct mmu_page_descriptor
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struct mmu_page_descriptor_ram
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{
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uint8_t cache_mode : 2;
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uint8_t supervisor_protect : 1;
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@@ -110,7 +121,7 @@ struct mmu_page_descriptor
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};
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extern void mmu_init(void);
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extern uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags);
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extern uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor_ram *flags);
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/*
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* API functions for the BaS driver interface
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