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add palette register tests

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This commit is contained in:
Markus Fröschle
2017-02-04 22:31:05 +00:00
parent 626ca2a94d
commit 3c15ef3471
1 changed files with 148 additions and 44 deletions
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192
BaS_gcc/tos/fpga_test/sources/fpga_test.c
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@@ -23,33 +23,67 @@ long bas_start = 0xe0000000;
volatile uint16_t *FB_CS1 = (volatile uint16_t *) 0xfff00000; /* "classic" ATARI I/O registers */
volatile uint32_t *FB_CS2 = (volatile uint32_t *) 0xf0000000; /* FireBee 32 bit I/O registers */
volatile uint16_t *FB_CS3 = (volatile uint16_t *) 0xf8000000; /* FireBee SRAM */
uint32_t *FB_CS4 = (uint32_t *) 0x40000000; /* FireBee SD RAM */
volatile uint32_t *FB_CS4 = (uint32_t *) 0x40000000; /* FireBee SD RAM */
const long sdram_size = 128 * 1024L * 1024L;
static void init_ddr_ram(void)
{
xprintf("init video RAM: ");
FB_CS2[0x100] = 0xb; /* set cke = 1, cs=1, config = 1 */
NOP();
FB_CS4[0] = 0x00050400; /* IPALL */
NOP();
FB_CS4[0] = 0x00072000; /* load EMR pll on */
NOP();
FB_CS4[0] = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */
NOP();
FB_CS4[0] = 0x00050400; /* IPALL */
NOP();
FB_CS4[0] = 0x00060000; /* auto refresh */
NOP();
FB_CS4[0] = 0x00060000; /* auto refresh */
NOP();
/* FIXME: what's this? */
FB_CS4[0] = 0000070022; /* load MR dll on */
NOP();
FB_CS2[0x100] = 0x01070082; /* fifo on, refresh on, ddrcs und cke on, video dac on, Falcon shift mode on */
xprintf("finished\r\n");
}
bool verify_ddr_ram(uint32_t value)
{
uint32_t *lp;
uint16_t *wp;
volatile uint32_t *lp;
volatile uint16_t *wp;
uint32_t rl;
uint16_t rw;
lp = FB_CS4;
/*
* write longs
* write/read longs
*/
lp = FB_CS4;
do
{
*lp = value;
} while (lp++ <= FB_CS4 + sdram_size - 1);
xprintf("W: 0x%08x R: 0x%08x\r", value, rl = *lp);
/*
* read longs
*/
lp = FB_CS4;
do
{
if (*lp != value)
if (rl != value)
{
xprintf("\nvalidation error at %p: written = 0x%08x, read = 0x%08x\r\n", lp, value, rl);
return false;
}
} while (lp++ <= FB_CS4 + sdram_size - 1);
@@ -57,21 +91,19 @@ bool verify_ddr_ram(uint32_t value)
wp = (uint16_t *) FB_CS4;
/*
* write words
*/
do
{
*wp = (uint16_t) value;
} while (wp++ <= (uint16_t *) FB_CS4 + sdram_size - 1);
/*
* read words
* write/read words
*/
wp = (uint16_t *) FB_CS4;
do
{
if (*wp != value)
*wp = (uint16_t) value;
xprintf("W: 0x%04x R: 0x%04x\r", value, rw = *wp);
if (rw != value)
{
xprintf("\nvalidation error at %p: written = 0x%04x, read = 0x%04x\r\n", wp, value, rw);
return false;
}
} while (wp++ <= (uint16_t *) FB_CS4 + sdram_size - 1);
@@ -157,7 +189,7 @@ bool verify_wordaddr(volatile uint16_t * const addr, uint16_t value)
if (value != (rvalue = *addr))
{
xprintf("validation error at %p, wrote 0x%4x, read 0x%4x\r\n", addr, value, rvalue);
xprintf("validation error at %p, wrote 0x%04x, read 0x%04x\r\n", addr, value, rvalue);
xprintf("\r\n");
@@ -169,7 +201,7 @@ bool verify_wordaddr(volatile uint16_t * const addr, uint16_t value)
bool verify_word(volatile uint16_t * const addr, uint16_t low_value, uint16_t high_value)
{
int16_t i;
uint16_t i;
for (i = low_value; i <= high_value; i++)
if (verify_wordaddr(addr, i) == false)
@@ -182,30 +214,98 @@ bool verify_word(volatile uint16_t * const addr, uint16_t low_value, uint16_t hi
return true;
}
void atari_io_test(void)
bool verify_byteaddr(volatile uint8_t * const addr, uint8_t value)
{
volatile uint16_t *SYS_CTR = &FB_CS1[0x7c003]; /* 0xffff8006 */
volatile uint16_t *VDL_LOF = &FB_CS1[0x7c107]; /* 0xffff820e */
volatile uint16_t *VDL_LWD = &FB_CS1[0x7c108]; /* 0xffff8210 */
volatile uint16_t *VDL_HHT = &FB_CS1[0x7c141]; /* 0xffff8282 */
volatile uint16_t *VDL_HBB = &FB_CS1[0x7c142]; /* 0xffff8284 */
volatile uint16_t *VDL_HBE = &FB_CS1[0x7c143]; /* 0xffff8286 */
volatile uint16_t *VDL_HDB = &FB_CS1[0x7c144]; /* 0xffff8288 */
volatile uint16_t *VDL_HDE = &FB_CS1[0x7c145]; /* 0xffff828a */
volatile uint16_t *VDL_HSS = &FB_CS1[0x7c146]; /* 0xffff828c */
uint8_t rvalue;
*addr = value;
volatile uint16_t *VDL_VFT = &FB_CS1[0x7c151]; /* 0xffff82a2 */
volatile uint16_t *VDL_VBB = &FB_CS1[0x7c152]; /* 0xffff82a4 */
volatile uint16_t *VDL_VBE = &FB_CS1[0x7c153]; /* 0xffff82a6 */
volatile uint16_t *VDL_VDB = &FB_CS1[0x7c154]; /* 0xffff82a8 */
volatile uint16_t *VDL_VDE = &FB_CS1[0x7c155]; /* 0xffff82aa */
volatile uint16_t *VDL_VSS = &FB_CS1[0x7c156]; /* 0xffff82ac */
volatile uint16_t *VDL_VCT = &FB_CS1[0x7c160]; /* 0xffff82c0 */
volatile uint16_t *VDL_VMD = &FB_CS1[0x7c161]; /* 0xffff82c2 */
if (value != (rvalue = *addr))
{
xprintf("validation error at %p, wrote 0x%02x, read 0x%02x\r\n", addr, value, rvalue);
xprintf("\r\n");
return false;
}
return true;
}
bool verify_byte(volatile uint8_t * const addr, uint8_t low_value, uint8_t high_value)
{
int8_t i;
for (i = low_value; i <= high_value; i++)
if (verify_byteaddr(addr, i) == false)
{
xprintf("verify of %p failed: 0x%02x written, 0x%02x read\r\n",
addr, i, *addr);
return false;
}
return true;
}
void falcon_io_test(void)
{
int i;
volatile uint16_t *SYS_CTR = &FB_CS1[0x7c003]; /* 0xffff8006 */
volatile uint8_t *VIDEO_ADR_HI = ((volatile uint8_t *) &FB_CS1[0x7c100]) + 1; /* 0xffff8201 */
volatile uint8_t *VIDEO_ADR_MI = ((volatile uint8_t *) &FB_CS1[0x7c101]) + 1; /* 0xffff8203 */
volatile uint8_t *VIDEO_ADR_LO = ((volatile uint8_t *) &FB_CS1[0x7c106]) + 1; /* 0xffff820d */
volatile uint8_t *VIDEO_CNT_HI = ((volatile uint8_t *) &FB_CS1[0x7c102]) + 1; /* 0xffff8205 */
volatile uint8_t *VIDEO_CNT_MI = ((volatile uint8_t *) &FB_CS1[0x7c103]) + 1; /* 0xffff8207 */
volatile uint8_t *VIDEO_CNT_LO = ((volatile uint8_t *) &FB_CS1[0x7c104]) + 1; /* 0xffff8209 */
volatile uint8_t *SYNC_MODE = ((volatile uint8_t *) &FB_CS1[0x7c105]) + 1; /* 0xffff8006 */
volatile uint16_t *VDL_LOF = &FB_CS1[0x7c107]; /* 0xffff820e */
volatile uint16_t *VDL_LWD = &FB_CS1[0x7c108]; /* 0xffff8210 */
volatile uint16_t *VDL_HHT = &FB_CS1[0x7c141]; /* 0xffff8282 */
volatile uint16_t *VDL_HBB = &FB_CS1[0x7c142]; /* 0xffff8284 */
volatile uint16_t *VDL_HBE = &FB_CS1[0x7c143]; /* 0xffff8286 */
volatile uint16_t *VDL_HDB = &FB_CS1[0x7c144]; /* 0xffff8288 */
volatile uint16_t *VDL_HDE = &FB_CS1[0x7c145]; /* 0xffff828a */
volatile uint16_t *VDL_HSS = &FB_CS1[0x7c146]; /* 0xffff828c */
volatile uint16_t *VDL_VFT = &FB_CS1[0x7c151]; /* 0xffff82a2 */
volatile uint16_t *VDL_VBB = &FB_CS1[0x7c152]; /* 0xffff82a4 */
volatile uint16_t *VDL_VBE = &FB_CS1[0x7c153]; /* 0xffff82a6 */
volatile uint16_t *VDL_VDB = &FB_CS1[0x7c154]; /* 0xffff82a8 */
volatile uint16_t *VDL_VDE = &FB_CS1[0x7c155]; /* 0xffff82aa */
volatile uint16_t *VDL_VSS = &FB_CS1[0x7c156]; /* 0xffff82ac */
volatile uint16_t *VDL_VCT = &FB_CS1[0x7c160]; /* 0xffff82c0 */
volatile uint16_t *VDL_VMD = &FB_CS1[0x7c161]; /* 0xffff82c2 */
/* ST palette registers */
volatile uint8_t *st_palette = (volatile uint8_t *) &FB_CS1[0x7c120];
xprintf("verify VIDEO_ADR_XX registers\r\n");
verify_byte(VIDEO_ADR_HI, 0x00, 0xff);
verify_byte(VIDEO_ADR_MI, 0x00, 0xff);
verify_byte(VIDEO_ADR_LO, 0x00, 0xff);
xprintf("verify VIDEO_CNT_XX registers\r\n");
verify_byte(VIDEO_CNT_HI, 0x00, 0xff);
verify_byte(VIDEO_CNT_MI, 0x00, 0xff);
verify_byte(VIDEO_CNT_LO, 0x00, 0xff);
xprintf("verify SYNC_MODE register\r\n");
verify_byte(SYNC_MODE, 0x00, 0xff);
xprintf("verify SYS_CTR register\r\n");
verify_word(SYS_CTR, 0, 0x1ff);
for (i = 0; i < 16 * 2; i += 2)
{
xprintf("verify ST palette register %d\r\n", i / 2);
verify_byte(&st_palette[i], i / 2, i / 2);
verify_byte(&st_palette[i], i / 2, i / 2); /* do two consecutive tests here because of RAM latency */
}
xprintf("verify LOF register\r\n");
verify_word(VDL_LOF, 0, 0x1ff);
@@ -260,11 +360,15 @@ void do_tests(void)
{
xprintf("start tests:\r\n");
xprintf("ATARI I/O test\r\n");
atari_io_test();
xprintf("Falcon I/O test\r\n");
falcon_io_test();
xprintf("FireBee I/O test\r\n");
firebee_io_test();
init_ddr_ram();
verify_ddr_ram(0xaaaaaaaa);
verify_ddr_ram(0x55555555);
}