From 33d71f3d84b58338cab4778df0e49d873d4e3b14 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 16 Oct 2012 05:53:53 +0000 Subject: [PATCH] FPGA pins (clock, config) were the wrong way round for FPGA programming in init_fpga. Corrected. --- BaS_GNU/sources/sysinit.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 2dc170e..caaeb2a 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -216,8 +216,8 @@ void init_fpga(void) uart_out_word('FPGA'); - MCF_GPIO_PODR_FEC1L |= (1 << 1); - MCF_GPIO_PODR_FEC1L |= (1 << 2); + MCF_GPIO_PODR_FEC1L &= ~(1 << 1); /* FPGA clock => low */ + MCF_GPIO_PODR_FEC1L &= ~(1 << 2); /* FPGA config => low */ while ((! (MCF_GPIO_PPDSDR_FEC1L & (1 << 0))) && (! (MCF_GPIO_PPDSDR_FEC1L & (1 << 5)))); @@ -283,10 +283,10 @@ void init_fpga(void) } else { - MCF_PSC0_PSCTB_8BIT = ' NOT'; + uart_out_word(' NOT'); } - MCF_PSC0_PSCTB_8BIT = 'OK! '; - MCF_PSC0_PSCTB_8BIT = 0x0d0a; + uart_out_word(' OK!'); + uart_out_word(0x0d0a); } void wait_pll(void)