modified debug output and FBCS5 waitstates
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@@ -63,4 +63,4 @@ erase 0xe0000000 37
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erase 0xe0000000 38
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erase 0xe0000000 39
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load -v ../../emutos/emutos-m548x_bas.elf
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load ../../emutos/emutos-m548x_bas.elf
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@@ -58,9 +58,9 @@
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#define DEBUG_MMU
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#ifdef DEBUG_MMU
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#define debug_print(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg);} while(0)
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#define dbg_mmu(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg);} while(0)
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#else
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#define debug_print(format, arg...) do {;} while (0)
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#define dbg_mmu(format, arg...) do {;} while (0)
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#endif /* DEBUG_MMU */
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/*
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@@ -363,7 +363,7 @@ void mmutr_miss(void)
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{
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register uint32_t address asm("d0");
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debug_print("MMU TLB MISS at 0x%08x\r\n", address);
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dbg_mmu("MMU TLB MISS at 0x%08x\r\n", address);
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flush_and_invalidate_caches();
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switch (address)
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@@ -371,13 +371,13 @@ void mmutr_miss(void)
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case keyctl:
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case keybd:
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/* do something to emulate the IKBD access */
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debug_print("IKBD access\r\n");
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dbg_mmu("IKBD access\r\n");
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break;
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case midictl:
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case midi:
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/* do something to emulate MIDI access */
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debug_print("MIDI ACIA access\r\n");
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dbg_mmu("MIDI ACIA access\r\n");
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break;
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default:
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@@ -459,7 +459,7 @@ void init_fbcs()
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MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000);
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MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 /* CPLD access */
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| MCF_FBCS_CSCR_WS(10)
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| MCF_FBCS_CSCR_WS(32)
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| MCF_FBCS_CSCR_ASET(1)
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| MCF_FBCS_CSCR_AA;
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MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M
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