Firebee/BaS_gcc
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

modified debug output and FBCS5 waitstates

Browse Source
This commit is contained in:
Markus Fröschle
2013-12-17 17:53:45 +00:00
parent 38d1e75887
commit 2d34a5b8ad
3 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
flash_scripts/flash_m548x_etos.bdm
View File

@@ -63,4 +63,4 @@ erase 0xe0000000 37
erase 0xe0000000 38 erase 0xe0000000 38
erase 0xe0000000 39 erase 0xe0000000 39
load -v ../../emutos/emutos-m548x_bas.elf load ../../emutos/emutos-m548x_bas.elf

10
sources/mmu.c
View File

@@ -58,9 +58,9 @@
#define DEBUG_MMU #define DEBUG_MMU
#ifdef DEBUG_MMU #ifdef DEBUG_MMU
#define debug_print(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg);} while(0) #define dbg_mmu(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg);} while(0)
#else #else
#define debug_print(format, arg...) do {;} while (0) #define dbg_mmu(format, arg...) do {;} while (0)
#endif /* DEBUG_MMU */ #endif /* DEBUG_MMU */
/* /*
@@ -363,7 +363,7 @@ void mmutr_miss(void)
{ {
register uint32_t address asm("d0"); register uint32_t address asm("d0");
debug_print("MMU TLB MISS at 0x%08x\r\n", address); dbg_mmu("MMU TLB MISS at 0x%08x\r\n", address);
flush_and_invalidate_caches(); flush_and_invalidate_caches();
switch (address) switch (address)
@@ -371,13 +371,13 @@ void mmutr_miss(void)
case keyctl: case keyctl:
case keybd: case keybd:
/* do something to emulate the IKBD access */ /* do something to emulate the IKBD access */
debug_print("IKBD access\r\n"); dbg_mmu("IKBD access\r\n");
break; break;
case midictl: case midictl:
case midi: case midi:
/* do something to emulate MIDI access */ /* do something to emulate MIDI access */
debug_print("MIDI ACIA access\r\n"); dbg_mmu("MIDI ACIA access\r\n");
break; break;
default: default:

2
sources/sysinit.c
View File

@@ -459,7 +459,7 @@ void init_fbcs()
MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000); MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000);
MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 /* CPLD access */ MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 /* CPLD access */
| MCF_FBCS_CSCR_WS(10) | MCF_FBCS_CSCR_WS(32)
| MCF_FBCS_CSCR_ASET(1) | MCF_FBCS_CSCR_ASET(1)
| MCF_FBCS_CSCR_AA; | MCF_FBCS_CSCR_AA;
MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M