From 1dd15009b0c56afff7270a468879240b5458c865 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= <vincent.riviere@freesbee.fr>
Date: Sat, 20 Oct 2012 14:00:11 +0000
Subject: [PATCH] Clean up CACR initialization.

---
 BaS_GNU/sources/cache.c      |  3 ---
 BaS_GNU/sources/mmu.S        |  7 -------
 BaS_GNU/sources/startcf.S    | 10 +++++++---
 BaS_GNU/sources/supervisor.S |  3 ---
 BaS_GNU/sources/sysinit.c    |  8 --------
 5 files changed, 7 insertions(+), 24 deletions(-)

diff --git a/BaS_GNU/sources/cache.c b/BaS_GNU/sources/cache.c
index 5ebd2ea..1cb9f9b 100644
--- a/BaS_GNU/sources/cache.c
+++ b/BaS_GNU/sources/cache.c
@@ -81,9 +81,6 @@ void clear_caches(void)
 	"	move.l		d0,a0\n\t"
 	"	cmpi.w		#4,d0				| all ways?\n\t"
 	"	bne			cfa_setloop			| no->\n\t"
-	"	nop\n\t"
-	"	move.l		_rt_cacr,d0			| get cacr shadow register\n\t"
-	"	movec		d0,cacr				| set old value\n\t"
 	"	move.l		(sp)+,d2\n\t"
 	"	move.w		d2,sr				| restore previous interrupt mask\n\t"
 	/* input */	:
diff --git a/BaS_GNU/sources/mmu.S b/BaS_GNU/sources/mmu.S
index d268e70..e1e1b11 100644
--- a/BaS_GNU/sources/mmu.S
+++ b/BaS_GNU/sources/mmu.S
@@ -82,9 +82,6 @@ _mmu_init:
  		clr.l	d0
 		movec	d0,ASID				// ASID allways 0
 		move.l	d0,_rt_asid			// sichern
-		movec	d0,cacr				// cache aus
-		move.l	d0,_rt_cacr			// sichern
-		nop
 		
 		move.l	#0xC03FC040,d0		// data r/w precise  c000'0000-ffff'ffff
 		movec	d0,ACR0
@@ -171,10 +168,6 @@ _mmu_init:
 		move.l	d1,MCF_MMU_MMUDR
 		move.l	d3,MCF_MMU_MMUOR						// setzen instr
 */
-		move.l	#0xa10ca120,d0
-		move.l	d0,_rt_cacr								// sichern
- 		movec	d0,cacr
-		nop
 		rts
 
 /*
diff --git a/BaS_GNU/sources/startcf.S b/BaS_GNU/sources/startcf.S
index 646c693..c0f9fdb 100644
--- a/BaS_GNU/sources/startcf.S
+++ b/BaS_GNU/sources/startcf.S
@@ -33,10 +33,14 @@ warmstart:
 		/* set stack pointer to end of SRAM1 */
 		lea 	__SUP_SP,a7
 
-		/* instruction cache on */
-		move.l	#0x000C8100,d0
+		/* Initialize the processor caches.
+		 * The instruction cache is fully enabled.
+		 * The data cache is enabled, but cache-inhibited by default.
+		 * Later, the MMU will fully activate the data cache for specific areas.
+		 * It is important to enable both caches now, otherwise cpushl would hang.
+		 */
+		move.l	#0xa50c8120,d0
 		movec	d0,cacr
-		nop
 
 		/* initialize any hardware specific issues */
 		bra    _initialize_hardware
diff --git a/BaS_GNU/sources/supervisor.S b/BaS_GNU/sources/supervisor.S
index b728362..9afa84a 100644
--- a/BaS_GNU/sources/supervisor.S
+++ b/BaS_GNU/sources/supervisor.S
@@ -573,9 +573,6 @@ cfa_setloop:
 	move.l		d0,a0
 	cmpi.w		#4,d0				// all ways?
 	bne			cfa_setloop			// nein->
-	nop
-	move.l		_rt_cacr,d0			// holen
-	movec		d0,cacr				// setzen
 	move.w		d2,sr				// alte interrupt maske
 	movem.l		(a7),d0-d2/a0		// register zur�ck
 	lea			16(a7),a7
diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c
index adb6af7..fb01cb8 100644
--- a/BaS_GNU/sources/sysinit.c
+++ b/BaS_GNU/sources/sysinit.c
@@ -675,14 +675,6 @@ void initialize_hardware(void) {
 	uint32_t *dst;	/* destination address to copy to */
 	uint32_t *jmp;	/* address of BaS() routine to jmp at after copy */
 
-	__asm__ __volatile__(
-	"move.l 	#0x000C8120,D0\n\t"
-	"move.l		D0,_rt_cacr\n\t"
-	"movec		D0,CACR\n\t"
-	"nop\n\t"
-	 : : : "d0", "memory"
-	);
-
 	init_gpio();
 	init_serial();
 	init_slt();