make pci_test skeleton compile
This commit is contained in:
Markus Fröschle
@@ -2,6 +2,7 @@
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.PHONY: jtagwait
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.PHONY: bascook
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.PHONY: vmem_test
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.PHONY: pci_test
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tos: jtagwait bascook vmem_test pci_test
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jtagwait:
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@@ -7,159 +7,17 @@
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#include "MCF5475.h"
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#include "driver_vec.h"
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#define FPGA_CONFIG (1 << 2)
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#define FPGA_CONF_DONE (1 << 5)
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#define SRAM1_START 0xff101000
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#define SRAM1_END SRAM1_START + 0x1000
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#define SAFE_STACK SRAM1_END - 4
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#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
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#define SYSCLK 132000
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long bas_start = 0xe0000000;
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extern volatile uint32_t _VRAM[];
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volatile int32_t time, start, end;
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int i;
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static void wait_pll(void)
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{
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int32_t trgt = MCF_SLT0_SCNT - 100000;
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do
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{
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;
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} while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt);
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}
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static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
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static void init_pll(void)
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{
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xprintf("FPGA PLL initialization: ");
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x48) = 27; /* loopfilter r */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */
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wait_pll();
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* (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */
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wait_pll();
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* (volatile uint8_t *) 0xf0000800 = 0; /* set */
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xprintf("finished\r\n");
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}
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/*
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* INIT VIDEO DDR RAM
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*/
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static void init_video_ddr(void) {
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xprintf("init video RAM: ");
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* (volatile uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */
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NOP();
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_VRAM[0] = 0x00050400; /* IPALL */
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NOP();
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_VRAM[0] = 0x00072000; /* load EMR pll on */
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NOP();
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_VRAM[0] = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */
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NOP();
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_VRAM[0] = 0x00050400; /* IPALL */
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NOP();
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_VRAM[0] = 0x00060000; /* auto refresh */
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NOP();
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_VRAM[0] = 0x00060000; /* auto refresh */
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NOP();
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/* FIXME: what's this? */
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_VRAM[0] = 0000070022; /* load MR dll on */
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NOP();
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* (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */
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xprintf("sys_ctr = 0x%08x\r\n", * (uint32_t *) 0xf0000400);
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xprintf("finished\r\n");
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}
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void do_tests(void)
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{
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uint32_t version;
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xprintf("initialize Firebee video PLL\r\n");
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init_pll();
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xprintf("finished\r\n");
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xprintf("initialize video ddr memory\r\n");
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init_video_ddr();
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xprintf("finished\r\n");
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xprintf("try to read Configware version (only works on later configs)\r\n");
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version = * (uint32_t *) 0xffffffff;
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xprintf("version = 0x%08lx\r\n", version);
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xprintf("try to access Firebee FPGA memory\r\n");
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xprintf("read\r\n");
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start = MCF_SLT0_SCNT;
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hexdump((uint8_t *) _VRAM, 64);
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end = MCF_SLT0_SCNT;
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time = (start - end) / (SYSCLK / 1000) / 1000;
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xprintf("finished (took %f seconds).\r\n", time / 1000.0);
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xprintf("write\r\n");
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start = MCF_SLT0_SCNT;
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for (i = 0; i < 64; i++)
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{
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((uint8_t *) _VRAM)[i] = (uint32_t) i;
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}
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end = MCF_SLT0_SCNT;
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time = (start - end) / (SYSCLK / 1000) / 1000;
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xprintf("finished (took %f seconds).\r\n", time / 1000.0);
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xprintf("read\r\n");
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start = MCF_SLT0_SCNT;
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hexdump((uint8_t *) _VRAM, 64);
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hexdump((uint8_t *) 0, 64);
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end = MCF_SLT0_SCNT;
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time = (start - end) / (SYSCLK / 1000) / 1000;
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@@ -172,66 +30,6 @@ void wait_for_jtag(void)
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{
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long i;
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/* set supervisor stack to end of SRAM1 */
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__asm__ __volatile__ (
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" move #0x2700,sr\n\t" /* disable interrupts */
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" move.l %[stack],d0\n\t" /* 4KB on-chip core SRAM1 */
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" move.l d0,sp\n\t" /* set stack pointer */
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:
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: [stack] "i" (SAFE_STACK)
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: "d0", "cc" /* clobber */
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);
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MCF_EPORT_EPIER = 0x0; /* disable EPORT interrupts */
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MCF_INTC_IMRL = 0xffffffff;
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MCF_INTC_IMRH = 0xffffffff; /* disable interrupt controller */
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MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */
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xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
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/*
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* configure FEC1L port directions to enable external JTAG configuration download to FPGA
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*/
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MCF_GPIO_PDDR_FEC1L = 0 |
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MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
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/* all other bits = input */
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/*
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* configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink
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*/
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MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3);
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/*
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* now that GPIO ports have been switched to input, we can poll for FPGA config
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* started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
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*/
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xprintf("waiting for JTAG configuration start\r\n");
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while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load started */
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xprintf("waiting for JTAG configuration to finish\r\n");
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while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */
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xprintf("JTAG configuration finished.\r\n");
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/* wait */
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xprintf("wait a little to let things settle...\r\n");
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for (i = 0; i < 100000L; i++);
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xprintf("disable caches\r\n");
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__asm__ __volatile(
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"move.l #0x01000000,d0 \r\n"
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"movec d0,CACR \r\n"
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: /* no output */
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: /* no input */
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: "d0", "memory");
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xprintf("init FPGA PLLs\r\n");
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init_pll();
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xprintf("init video DDR RAM\r\n");
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init_video_ddr();
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/* begin of tests */
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do_tests();
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xprintf("wait a little to let things settle...\r\n");
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@@ -266,13 +64,13 @@ int main(int argc, char *argv[])
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/*
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* seems to be a valid address
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*/
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bas_start = (long) addr;
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// bas_start = (long) addr;
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printf("BaS start address set to %p\r\n", (void *) bas_start);
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// printf("BaS start address set to %p\r\n", (void *) bas_start);
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}
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else
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{
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printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
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// printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
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}
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}
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Supexec(wait_for_jtag);
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