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fix formatting

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This commit is contained in:
Markus Fröschle
2017-04-15 08:29:05 +00:00
parent a1f77bf95f
commit 094634db16
1 changed files with 16 additions and 15 deletions
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13
BaS_gcc/radeon/radeon_base.c
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@@ -1494,9 +1494,9 @@ void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, in
/* Apply surface registers */
for (i = 0; i < 8; i++)
{
OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
OUTREG(SURFACE0_LOWER_BOUND + 0x10 * i, mode->surf_lower_bound[i]);
OUTREG(SURFACE0_UPPER_BOUND + 0x10 * i, mode->surf_upper_bound[i]);
OUTREG(SURFACE0_INFO + 0x10 * i, mode->surf_info[i]);
}
OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
@@ -1566,8 +1566,9 @@ static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs
{ 6, 6 },
{ 12, 7 },
{ 0, 0 },
};
int32_t fb_div, pll_output_freq = 0;
};
int32_t fb_div;
int32_t pll_output_freq = 0;
int32_t uses_dvo = 0;
/* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
@@ -1576,7 +1577,7 @@ static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs
*/
#if 1
/* XXX I had reports of flicker happening with the cinema display
* on TMDS1 that seem to be fixed if I also forbit odd dividers in
* on TMDS1 that seem to be fixed if I also forbid odd dividers in
* this case. This could just be a bandwidth calculation issue, I
* haven't implemented the bandwidth code yet, but in the meantime,
* forcing uses_dvo to 1 fixes it and shouln't have bad side effects,