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fixed a few MMU quirks

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This commit is contained in:
Markus Fröschle
2014-09-17 05:28:16 +00:00
parent 01141f4251
commit 02ab73f2cc
6 changed files with 316 additions and 308 deletions
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2
dma/dma.c
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@@ -39,7 +39,7 @@
#error "unknown machine!" #error "unknown machine!"
#endif /* MACHINE_FIREBEE */ #endif /* MACHINE_FIREBEE */
#define DBG_DMA //#define DBG_DMA
#ifdef DBG_DMA #ifdef DBG_DMA
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else #else

10
sys/cache.c
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@@ -32,7 +32,7 @@ void cacr_set(uint32_t value)
__asm__ __volatile__("movec %0, cacr\n\t" __asm__ __volatile__("movec %0, cacr\n\t"
: /* output */ : /* output */
: "r" (rt_cacr) : "r" (rt_cacr)
: /* clobbers */); : "memory" /* clobbers */);
} }
uint32_t cacr_get(void) uint32_t cacr_get(void)
@@ -45,7 +45,13 @@ uint32_t cacr_get(void)
void disable_data_cache(void) void disable_data_cache(void)
{ {
flush_and_invalidate_caches(); flush_and_invalidate_caches();
cacr_set(cacr_get() | CF_CACR_DCINVA); cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
}
void disable_instruction_cache(void)
{
flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
} }
void enable_data_cache(void) void enable_data_cache(void)

20
sys/exceptions.S
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@@ -758,15 +758,17 @@ irq7:
/* /*
* general purpose timer 0 (GPT0): video change, later also others. GPT0 is used as * general purpose timer 0 (GPT0): video change, later also others.
* input trigger. It is connected to the TIN0 signal of the FPGA and triggers everytime *
* vbasehi is written to, i.e. when the video base address gets changed * GPT0 is used as input trigger. It is connected to the TIN0 signal of
* the FPGA and triggers everytime vbasehi is written to, i.e.
* when the video base address gets changed
*/ */
handler_gpt0: handler_gpt0:
move #0x2700,sr // disable interrupts move #0x2700,sr // disable interrupts
lea -28(a7),a7 // save registers lea -7 * 4(sp),sp // save registers
movem.l d0-d4/a0-a1,(a7) movem.l d0-d4/a0-a1,(sp)
mvz.b vbasehi,d0 // screen base address high mvz.b vbasehi,d0 // screen base address high
cmp.w #2,d0 // screen base lower than 0x20000? cmp.w #2,d0 // screen base lower than 0x20000?
@@ -779,7 +781,7 @@ handler_gpt0:
move.l (a0),_video_sbt // save time move.l (a0),_video_sbt // save time
// FIXME: don't we need to get out here? // FIXME: don't we need to get out here?
bra video_chg_end // bra video_chg_end
sca_other: sca_other:
lsl.l #8,d0 // build new screen start address from Atari register contents lsl.l #8,d0 // build new screen start address from Atari register contents
@@ -840,7 +842,7 @@ video_chg_2page:
mvz.w 0xffff82a8,d1 // VDB: vertical display begin mvz.w 0xffff82a8,d1 // VDB: vertical display begin
sub.l d1,d2 // number of lines sub.l d1,d2 // number of lines
mulu d2,d4 // times number of words per line mulu d2,d4 // times number of words per line
add.l d4,d0 // video gr<EFBFBD>sse add.l d4,d0 // video memory end address
cmp.l #__STRAM_END,d0 // start address > end of STRAM? cmp.l #__STRAM_END,d0 // start address > end of STRAM?
bge video_chg_end // yes - we're finished bge video_chg_end // yes - we're finished
@@ -853,8 +855,8 @@ video_chg_2page:
jsr _flush_and_invalidate_caches jsr _flush_and_invalidate_caches
video_chg_end: video_chg_end:
lea MCF_GPT0_GMS,a0 // clear interrupt lea MCF_GPT0_GMS,a0 // disable and reenable timer
bclr.b #0,3(a0) bclr.b #0,3(a0) // input capture
nop nop
bset.b #0,3(a0) bset.b #0,3(a0)

2
sys/init_fpga.c
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@@ -27,7 +27,7 @@
#include "bas_printf.h" #include "bas_printf.h"
#include "wait.h" #include "wait.h"
#define FPGA_DEBUG // #define FPGA_DEBUG
#if defined(FPGA_DEBUG) #if defined(FPGA_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else #else

2
sys/interrupts.c
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@@ -38,7 +38,7 @@
extern void (*rt_vbr[])(void); extern void (*rt_vbr[])(void);
#define VBR rt_vbr #define VBR rt_vbr
#define IRQ_DEBUG //#define IRQ_DEBUG
#if defined(IRQ_DEBUG) #if defined(IRQ_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0) #define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
#else #else

4
sys/mmu.c
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@@ -62,7 +62,7 @@
#error "unknown machine!" #error "unknown machine!"
#endif /* MACHINE_FIREBEE */ #endif /* MACHINE_FIREBEE */
#define DEBUG_MMU // #define DEBUG_MMU
#ifdef DEBUG_MMU #ifdef DEBUG_MMU
#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0) #define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
#else #else
@@ -377,7 +377,7 @@ void mmu_init(void)
* Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
* virtual address. This is also used (completely) when BaS is in RAM * virtual address. This is also used (completely) when BaS is in RAM
*/ */
flags.cache_mode = CACHE_WRITETHROUGH; flags.cache_mode = CACHE_COPYBACK;
flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE; flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE;
mmu_map_page(SDRAM_START + SDRAM_SIZE - 0X00200000, SDRAM_START + SDRAM_SIZE - 0X00200000, MMU_PAGE_SIZE_1M, &flags); mmu_map_page(SDRAM_START + SDRAM_SIZE - 0X00200000, SDRAM_START + SDRAM_SIZE - 0X00200000, MMU_PAGE_SIZE_1M, &flags);