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fixed a few MMU quirks

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This commit is contained in:
Markus Fröschle
2014-09-17 05:28:16 +00:00
parent 01141f4251
commit 02ab73f2cc
6 changed files with 316 additions and 308 deletions
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154
sys/cache.c
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@@ -32,7 +32,7 @@ void cacr_set(uint32_t value)
__asm__ __volatile__("movec %0, cacr\n\t"
: /* output */
: "r" (rt_cacr)
: /* clobbers */);
: "memory" /* clobbers */);
}
uint32_t cacr_get(void)
@@ -44,35 +44,41 @@ uint32_t cacr_get(void)
void disable_data_cache(void)
{
flush_and_invalidate_caches();
cacr_set(cacr_get() | CF_CACR_DCINVA);
flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
}
void disable_instruction_cache(void)
{
flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
}
void enable_data_cache(void)
{
cacr_set(cacr_get() & ~CF_CACR_DCINVA);
cacr_set(cacr_get() & ~CF_CACR_DCINVA);
}
void flush_and_invalidate_caches(void)
{
__asm__ __volatile__(
" clr.l d0 \n\t"
" clr.l d1 \n\t"
" move.l d0,a0 \n\t"
"cfa_setloop: \n\t"
" cpushl bc,(a0) | flush\n\t"
" lea 0x10(a0),a0 | index+1\n\t"
" addq.l #1,d1 | index+1\n\t"
" cmpi.w #512,d1 | all sets?\n\t"
" bne.s cfa_setloop | no->\n\t"
" clr.l d1 \n\t"
" addq.l #1,d0 \n\t"
" move.l d0,a0 \n\t"
" cmpi.w #4,d0 | all ways?\n\t"
" bne.s cfa_setloop | no->\n\t"
/* input */ :
/* output */ :
/* clobber */ : "cc", "d0", "d1", "a0"
__asm__ __volatile__(
" clr.l d0 \n\t"
" clr.l d1 \n\t"
" move.l d0,a0 \n\t"
"cfa_setloop: \n\t"
" cpushl bc,(a0) | flush\n\t"
" lea 0x10(a0),a0 | index+1\n\t"
" addq.l #1,d1 | index+1\n\t"
" cmpi.w #512,d1 | all sets?\n\t"
" bne.s cfa_setloop | no->\n\t"
" clr.l d1 \n\t"
" addq.l #1,d0 \n\t"
" move.l d0,a0 \n\t"
" cmpi.w #4,d0 | all ways?\n\t"
" bne.s cfa_setloop | no->\n\t"
/* input */ :
/* output */ :
/* clobber */ : "cc", "d0", "d1", "a0"
);
}
@@ -92,35 +98,35 @@ void flush_icache_range(void *address, size_t size)
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3)) {
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set) /* input parameters */
: "cc" /* clobbered registers */
);
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set) /* input parameters */
: "cc" /* clobbered registers */
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_ICACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3)) {
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set])"
: /* output parameters */
: [set] "a" (set)
: "cc"
);
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set])"
: /* output parameters */
: [set] "a" (set)
: "cc"
);
}
}
@@ -142,37 +148,37 @@ void flush_dcache_range(void *address, size_t size)
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_DCACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq%.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
for (set = start_set; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq%.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
}