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Sync from Fredi's source tree 13/05/2017

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This commit is contained in:
David Gálvez
2018-04-09 16:26:54 +02:00
parent c1e31dcdf0
commit 030afcd535
59 changed files with 13625 additions and 1139 deletions
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336
sources/sysinit.c
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@@ -7,18 +7,20 @@
*/
#include "MCF5475.h"
#include "startcf.h"
#include "RuntimeConfig.h"
extern unsigned long far __VRAM;
extern unsigned long far __Bas_base;
extern unsigned long far BaS;
extern unsigned long far __BOOT_FLASH[];
extern int copy_end();
extern int warte_10us();
extern int warte_1ms();
extern int warte_10ms();
extern int warte_50us();
extern void warte_10us();
extern void warte_1ms();
extern void set_ide_access_mode();
extern unsigned long far rt_cacr;
extern unsigned long far rt_acr0;
extern unsigned long far rt_acr1;
extern unsigned long far rt_acr2;
extern unsigned long far rt_acr3;
extern unsigned long far rt_mmubar;
/********************************************************************/
// init SLICE TIMER 0
@@ -119,7 +121,17 @@ void init_seriel(void)
MCF_PSC3_PSCCR = 0x05;
MCF_INTC_ICR32 = 0x3F; //MAXIMALE PRIORITY/**********/
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = 0x0a0a0a0d;
MCF_PSC0_PSCTB_8BIT = 'BaS ';
MCF_PSC0_PSCTB_8BIT = '13.0';
MCF_PSC0_PSCTB_8BIT = '5.20';
MCF_PSC0_PSCTB_8BIT = '17';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = '====';
MCF_PSC0_PSCTB_8BIT = '====';
MCF_PSC0_PSCTB_8BIT = '====';
MCF_PSC0_PSCTB_8BIT = '==';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = 'SERI';
MCF_PSC0_PSCTB_8BIT = 'AL O';
MCF_PSC0_PSCTB_8BIT = 'K! ';
@@ -175,39 +187,43 @@ void init_ddram(void)
/********************************************************************/
void init_fbcs()
{
MCF_PSC0_PSCTB_8BIT = 'FBCS';
/* Flash */
MCF_FBCS0_CSAR = 0xE0000000; // FLASH ADRESS
MCF_FBCS0_CSCR = 0x00001180; // 16 bit 4ws aa
MCF_FBCS0_CSMR = 0x007F0001; // 8MB on
MCF_PSC0_PSCTB_8BIT = 'FBCS';
MCF_FBCS1_CSAR = 0xFFF00000; // ATARI I/O ADRESS
MCF_FBCS1_CSAR = 0xFFF80000; // FFF8'0000-FFFF'FFFF: ATARI I/O ADRESS
MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT
| MCF_FBCS_CSCR_WS(8) // DEFAULT 8WS
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_1M
| MCF_FBCS_CSCR_WS(63) // DEFAULT 63WS
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
| MCF_FBCS_CSMR_V);
MCF_FBCS2_CSAR = 0xF0000000; // NEUER I/O ADRESS-BEREICH
MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
| MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS
| MCF_FBCS_CSCR_WS(8) // DEFAULT 8WS
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M // F000'0000-F7FF'FFFF
| MCF_FBCS_CSMR_V);
MCF_FBCS3_CSAR = 0xF8000000; // NEUER I/O ADRESS-BEREICH
MCF_FBCS3_CSAR = 0xFFF00000; // IDE I/O ADRESS-BEREICH BURST!
MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT
| MCF_FBCS_CSCR_WS(16) // DEFAULT 16WS
| MCF_FBCS_CSCR_BSTR // Burst read enable
| MCF_FBCS_CSCR_BSTW // Burst write enable
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M // F800'0000-FBFF'FFFF
MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_512K // FFF0'0000-FFF7'FFFF
| MCF_FBCS_CSMR_V);
MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BEN<45>TZT, DECODE DIREKT AUF DEM FPGA
MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH,
MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
| MCF_FBCS_CSCR_BSTR // BURST READ ENABLE
| MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE
MCF_FBCS4_CSMR = (MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF
| MCF_FBCS_CSMR_V);
/* Flash */
MCF_FBCS0_CSAR = 0xE0000000; // FLASH ADRESS
MCF_FBCS0_CSCR = 0x00001180; // 16 bit 4ws aa
MCF_FBCS0_CSMR = 0x007F0001; // 8MB on
MCF_PSC0_PSCTB_8BIT = ' OK!';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
@@ -241,23 +257,87 @@ test_STATUS:
jsr warte_10us // warten
lea 0xE0700000,a0 // startadresse fpga daten
moveq #0x4,d2
moveq #0x6,d3
moveq #0xc,d4
moveq #0xe,d5
word_send_loop:
cmp.l #0xE0800000,a0
bgt fpga_error
move.b (a0)+,d0 // 32 bit holen
moveq #8,d1 // 32 bit ausgeben
bit_send_loop:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_1
bclr #3,(a1)
bra bit_send
bit_is_1:
bset #3,(a1)
bit_send:
bset #1,(a1) // clock=high
bclr #1,(a1) // clock=low
subq.l #1,d1
bne bit_send_loop // wiederholen bis fertig
bcs bit_is_10 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send0
bit_is_10:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send0:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_11 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send1
bit_is_11:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send1:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_12 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send2
bit_is_12:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send2:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_13 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send3
bit_is_13:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send3:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_14 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send4
bit_is_14:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send4:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_15 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send5
bit_is_15:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send5:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_16 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send6
bit_is_16:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send6:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_17 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send7
bit_is_17:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send7:
// test auf fertig
btst #5,(a2) // fpga fertig, conf_done=high?
beq word_send_loop // nein, next word->
move.l #4000,d1
@@ -267,8 +347,31 @@ overclk:
bclr #1,(a1) // clock=low
subq.l #1,d1
bne overclk // weiter bis fertig
// datum des FPGA files ausgeben
jsr warte_10us // warten
lea MCF_PSC0_PSCTB_8BIT,a3
move.l #': Da',(a3)
move.l #'te: ',(a3)
move.l 0xf0040100,d1
moveq #8,d0
date_loop:
btst #0,d0
bne kein_punkt
btst #2,d0
beq kein_punkt
move.b #'.',(a3)
kein_punkt:
move.l d0,d3 // index
subq.l #1,d3 // -1
lsl.l #2,d3 // *2
move.l d1,d2
lsr.l d3,d2 // und schieben
and.l #0x0f,d2
add.l #'0',d2
move.b d2,(a3)
subq.l #1,d0
bgt date_loop
bra init_fpga_end
//---------------------------------------------------------
wait_pll:
lea MCF_SLT0_SCNT,a3
@@ -322,7 +425,7 @@ asm
move.w #1,0x44(a0) // M low = 1
bsr wait_pll
move.w #145,0x04(a0) // M high = 145 = 146MHz
move.w #65,0x04(a0) // M high = 65 = 65MHz
bsr wait_pll
clr.b (a1) // set
@@ -368,7 +471,7 @@ void init_video_ddr(void)
/********************************************************************/
/* video mit aufl<66>sung 1280x1000 137MHz /*
/********************************************************************/
/*
void video_1280_1024(void)
{
extern int wait_pll;
@@ -381,7 +484,7 @@ extern int wait_pll;
//testmuster 1
lea __VRAM,a2
lea __VRAM+0x600000,a3
lea __VRAM+0x120000,a3
clr.l d0
move.l #0x1000102,d1
loop5: move.l d0,(a2)+
@@ -409,35 +512,48 @@ flo6: cmp.l a2,a3
bgt loop5
// screen setzen
//horizontal 1280
//horizontal 1024
lea 0xffff8282,a0
move.w #1800,(a0)+
move.w #1380,(a0)+
move.w #99,(a0)+
move.w #100,(a0)+
move.w #1379,(a0)+
move.w #1500,(a0)
//vertical 1024
move.w #1344,(a0)+
move.w #1184,(a0)+
move.w #159,(a0)+
move.w #160,(a0)+
move.w #1183,(a0)+
move.w #1208,(a0)
//vertical 768
lea 0xffff82a2,a0
move.w #1150,(a0)+
move.w #1074,(a0)+
move.w #49,(a0)+
move.w #50,(a0)+
move.w #1073,(a0)+
move.w #1100,(a0)+
move.w #806,(a0)+
move.w #797,(a0)+
move.w #28,(a0)+
move.w #29,(a0)+
move.w #796,(a0)+
move.w #800,(a0)+
// acp video on
move.l #0x01070207,d0
move.l #0x0107820b,d0 // acp video, color1, pll pixelclk, dac on
move.l d0,0xf0000400
lea 0xffff8200,a0
clr.w (a0)
clr.b 3(a0)
clr.b 0xd(a0)
move.w #0x400,10(a0)
move.w #0x182,0xc0(a0)
clr.w 0xc2(a0)
// clut setzen
lea 0xf0000000,a0
move.l #0xffffffff,(a0)+
move.l #0xff,(a0)+
move.l #0xff00,(a0)+
move.l #0xff0000,(a0)
// halt
/*
lea 0xffff8200,a0
move.w #6,0xc0(a0)
move.w #7,0x40(a0)
move.w #7,0x42(a0)
move.w #7,0x44(a0)
move.w #7,0x46(a0)
move.b #1,0x60(a0)
halt
}
@@ -767,70 +883,64 @@ ac97_end:
}
/********************************************************************/
void __initialize_hardware(void)
{
_init_hardware:
asm
{
// instruction cache on
move.l #0x000C8120,d0
init_ddram();
asm
{
// instruction cache on
move.l #0x007fe000,d0
movec d0,acr0
move.l d0,rt_acr0
movec d0,acr2
move.l d0,rt_acr2
clr.l d0
movec d0,acr1
move.l d0,rt_acr1
movec d0,acr3
move.l d0,rt_acr3
move.l d0,MCF_MMU_MMUCR
move.l #0x050c8120,d0
move.l d0,rt_cacr
movec d0,cacr
nop
}
init_gpio();
init_seriel();
init_slt();
init_fbcs();
init_ddram();
// Ports nicht initialisieren wenn DIP Switch 5 = on
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq not_init_ports
}
}
init_gpio();
init_seriel();
init_slt();
init_fbcs();
init_fpga();
init_video_ddr();
vdi_on();
// Ports nicht initialisieren wenn DIP Switch 6 = on
asm
{
// IDE reset
lea 0xffff8802,a0 // IDE reset
move.b #14,-2(a0)
move.b #0x80,(a0)
bsr warte_1ms
clr.b (a0)
// dip switch
move.b DIP_SWITCH,d0 // dip schalter adresse
move.b d0,0xF0040002 // acp conf +2
// ACP_CONF setzen und Ports nicht initialisieren wenn DIP Switch 6 = on
btst.b #6,d0
beq not_init_ports
}
init_PCI(); //pci braucht zeit
not_init_ports:
init_fpga();
init_video_ddr();
vdi_on();
// Ports nicht initialisieren wenn DIP Switch 5 = on
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq not_init_ports2
}
test_upd720101();
// video_1280_1024();
init_ac97();
not_init_ports2:
test_upd720101();
// video_1280_1024();
asm
{
not_init_ports:
}
set_ide_access_mode();
asm
{
/*****************************************************/
/* BaS kopieren
/*****************************************************/
lea copy_start,a0
lea BaS,a1
sub.l a0,a1
move.l #__Bas_base,a2
move.l a2,a3
add.l a1,a3
lea copy_end,a4
BaS_kopieren_loop: // immer 16 bytes
move.l (a0)+,(a2)+
move.l (a0)+,(a2)+
move.l (a0)+,(a2)+
move.l (a0)+,(a2)+
cmp.l a4,a0
blt BaS_kopieren_loop
/*****************************************************/
jmp (a3)
copy_start:
/********************************************************************/
}
}