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Sync from Fredi's source tree 13/05/2017

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This commit is contained in:
David Gálvez
2018-04-09 16:26:54 +02:00
parent c1e31dcdf0
commit 030afcd535
59 changed files with 13625 additions and 1139 deletions
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350
sources/alt und div/BaS.c.neu Normal file
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/*
* BaS
*
*/
#include "MCF5475.h"
#include "startcf.h"
#include "MCD_dma.h"
#define MBAR_BASE_ADRS 0xff000000
#define MMAP_DMA 0x00008000
#define MMAP_SRAM 0x00010000
extern unsigned long far __SP_AFTER_RESET[];
extern unsigned long far __Bas_base[];
/* imported routines */
extern int mmu_init();
extern int mmutr_miss();
extern int vec_init();
extern int illegal_table_make();
extern int cf68k_initialize();
/********************************************************************/
/* warte_routinen /*
********************************************************************/
void warte_10ms(void)
{
asm
{
warte_10ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_1ms(void)
{
asm
{
warte_1ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_100us(void)
{
asm
{
warte_100us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #13200,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_50us(void)
{
asm
{
warte_50us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #6600,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_10us(void)
{
asm
{
warte_10us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_1us(void)
{
asm
{
warte_1us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
/********************************************************************/
void BaS(void)
{
int az_sectors;
int sd_status,i;
int status;
int dma_task_nr = 0;
az_sectors = sd_card_init();
if(az_sectors>0)
{
sd_card_idle();
}
/* variablenbereich setzen*/
asm
{
lea 0x1fc00000,a5
lea 0x1fd00000,a6
}
init_dma:
status =
MCD_initDma(
(dmaRegs*) (MBAR_BASE_ADRS + MMAP_DMA),
(void*) (MBAR_BASE_ADRS + MMAP_SRAM),
(MCD_RELOC_TASKS)
);
status = MCD_startDma(0, /*int channel, /* the channel on which to run the DMA */
(char*) (0xfff00000), /*s8 *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
0, /*s16 srcIncr, /* the amount to increment the source address per transfer */
(char*) (0x12345678), /*s8 *destAddr, /* the address to move data to */
2, /*s16 destIncr, /* the amount to increment the destination address per transfer */
512, /*u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
2, /*u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
3, /*u32 initiator, /* what device initiates the DMA */
4, /*int priority, /* priority of the DMA */
MCD_SINGLE_DMA+
MCD_TT_FLAGS_CW+
MCD_TT_FLAGS_RL+
MCD_TT_FLAGS_SP, /*u32 flags, /* flags describing the DMA */
MCD_NO_BYTE_SWAP+
MCD_NO_BIT_REV /*u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
);
status =
MCD_dmaStatus(0);
MCD_killDma(0);
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq firetos_kopieren
lea MCF_PSC0_PSCTB_8BIT,a6
lea MCF_PSC3_PSCTB_8BIT,a3
lea MCF_PSC3_PSCRB_8BIT,a4
lea MCF_PSC3_PSCRFCNT,a5
move.l #'ACPF',(a3) // SEND SYNC MARKE, MCF BEREIT
bsr warte_10ms
move.l #'PIC ',(a6)
move.b (a4),d0
move.b d0,(a6)
move.b (a4),d1
move.b d1,(a6)
move.b (a4),d2
move.b d2,(a6)
move.l #0x0a0d,(a6)
move.b #0x01,(a3) // RTC DATEN ANFORDERN
// TOS kopieren
lea 0x00e00000,a0
lea 0xe0600000,a1 // default tos
lea 0xe0700000,a2 // 1MB
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
bne cptos_loop
firetos_kopieren:
lea 0x00e00000,a0
lea 0xe0400000,a1
lea 0xe0500000,a2 // 1MB
cptos_loop:
move.l (a1)+,(a0)+
cmp.l a2,a1
blt cptos_loop
/***************************************************************/
/* div inits
/***************************************************************/
div_inits:
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq video_setup
// rtc daten, mmu set, etc nur wenn switch 6 = off
lea 0xffff8961,a0
clr.l d1
moveq #64,d2
move.b (a4),d0
cmp.b #0x81,d0
bne not_rtc
loop_sr:
move.b (a4),d0
move.b d1,(a0)
move.b d0,2(a0)
addq.l #1,d1
cmp.b d1,d2
bne loop_sr
move.b #63,(a0)
move.b 2(a0),d0
add #1,d0
move.b d0,2(a0)
not_rtc:
bsr mmu_init
bsr vec_init
bsr illegal_table_make
// interrupts
clr.l 0xf0010004 // disable all interrupts
lea MCF_EPORT_EPPAR,a0
move.w #0xaaa8,(a0) // falling edge all,
// timer 0 on mit int -> video change -------------------------------------------
move.l #MCF_GPT_GMS_ICT(1)|MCF_GPT_GMS_IEN|MCF_GPT_GMS_TMS(1),d0 //caputre mit int on rising edge
move.l d0,MCF_GPT0_GMS
moveq.l #0x3f,d0 // max prority interrutp
move.b d0,MCF_INTC_ICR62 // setzen
// -------------------------------------------------
move.b #0xfe,d0
move.b d0,0xf0010004 // enable int 1-7
nop
lea MCF_EPORT_EPIER,a0
move.b #0xfe,(a0) // int 1-7 on
nop
lea MCF_EPORT_EPFR,a0
move.b #0xff,(a0) // alle pending interrupts löschen
nop
lea MCF_INTC_IMRL,a0
move.l #0xFFFFFF00,(a0) // int 1-7 on
lea MCF_INTC_IMRH,a0
move.l #0xBFFFFFFE,(a0) // psc3 and timer 0 int on
move.l #MCF_MMU_MMUCR_EN,d0
move.l d0,MCF_MMU_MMUCR // mmu on
nop
nop
/********************************************************************/
/* IDE reset
/********************************************************************/
lea 0xffff8802,a0
move.b #14,-2(a0)
move.b #0x80,(a0)
bsr warte_1ms
clr.b (a0)
/********************************************************************/
/* video setup
/********************************************************************/
video_setup:
lea 0xf0000410,a0
// 25MHz
move.l #0x032002ba,(a0)+ // horizontal 640x480
move.l #0x020c020a,(a0)+ // vertikal 640x480
move.l #0x0190015d,(a0)+ // horizontal 320x240
move.l #0x020C020A,(a0)+ // vertikal 320x240 */
/*
// 32MHz
move.l #0x037002ba,(a0)+ // horizontal 640x480
move.l #0x020d020a,(a0)+ // vertikal 640x480
move.l #0x02A001e0,(a0)+ // horizontal 320x240
move.l #0x05a00160,(a0)+ // vertikal 320x240
*/
lea -0x20(a0),a0
move.l #0x01070002,(a0) // fifo on, refresh on, ddrcs und cke on, video dac on,
/********************************************************************/
/* memory setup
/********************************************************************/
lea 0x400,a0
lea 0x800,a1
mem_clr_loop:
clr.l (a0)+
clr.l (a0)+
clr.l (a0)+
clr.l (a0)+
cmp.l a0,a1
bgt mem_clr_loop
moveq #0x48,d0
move.b d0,0xffff8007
// stram
move.l #0xe00000,d0 // ende stram
move.l d0,0x42e
move.l #0x752019f3,d0 // memvalid
move.l d0,0x420
move.l #0x237698aa,d0 // memval2
move.l d0,0x43a
move.l #0x5555aaaa,d0 // memval3
move.l d0,0x51a
// ttram
move.l #__Bas_base,d0 // ende ttram
move.l d0,0x5a4
move.l #0x1357bd13,d0 // ramvalid
move.l d0,0x5a8
// init acia
moveq #3,d0
move.b d0,0xfffffc00
nop
move.b d0,0xfffffc04
nop
moveq #0x96,d0
move.b d0,0xfffffc00
moveq #-1,d0
nop
move.b d0,0xfffffa0f
nop
move.b d0,0xfffffa11
nop
// test auf protect mode ---------------------
move.b DIP_SWITCH,d0
btst #7,d0
beq no_protect // nein->
move.w #0x0700,sr
no_protect:
jmp 0xe00030
}
}

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/*
* BaS
*
*/
#include "MCF5475.h"
#include "startcf.h"
#include "MCD_dma.h"
#define MBAR_BASE_ADRS 0xff000000
#define MMAP_DMA 0x00008000
#define MMAP_SRAM 0x00010000
extern unsigned long far __SP_AFTER_RESET[];
extern unsigned long far __Bas_base[];
/* imported routines */
extern int mmu_init();
extern int mmutr_miss();
extern int vec_init();
extern int illegal_table_make();
extern int cf68k_initialize();
/********************************************************************/
/* warte_routinen /*
********************************************************************/
void warte_10ms(void)
{
asm
{
warte_10ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_1ms(void)
{
asm
{
warte_1ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_100us(void)
{
asm
{
warte_100us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #13200,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_50us(void)
{
asm
{
warte_50us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #6600,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_10us(void)
{
asm
{
warte_10us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_1us(void)
{
asm
{
warte_1us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
/********************************************************************/
void BaS(void)
{
int az_sectors;
int sd_status,i;
int status;
int dma_task_nr = 0;
az_sectors = sd_card_init();
if(az_sectors>0)
{
sd_card_idle();
}
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq firetos_kopieren
lea MCF_PSC0_PSCTB_8BIT,a6
lea MCF_PSC3_PSCTB_8BIT,a3
lea MCF_PSC3_PSCRB_8BIT,a4
lea MCF_PSC3_PSCRFCNT,a5
move.l #'ACPF',(a3) // SEND SYNC MARKE, MCF BEREIT
bsr warte_10ms
move.l #'PIC ',(a6)
move.b (a4),d0
move.b d0,(a6)
move.b (a4),d1
move.b d1,(a6)
move.b (a4),d2
move.b d2,(a6)
move.l #0x0a0d,(a6)
move.b #0x01,(a3) // RTC DATEN ANFORDERN
// TOS kopieren
lea 0x00e00000,a0
lea 0xe0600000,a1 // default tos
lea 0xe0700000,a2 // 1MB
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
bne cptos_loop
firetos_kopieren:
lea 0x00e00000,a0
lea 0xe0400000,a1
lea 0xe0500000,a2 // 1MB
cptos_loop:
move.l (a1)+,(a0)+
cmp.l a2,a1
blt cptos_loop
/***************************************************************/
/* div inits
/***************************************************************/
div_inits:
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq video_setup
// rtc daten, mmu set, etc nur wenn switch 6 = off
lea 0xffff8961,a0
clr.l d1
moveq #64,d2
move.b (a4),d0
cmp.b #0x81,d0
bne not_rtc
loop_sr:
move.b (a4),d0
move.b d1,(a0)
move.b d0,2(a0)
addq.l #1,d1
cmp.b d1,d2
bne loop_sr
move.b #63,(a0)
move.b 2(a0),d0
add #1,d0
move.b d0,2(a0)
not_rtc:
bsr mmu_init
bsr vec_init
bsr illegal_table_make
// interrupts
clr.l 0xf0010004 // disable all interrupts
lea MCF_EPORT_EPPAR,a0
move.w #0xaaa8,(a0) // falling edge all,
// timer 0 on mit int -> video change -------------------------------------------
move.l #MCF_GPT_GMS_ICT(1)|MCF_GPT_GMS_IEN|MCF_GPT_GMS_TMS(1),d0 //caputre mit int on rising edge
move.l d0,MCF_GPT0_GMS
moveq.l #0x3f,d0 // max prority interrutp
move.b d0,MCF_INTC_ICR62 // setzen
// -------------------------------------------------
move.b #0xfe,d0
move.b d0,0xf0010004 // enable int 1-7
nop
lea MCF_EPORT_EPIER,a0
move.b #0xfe,(a0) // int 1-7 on
nop
lea MCF_EPORT_EPFR,a0
move.b #0xff,(a0) // alle pending interrupts löschen
nop
lea MCF_INTC_IMRL,a0
move.l #0xFFFFFF00,(a0) // int 1-7 on
lea MCF_INTC_IMRH,a0
move.l #0xBFFFFFFE,(a0) // psc3 and timer 0 int on
move.l #MCF_MMU_MMUCR_EN,d0
move.l d0,MCF_MMU_MMUCR // mmu on
nop
nop
/********************************************************************/
/* IDE reset
/********************************************************************/
lea 0xffff8802,a0
move.b #14,-2(a0)
move.b #0x80,(a0)
bsr warte_1ms
clr.b (a0)
/********************************************************************/
/* video setup
/********************************************************************/
video_setup:
lea 0xf0000410,a0
// 25MHz
move.l #0x032002ba,(a0)+ // horizontal 640x480
move.l #0x020c020a,(a0)+ // vertikal 640x480
move.l #0x0190015d,(a0)+ // horizontal 320x240
move.l #0x020C020A,(a0)+ // vertikal 320x240 */
/*
// 32MHz
move.l #0x037002ba,(a0)+ // horizontal 640x480
move.l #0x020d020a,(a0)+ // vertikal 640x480
move.l #0x02A001e0,(a0)+ // horizontal 320x240
move.l #0x05a00160,(a0)+ // vertikal 320x240
*/
lea -0x20(a0),a0
move.l #0x01070002,(a0) // fifo on, refresh on, ddrcs und cke on, video dac on,
/********************************************************************/
/* memory setup
/********************************************************************/
lea 0x400,a0
lea 0x800,a1
mem_clr_loop:
clr.l (a0)+
clr.l (a0)+
clr.l (a0)+
clr.l (a0)+
cmp.l a0,a1
bgt mem_clr_loop
moveq #0x48,d0
move.b d0,0xffff8007
// stram
move.l #0xe00000,d0 // ende stram
move.l d0,0x42e
move.l #0x752019f3,d0 // memvalid
move.l d0,0x420
move.l #0x237698aa,d0 // memval2
move.l d0,0x43a
move.l #0x5555aaaa,d0 // memval3
move.l d0,0x51a
// ttram
move.l #__Bas_base,d0 // ende ttram
move.l d0,0x5a4
move.l #0x1357bd13,d0 // ramvalid
move.l d0,0x5a8
// init acia
moveq #3,d0
move.b d0,0xfffffc00
nop
move.b d0,0xfffffc04
nop
moveq #0x96,d0
move.b d0,0xfffffc00
moveq #-1,d0
nop
move.b d0,0xfffffa0f
nop
move.b d0,0xfffffa11
nop
// test auf protect mode ---------------------
move.b DIP_SWITCH,d0
btst #7,d0
beq no_protect // nein->
move.w #0x0700,sr
no_protect:
jmp 0xe00030
}
}

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#include "MCF5475.h"
#include "startcf.h"
extern unsigned long far __SP_AFTER_RESET[];
extern unsigned long far __Bas_base[];
/* imported routines */
//extern int warten_20ms();
//extern int warten_200us();
//extern int warten_10us();
/********************************************************************/
void asm sd_test(void)
{
clr.w MCF_PAD_PAR_DSPI
lea MCF_GPIO_PPDSDR_DSPI,a2 // data in
lea MCF_GPIO_PODR_DSPI,a1 // data out
move.b #0x00,(a1) // alle auf 0
lea MCF_GPIO_PDDR_DSPI,a0
move.b #0x7d,(a0) // din = input rest output
bsr warten_20ms
move.b #0x7f,(a1) // alle auf 1
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
// sd idle
sd_idle:
bsr sd_16clk
moveq #0x40,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x95,d4
bsr sd_com
bsr sd_receive
cmp.b #0x05,d5
beq sd_test
cmp.b #0x01,d5
beq wait_of_aktiv
cmp.b #0x04,d5
beq sd_init_ok
cmp.b #0x00,d5
beq sd_init_ok
bra sd_idle
// acdm 41
wait_of_aktiv:
bsr sd_16clk
moveq #0x77,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
bsr sd_16clk
move.l #0xff,d6
moveq #0x69,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #0x02,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #0x01,d4
bsr sd_com
and d5,d6
bsr sd_receive
cmp.b #0x00,d5
beq sd_init_ok
cmp.b #0x05,d5
beq sd_test
bra wait_of_aktiv
sd_init_ok:
// blockgrösse 512byt
sd_bg:
bsr sd_16clk
moveq #0x50,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #02,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_bg
// read block
sd_rb:
bsr sd_16clk
moveq #0x51,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_rb
lea 0xc00000,a4
move.l #513,d7
rd_rb:
bsr sd_receive
move.b d5,(a4)+
subq.l #1,d7
bne rd_rb
// write block
sd_wb:
bsr sd_16clk
moveq #0x58,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_wb
lea 0xc00000,a4
move.l #513,d7
moveq.l #0x66,d4
wr_wb:
bsr sd_com
// subq.l #1,d4
moveq #0x66,d4
subq.l #1,d7
bne wr_wb
bsr sd_receive
wr_wb_el:
moveq #0xff,d4
bsr sd_com
cmp.b #0xff,d5
bne wr_wb_el
// read block 2
sd_rb2:
bsr sd_16clk
moveq #0x51,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_rb2
lea 0xc00400,a4
move.l #513,d7
rd_rb2:
bsr sd_receive
move.b d5,(a4)+
subq.l #1,d7
bne rd_rb2
nop
nop
rts
sd_receive:
moveq #0xff,d4
bsr sd_com
cmp.b #0xff,d5
beq sd_receive
rts
sd_com:
bclr.b #6,(a1)
sd_comb:
bsr warten_10us
moveq #7,d2
clr.l d5
sd_com_loop:
btst d2,d4
beq sd_com2
bset.b #0,(a1)
bra sd_com2_1
sd_com2:
bclr.b #0,(a1)
sd_com2_1:
bsr sd_clk
and.l #0x02,d3
beq sd_com3
bset.b d2,d5
sd_com3:
subq.l #1,d2
bge sd_com_loop
bsr warten_10us
bset.b #6,(a1)
bset.b #0,(a1)
bsr warten_200us
rts
sd_clk:
tst.b 0xfffff700
tst.b 0xfffff700
bset.b #2,(a1)
tst.b 0xfffff700
tst.b 0xfffff700
move.b (a2),d3
tst.b 0xfffff700
bclr.b #2,(a1)
rts
sd_15clk:
move #15,d0
bra sd_16clk
sd_16clk:
moveq #16,d0
sd_16clk1:
bsr sd_clk
subq.l #1,d0
bne sd_16clk1
bsr warten_10us
rts
// warteschleife ca. 20ms
warten_20ms:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #700000,d6
bra warten_loop
// warteschleife ca. 200us
warten_200us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #7000,d6
bra warten_loop
// warteschleife ca. 10us
warten_10us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #333,d6
warten_loop:
move.l (a0),d1
sub.l d0,d1
add.l d6,d1
bpl warten_loop
move.l (sp)+,d0
move.l (sp)+,d1
move.l (sp)+,d6
move.l (sp)+,a0
rts;
}
/**************************************************/
void asm ide_test(void)
{
lea MCF_PAD_PAR_DSPI,a0
move.w #0x1fff,(a0)
lea MCF_DSPI_DCTAR0,a0
move.l #0x38a644e4,(a0)
lea MCF_DSPI_DMCR,a0
move.l #0x802d3c00,(a0)
clr.l MCF_DSPI_DTCR
bsr warten_20ms
lea MCF_DSPI_DTFR,a0
lea MCF_DSPI_DRFR,a1
moveq #10,d0
sd_reset:
move.l #0x000100ff,(a0)
bsr warten_20ms
and.l (a1),d0
subq.l #1,d0
bne sd_reset
moveq #10,d1
sd_loop1:
bsr warten_20ms
moveq #-1,d0
// cmd 0 set to idle
move.l #0x00200040,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200095,(a0)
bsr warten_20ms
and.l (a1),d0
cmp.w #0x0001,d0
beq sd_loop2
subq.l #1,d1
bne sd_loop1
moveq #10,d1
bra sd_test
sd_loop2:
moveq #-1,d0
// cmd 41
move.l #0x00200069,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200001,(a0)
bsr warten_20ms
and.l (a1),d0
tst.w d0
bne sd_loop2
nop
nop
/********************************************************************/
#define cmd_reg (0x1d)
#define status_reg (0x1d)
#define seccnt (0x09)
ide_test:
lea 0xfff00040,a0
lea 0xc00000,a1
move.b #0xec,cmd_reg(a0) //identify devcie cmd
bsr wait_int
bsr ds_rx
// read sector normal
move.b #1,seccnt(a0) // 1 sector
move.b #0x20,cmd_reg(a0) // read cmd
bsr wait_int
bsr ds_rx
// write testpattern sector
move.b #1,seccnt(a0) // 1 sector
move.b #0x30,cmd_reg(a0) // write cmd
bsr drq_wait
// write pattern
move.l #256,d0
ide_test_loop3:
move.w #0xa55a,(a0)
subq.l #1,d0
bne ide_test_loop3
bsr wait_int
// read testpattern sector
move.b #1,seccnt(a0) // 1 sector
move.b #0x20,cmd_reg(a0) // read
bsr wait_int
bsr ds_rx
// sector restauriern
move.b #1,seccnt(a0) // 1 sector
move.b #0x30,cmd_reg(a0) // write
lea -0x400(a1),a1 // vorletzer
bsr drq_wait
bsr ds_tx
bsr wait_int
// fertig und zurück
nop
rts
// wait auf int
wait_int:
move.b 0xfffffa01,d0
btst.b #5,d0
bne wait_int
move.b status_reg(a0),d0
rts
// wait auf drq
drq_wait:
move.b status_reg(a0),d0
btst #3,d0
beq drq_wait
rts
// 1 sector lesen word
ds_rx:
move.l #256,d0
ds_rx_loop:
move.w (a0),(a1)+
subq.l #1,d0
bne ds_rx_loop
rts
// 1 sector lesen long
ds_rxl:
move.l #128,d0
ds_rxl_loop:
move.l (a0),(a1)+
subq.l #1,d0
bne ds_rxl_loop
rts
// 1 sector schreiben word
ds_tx:
move.l #256,d0
ds_tx_loop:
move.w (a1)+,(a0)
subq.l #1,d0
bne ds_tx_loop
rts
// 1 sector schreiben word
ds_txl:
move.l #128,d0
ds_txl_loop:
move.l (a1)+,(a0)
subq.l #1,d0
bne ds_txl_loop
rts
// warteschleife ca. 20ms
warten_20ms:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #700000,d6
bra warten_loop
// warteschleife ca. 200us
warten_200us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #7000,d6
bra warten_loop
// warteschleife ca. 10us
warten_10us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #333,d6
warten_loop:
move.l (a0),d1
sub.l d0,d1
add.l d6,d1
bpl warten_loop
move.l (sp)+,d0
move.l (sp)+,d1
move.l (sp)+,d6
move.l (sp)+,a0
rts;
}
/********************************************************************/