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Sync from Fredi's source tree 13/05/2017

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This commit is contained in:
David Gálvez
2018-04-09 16:26:54 +02:00
parent c1e31dcdf0
commit 030afcd535
59 changed files with 13625 additions and 1139 deletions
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362
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/*
* File: MCD_dma.h
* Purpose: Main header file for multi-channel DMA API.
*
* Notes:
*/
#ifndef _MCD_API_H
#define _MCD_API_H
/*
* Turn Execution Unit tasks ON (#define) or OFF (#undef)
*/
#undef MCD_INCLUDE_EU
/*
* Number of DMA channels
*/
#define NCHANNELS 16
/*
* Total number of variants
*/
#ifdef MCD_INCLUDE_EU
#define NUMOFVARIANTS 6
#else
#define NUMOFVARIANTS 4
#endif
/*
* Define sizes of the various tables
*/
#define TASK_TABLE_SIZE (NCHANNELS*32)
#define VAR_TAB_SIZE (128)
#define CONTEXT_SAVE_SIZE (128)
#define FUNCDESC_TAB_SIZE (256)
#ifdef MCD_INCLUDE_EU
#define FUNCDESC_TAB_NUM 16
#else
#define FUNCDESC_TAB_NUM 1
#endif
#ifndef DEFINESONLY
/*
* Portability typedefs
*/
typedef int s32;
typedef unsigned int u32;
typedef short s16;
typedef unsigned short u16;
typedef char s8;
typedef unsigned char u8;
/*
* These structures represent the internal registers of the
* multi-channel DMA
*/
struct dmaRegs_s {
u32 taskbar; /* task table base address register */
u32 currPtr;
u32 endPtr;
u32 varTablePtr;
u16 dma_rsvd0;
u16 ptdControl; /* ptd control */
u32 intPending; /* interrupt pending register */
u32 intMask; /* interrupt mask register */
u16 taskControl[16]; /* task control registers */
u8 priority[32]; /* priority registers */
u32 initiatorMux; /* initiator mux control */
u32 taskSize0; /* task size control register 0. */
u32 taskSize1; /* task size control register 1. */
u32 dma_rsvd1; /* reserved */
u32 dma_rsvd2; /* reserved */
u32 debugComp1; /* debug comparator 1 */
u32 debugComp2; /* debug comparator 2 */
u32 debugControl; /* debug control */
u32 debugStatus; /* debug status */
u32 ptdDebug; /* priority task decode debug */
u32 dma_rsvd3[31]; /* reserved */
};
typedef volatile struct dmaRegs_s dmaRegs;
#endif
/*
* PTD contrl reg bits
*/
#define PTD_CTL_TSK_PRI 0x8000
#define PTD_CTL_COMM_PREFETCH 0x0001
/*
* Task Control reg bits and field masks
*/
#define TASK_CTL_EN 0x8000
#define TASK_CTL_VALID 0x4000
#define TASK_CTL_ALWAYS 0x2000
#define TASK_CTL_INIT_MASK 0x1f00
#define TASK_CTL_ASTRT 0x0080
#define TASK_CTL_HIPRITSKEN 0x0040
#define TASK_CTL_HLDINITNUM 0x0020
#define TASK_CTL_ASTSKNUM_MASK 0x000f
/*
* Priority reg bits and field masks
*/
#define PRIORITY_HLD 0x80
#define PRIORITY_PRI_MASK 0x07
/*
* Debug Control reg bits and field masks
*/
#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
#define DBG_CTL_AUTO_ARM 0x00008000
#define DBG_CTL_BREAK 0x00004000
#define DBG_CTL_COMP1_TYP_MASK 0x00003800
#define DBG_CTL_COMP2_TYP_MASK 0x00000070
#define DBG_CTL_EXT_BREAK 0x00000004
#define DBG_CTL_INT_BREAK 0x00000002
/*
* PTD Debug reg selector addresses
* This reg must be written with a value to show the contents of
* one of the desired internal register.
*/
#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
have initiators asserted */
/*
* General return values
*/
#define MCD_OK 0
#define MCD_ERROR -1
#define MCD_TABLE_UNALIGNED -2
#define MCD_CHANNEL_INVALID -3
/*
* MCD_initDma input flags
*/
#define MCD_RELOC_TASKS 0x00000001
#define MCD_NO_RELOC_TASKS 0x00000000
#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */
/*
* MCD_dmaStatus Status Values for each channel
*/
#define MCD_NO_DMA 1 /* No DMA has been requested since reset */
#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */
#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
#define MCD_PAUSED 4 /* DMA active but it is currently paused */
#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */
#define MCD_DONE 6 /* the most recent DMA has completed. */
/*
* MCD_startDma parameter defines
*/
/*
* Constants for the funcDesc parameter
*/
/* Byte swapping: */
#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */
#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */
#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of
each 32-bit data value being DMAed.*/
#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each
16-bit half of each 32-bit data value DMAed */
#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */
#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */
/* CRCing: */
#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */
#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */
#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */
#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/
#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */
#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
/*
* Constants for the flags parameter
*/
#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */
#define MCD_TT_FLAGS_MASK 0x000000ff
#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
#define MCD_CHAIN_DMA /* TBD */
#define MCD_EU_DMA /* TBD */
#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
/* these flags are valid for MCD_startDma and the chained buffer descriptors */
#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */
#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */
#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring
last byte of data in buffer */
#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
prior to performing the DMA. */
/* Defines for the FEC buffer descriptor control/status word*/
#define MCD_FEC_BUF_READY 0x8000
#define MCD_FEC_WRAP 0x2000
#define MCD_FEC_INTERRUPT 0x1000
#define MCD_FEC_END_FRAME 0x0800
/*
* Defines for general intuitiveness
*/
#define MCD_TRUE 1
#define MCD_FALSE 0
/*
* Three different cases for destination and source.
*/
#define MINUS1 -1
#define ZERO 0
#define PLUS1 1
#ifndef DEFINESONLY
/* Task Table Entry struct*/
typedef struct {
u32 TDTstart; /* task descriptor table start */
u32 TDTend; /* task descriptor table end */
u32 varTab; /* variable table start */
u32 FDTandFlags; /* function descriptor table start and flags */
volatile u32 descAddrAndStatus;
volatile u32 modifiedVarTab;
u32 contextSaveSpace; /* context save space start */
u32 literalBases;
} TaskTableEntry;
/* Chained buffer descriptor */
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
struct MCD_bufDesc_struct {
u32 flags; /* flags describing the DMA */
u32 csumResult; /* checksum from checksumming performed since last checksum reset */
s8 *srcAddr; /* the address to move data from */
s8 *destAddr; /* the address to move data to */
s8 *lastDestAddr; /* the last address written to */
u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */
MCD_bufDesc *next; /* next buffer descriptor in chain */
u32 info; /* private information about this descriptor; DMA does not affect it */
};
/* Progress Query struct */
typedef volatile struct MCD_XferProg_struct {
s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */
s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */
u32 dmaSize; /* the amount of data transferred for the current buffer */
MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
} MCD_XferProg;
/* FEC buffer descriptor */
typedef volatile struct MCD_bufDescFec_struct {
u16 statCtrl;
u16 length;
u32 dataPointer;
} MCD_bufDescFec;
/*************************************************************************/
/*
* API function Prototypes - see MCD_dmaApi.c for further notes
*/
/*
* MCD_startDma starts a particular kind of DMA .
*/
int MCD_startDma (
int channel, /* the channel on which to run the DMA */
s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */
s16 srcIncr, /* the amount to increment the source address per transfer */
s8 *destAddr, /* the address to move data to */
s16 destIncr, /* the amount to increment the destination address per transfer */
u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
u32 initiator, /* what device initiates the DMA */
int priority, /* priority of the DMA */
u32 flags, /* flags describing the DMA */
u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
);
/*
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task structures, and
* setting up some global settings
*/
int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
/*
* MCD_dmaStatus() returns the status of the DMA on the requested channel.
*/
int MCD_dmaStatus (int channel);
/*
* MCD_XferProgrQuery() returns progress of DMA on requested channel
*/
int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
/*
* MCD_killDma() halts the DMA on the requested channel, without any
* intention of resuming the DMA.
*/
int MCD_killDma (int channel);
/*
* MCD_continDma() continues a DMA which as stopped due to encountering an
* unready buffer descriptor.
*/
int MCD_continDma (int channel);
/*
* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
* running on that channel).
*/
int MCD_pauseDma (int channel);
/*
* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
* running on that channel).
*/
int MCD_resumeDma (int channel);
/*
* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
*/
int MCD_csumQuery (int channel, u32 *csum);
/*
* MCD_getCodeSize provides the packed size required by the microcoded task
* and structures.
*/
int MCD_getCodeSize(void);
/*
* MCD_getVersion provides a pointer to a version string and returns a
* version number.
*/
int MCD_getVersion(char **longVersion);
/* macro for setting a location in the variable table */
#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
so I'm avoiding surrounding it with "do {} while(0)" */
#endif /* DEFINESONLY */
#endif /* _MCD_API_H */

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/*
* File: MCD_dmaApi.c
* Purpose: Main C file for multi-channel DMA API.
*
* Notes:
*/
#include "MCD_dma.h"
#include "MCD_tasksInit.h"
#include "MCD_progCheck.h"
/********************************************************************/
/*
* This is an API-internal pointer to the DMA's registers
*/
dmaRegs *MCD_dmaBar;
/*
* These are the real and model task tables as generated by the
* build process
*/
extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
/*
* However, this (usually) gets relocated to on-chip SRAM, at which
* point we access them as these tables
*/
volatile TaskTableEntry *MCD_taskTable;
TaskTableEntry *MCD_modelTaskTable;
/*
* MCD_chStatus[] is an array of status indicators for remembering
* whether a DMA has ever been attempted on each channel, pausing
* status, etc.
*/
static int MCD_chStatus[NCHANNELS] =
{
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
};
/*
* Prototypes for local functions
*/
static void MCD_memcpy (int *dest, int *src, u32 size);
static void MCD_resmActions (int channel);
/*
* Buffer descriptors used for storage of progress info for single Dmas
* Also used as storage for the DMA for CRCs for single DMAs
* Otherwise, the DMA does not parse these buffer descriptors
*/
#ifdef MCD_INCLUDE_EU
extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
#else
MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
#endif
MCD_bufDesc *MCD_relocBuffDesc;
/*
* Defines for the debug control register's functions
*/
#define DBG_CTL_COMP1_TASK (0x00002000) /* have comparator 1 look for a task # */
#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \
DBG_CTL_BREAK | \
DBG_CTL_INT_BREAK | \
DBG_CTL_COMP1_TASK)
#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \
DBG_CTL_INT_BREAK | \
DBG_CTL_COMP1_TASK)
#define DBG_KILL_ALL_STAT (0xFFFFFFFF)
/*
* Offset to context save area where progress info is stored
*/
#define CSAVE_OFFSET 10
/*
* Defines for Byte Swapping
*/
#define MCD_BYTE_SWAP_KILLER 0xFFF8888F
#define MCD_NO_BYTE_SWAP_ATALL 0x00040000
/*
* Execution Unit Identifiers
*/
#define MAC 0 /* legacy - not used */
#define LUAC 1 /* legacy - not used */
#define CRC 2 /* legacy - not used */
#define LURC 3 /* Logic Unit with CRC */
/*
* Task Identifiers
*/
#define TASK_CHAINNOEU 0
#define TASK_SINGLENOEU 1
#ifdef MCD_INCLUDE_EU
#define TASK_CHAINEU 2
#define TASK_SINGLEEU 3
#define TASK_FECRX 4
#define TASK_FECTX 5
#else
#define TASK_CHAINEU 0
#define TASK_SINGLEEU 1
#define TASK_FECRX 2
#define TASK_FECTX 3
#endif
/*
* Structure to remember which variant is on which channel
* TBD- need this?
*/
typedef struct MCD_remVariants_struct MCD_remVariant;
struct MCD_remVariants_struct
{
int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */
int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */
s16 remDestIncr[NCHANNELS]; /* DestIncr */
s16 remSrcIncr[NCHANNELS]; /* srcIncr */
u32 remXferSize[NCHANNELS]; /* xferSize */
};
/*
* Structure to remember the startDma parameters for each channel
*/
MCD_remVariant MCD_remVariants;
/********************************************************************/
/*
* Function: MCD_initDma
* Purpose: Initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task
* structures, and setting up some global settings
* Arguments:
* dmaBarAddr - pointer to the multichannel DMA registers
* taskTableDest - location to move DMA task code and structs to
* flags - operational parameters
* Return Value:
* MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
* MCD_OK otherwise
*/
extern u32 MCD_funcDescTab0[];
int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags)
{
int marker;
int i;
TaskTableEntry *entryPtr;
/* setup the local pointer to register set */
MCD_dmaBar = dmaBarAddr;
/* do we need to move/create a task table */
if ((flags & MCD_RELOC_TASKS) != 0)
{
int fixedSize;
u32 *fixedPtr;
/*int *tablePtr = taskTableDest;TBD*/
int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
int taskDescTabsOffset;
int taskTableSize, varTabsSize, funcDescTabsSize, contextSavesSize;
int taskDescTabSize;
int i;
/* check if physical address is aligned on 512 byte boundary */
if (((u32)taskTableDest & 0x000001ff) != 0)
return(MCD_TABLE_UNALIGNED);
MCD_taskTable = taskTableDest; /* set up local pointer to task Table */
/*
* Create a task table:
* - compute aligned base offsets for variable tables and
* function descriptor tables, then
* - loop through the task table and setup the pointers
* - copy over model task table with the the actual task descriptor
* tables
*/
taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
/* align variable tables to size */
varTabsOffset = taskTableSize + (u32)taskTableDest;
if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
/* align function descriptor tables */
varTabsSize = NCHANNELS * VAR_TAB_SIZE;
funcDescTabsOffset = varTabsOffset + varTabsSize;
if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
funcDescTabsOffset = (funcDescTabsOffset + FUNCDESC_TAB_SIZE) &
(~FUNCDESC_TAB_SIZE);
funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
fixedSize = taskTableSize + varTabsSize + funcDescTabsSize +
contextSavesSize;
/* zero the thing out */
fixedPtr = (u32 *)taskTableDest;
for (i = 0;i<(fixedSize/4);i++)
fixedPtr[i] = 0;
entryPtr = (TaskTableEntry*)MCD_taskTable;
/* set up fixed pointers */
for (i = 0; i < NCHANNELS; i++)
{
entryPtr[i].varTab = (u32)varTabsOffset; /* update ptr to local value */
entryPtr[i].FDTandFlags = (u32)funcDescTabsOffset | MCD_TT_FLAGS_DEF;
entryPtr[i].contextSaveSpace = (u32)contextSavesOffset;
varTabsOffset += VAR_TAB_SIZE;
#ifdef MCD_INCLUDE_EU /* if not there is only one, just point to the same one */
funcDescTabsOffset += FUNCDESC_TAB_SIZE;
#endif
contextSavesOffset += CONTEXT_SAVE_SIZE;
}
/* copy over the function descriptor table */
for ( i = 0; i < FUNCDESC_TAB_NUM; i++)
{
MCD_memcpy((void*)(entryPtr[i].FDTandFlags & ~MCD_TT_FLAGS_MASK),
(void*)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
}
/* copy model task table to where the context saves stuff leaves off*/
MCD_modelTaskTable = (TaskTableEntry*)contextSavesOffset;
MCD_memcpy ((void*)MCD_modelTaskTable, (void*)MCD_modelTaskTableSrc,
NUMOFVARIANTS * sizeof(TaskTableEntry));
entryPtr = MCD_modelTaskTable; /* point to local version of
model task table */
taskDescTabsOffset = (u32)MCD_modelTaskTable +
(NUMOFVARIANTS * sizeof(TaskTableEntry));
/* copy actual task code and update TDT ptrs in local model task table */
for (i = 0; i < NUMOFVARIANTS; i++)
{
asm
{
move.l #0x77777777,d0
}
taskDescTabSize = entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
MCD_memcpy ((void*)taskDescTabsOffset, (void*)entryPtr[i].TDTstart, taskDescTabSize);
entryPtr[i].TDTstart = (u32)taskDescTabsOffset;
taskDescTabsOffset += taskDescTabSize;
entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4;
}
#ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
where they are since DMA might write to them */
MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
#else /* DMA does not touch them so they can be wherever and we don't need to
waste SRAM on them */
MCD_relocBuffDesc = MCD_singleBufDescs;
#endif
}
else
{
/* point the would-be relocated task tables and the
buffer descriptors to the ones the linker generated */
if (((u32)MCD_realTaskTableSrc & 0x000001ff) != 0)
return(MCD_TABLE_UNALIGNED);
/* need to add code to make sure that every thing else is aligned properly TBD*/
/* this is problematic if we init more than once or after running tasks,
need to add variable to see if we have aleady init'd */
entryPtr = MCD_realTaskTableSrc;
for (i = 0; i < NCHANNELS; i++)
{
if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
((entryPtr[i].FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
return(MCD_TABLE_UNALIGNED);
}
MCD_taskTable = MCD_realTaskTableSrc;
MCD_modelTaskTable = MCD_modelTaskTableSrc;
MCD_relocBuffDesc = MCD_singleBufDescs;
}
/* Make all channels as totally inactive, and remember them as such: */
MCD_dmaBar->taskbar = (u32) MCD_taskTable;
for (i = 0; i < NCHANNELS; i++)
{
MCD_dmaBar->taskControl[i] = 0x0;
MCD_chStatus[i] = MCD_NO_DMA;
}
/* Set up pausing mechanism to inactive state: */
MCD_dmaBar->debugComp1 = 0; /* no particular values yet for either comparator registers */
MCD_dmaBar->debugComp2 = 0;
MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
/* enable or disable commbus prefetch, really need an ifdef or
something to keep from trying to set this in the 8220 */
if ((flags & MCD_COMM_PREFETCH_EN) != 0)
MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
else
MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
return(MCD_OK);
}
/*********************** End of MCD_initDma() ***********************/
/********************************************************************/
/* Function: MCD_dmaStatus
* Purpose: Returns the status of the DMA on the requested channel
* Arguments: channel - channel number
* Returns: Predefined status indicators
*/
int MCD_dmaStatus (int channel)
{
u16 tcrValue;
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
tcrValue = MCD_dmaBar->taskControl[channel];
if ((tcrValue & TASK_CTL_EN) == 0)
{ /* nothing running */
/* if last reported with task enabled */
if ( MCD_chStatus[channel] == MCD_RUNNING
|| MCD_chStatus[channel] == MCD_IDLE)
MCD_chStatus[channel] = MCD_DONE;
}
else /* something is running */
{
/* There are three possibilities: paused, running or idle. */
if ( MCD_chStatus[channel] == MCD_RUNNING
|| MCD_chStatus[channel] == MCD_IDLE)
{
MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
/* This register is selected to know which initiator is
actually asserted. */
if ((MCD_dmaBar->ptdDebug >> channel ) & 0x1 )
MCD_chStatus[channel] = MCD_RUNNING;
else
MCD_chStatus[channel] = MCD_IDLE;
/* do not change the status if it is already paused. */
}
}
return MCD_chStatus[channel];
}
/******************** End of MCD_dmaStatus() ************************/
/********************************************************************/
/* Function: MCD_startDma
* Ppurpose: Starts a particular kind of DMA
* Arguments: see below
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*/
int MCD_startDma (
int channel, /* the channel on which to run the DMA */
s8 *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
s16 srcIncr, /* the amount to increment the source address per transfer */
s8 *destAddr, /* the address to move data to */
s16 destIncr, /* the amount to increment the destination address per transfer */
u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
u32 initiator, /* what device initiates the DMA */
int priority, /* priority of the DMA */
u32 flags, /* flags describing the DMA */
u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
#ifdef MCD_NEED_ADDR_TRANS
s8 *srcAddrVirt /* virtual buffer descriptor address TBD*/
#endif
)
{
int srcRsdIncr, destRsdIncr;
int *cSave;
short xferSizeIncr;
int tcrCount = 0;
#ifdef MCD_INCLUDE_EU
u32 *realFuncArray;
#endif
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
/* tbd - need to determine the proper response to a bad funcDesc when not
including EU functions, for now, assign a benign funcDesc, but maybe
should return an error */
#ifndef MCD_INCLUDE_EU
funcDesc = MCD_FUNC_NOEU1;
#endif
#ifdef MCD_DEBUG
printf("startDma:Setting up params\n");
#endif
/* Set us up for task-wise priority. We don't technically need to do this on every start, but
since the register involved is in the same longword as other registers that users are in control
of, setting it more than once is probably preferable. That since the documentation doesn't seem
to be completely consistent about the nature of the PTD control register. */
MCD_dmaBar->ptdControl |= (u16) 0x8000;
#if 1 /* Not sure what we need to keep here rtm TBD */
/* Calculate additional parameters to the regular DMA calls. */
srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
/* Remember for each channel which variant is running. */
MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
MCD_remVariants.remDestIncr[channel] = destIncr;
MCD_remVariants.remSrcIncr[channel] = srcIncr;
MCD_remVariants.remXferSize[channel] = xferSize;
#endif
cSave = (int*)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET + CURRBD;
#ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */
realFuncArray = (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
/* Modify the LURC's normal and byte-residue-loop functions according to parameter. */
realFuncArray[(LURC*16)] = xferSize == 4 ?
funcDesc : xferSize == 2 ?
funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
realFuncArray[(LURC*16+1)] = (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
#endif
/* Write the initiator field in the TCR, and also set the initiator-hold
bit. Note that,due to a hardware quirk, this could collide with an
MDE access to the initiator-register file, so we have to verify that the write
reads back correctly. */
MCD_dmaBar->taskControl[channel] =
(initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
while(((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM)) &&
(tcrCount < 1000))
{
tcrCount++;
/*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020;*/
MCD_dmaBar->taskControl[channel] =
(initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
}
MCD_dmaBar->priority[channel] = (u8)priority & PRIORITY_PRI_MASK;
/* should be albe to handle this stuff with only one write to ts reg - tbd */
if (channel < 8 && channel >= 0)
{
MCD_dmaBar->taskSize0 &= ~(0xf << (7-channel)*4);
MCD_dmaBar->taskSize0 |= (xferSize & 3) << (((7 - channel)*4) + 2);
MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel)*4);
}
else
{
MCD_dmaBar->taskSize1 &= ~(0xf << (15-channel)*4);
MCD_dmaBar->taskSize1 |= (xferSize & 3) << (((15 - channel)*4) + 2);
MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel)*4);
}
/* setup task table flags/options which mostly control the line buffers */
MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
if (flags & MCD_FECTX_DMA)
{
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECTX].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend;
MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
}
else if (flags & MCD_FECRX_DMA)
{
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECRX].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECRX].TDTend;
MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
}
else if(flags & MCD_SINGLE_DMA)
{
/* this buffer descriptor is used for storing off initial parameters for later
progress query calculation and for the DMA to write the resulting checksum
The DMA does not use this to determine how to operate, that info is passed
with the init routine*/
MCD_relocBuffDesc[channel].srcAddr = srcAddr;
MCD_relocBuffDesc[channel].destAddr = destAddr;
MCD_relocBuffDesc[channel].lastDestAddr = destAddr; /* definitely not its final value */
MCD_relocBuffDesc[channel].dmaSize = dmaSize;
MCD_relocBuffDesc[channel].flags = 0; /* not used */
MCD_relocBuffDesc[channel].csumResult = 0; /* not used */
MCD_relocBuffDesc[channel].next = 0; /* not used */
/* Initialize the progress-querying stuff to show no progress:*/
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] =
(u32) &(MCD_relocBuffDesc[channel]);
/* tbd - need to keep the user from trying to call the EU routine
when MCD_INCLUDE_EU is not defined */
if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
{
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave,
MCD_taskTable, channel);
}
else
{
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave,
MCD_taskTable, channel);
}
}
else
{ /* chained DMAS */
/* Initialize the progress-querying stuff to show no progress:*/
#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc*) srcAddr)->srcAddr;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc*) srcAddr)->destAddr;
#else /* if using address translation, need the virtual addr of the first buffdesc */
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc*) srcAddrVirt)->destAddr;
#endif
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr;
if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
{
/*TDTStart and TDTEnd*/
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, destIncr, xferSize,
xferSizeIncr, cSave, MCD_taskTable, channel);
}
else
{
/*TDTStart and TDTEnd*/
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINEU].TDTend;
MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, xferSize,
xferSizeIncr, cSave, MCD_taskTable, channel);
}
}
MCD_chStatus[channel] = MCD_IDLE;
return(MCD_OK);
}
/************************ End of MCD_startDma() *********************/
/********************************************************************/
/* Function: MCD_XferProgrQuery
* Purpose: Returns progress of DMA on requested channel
* Arguments: channel - channel to retrieve progress for
* progRep - pointer to user supplied MCD_XferProg struct
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*
* Notes:
* MCD_XferProgrQuery() upon completing or after aborting a DMA, or
* while the DMA is in progress, this function returns the first
* DMA-destination address not (or not yet) used in the DMA. When
* encountering a non-ready buffer descriptor, the information for
* the last completed descriptor is returned.
*
* MCD_XferProgQuery() has to avoid the possibility of getting
* partially-updated information in the event that we should happen
* to query DMA progress just as the DMA is updating it. It does that
* by taking advantage of the fact context is not saved frequently for
* the most part. We therefore read it at least twice until we get the
* same information twice in a row.
*
* Because a small, but not insignificant, amount of time is required
* to write out the progress-query information, especially upon
* completion of the DMA, it would be wise to guarantee some time lag
* between successive readings of the progress-query information.
*/
/*
* How many iterations of the loop below to execute to stabilize values
*/
#define STABTIME 0
int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep)
{
MCD_XferProg prevRep;
int again; /* true if we are to try again to get consistent results */
int i; /* used as a time-waste counter */
int destDiffBytes; /* Total number of bytes that we think actually got xfered. */
int numIterations; /* number of iterations */
int bytesNotXfered; /* bytes that did not get xfered. */
s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
int subModVal, addModVal; /* Mode values to added and subtracted from the
final destAddr */
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
/* Read a trial value for the progress-reporting values*/
prevRep.lastSrcAddr =
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
prevRep.lastDestAddr =
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
prevRep.dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
prevRep.currBufDesc =
(MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
/* Repeatedly reread those values until they match previous values: */
do {
/* Waste a little bit of time to ensure stability: */
for (i = 0; i < STABTIME; i++)
i += i >> 2; /* make sure this loop does something so that it doesn't get optimized out */
/* Check them again: */
progRep->lastSrcAddr =
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
progRep->lastDestAddr =
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
progRep->dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
progRep->currBufDesc =
(MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
/* See if they match: */
if ( prevRep.lastSrcAddr != progRep->lastSrcAddr
|| prevRep.lastDestAddr != progRep->lastDestAddr
|| prevRep.dmaSize != progRep->dmaSize
|| prevRep.currBufDesc != progRep->currBufDesc)
{
/* If they don't match, remember previous values and try again:*/
prevRep.lastSrcAddr = progRep->lastSrcAddr;
prevRep.lastDestAddr = progRep->lastDestAddr;
prevRep.dmaSize = progRep->dmaSize;
prevRep.currBufDesc = progRep->currBufDesc;
again = MCD_TRUE;
}
else
again = MCD_FALSE;
} while (again == MCD_TRUE);
/* Update the dCount, srcAddr and destAddr */
/* To calculate dmaCount, we consider destination address. C
overs M1,P1,Z for destination */
switch(MCD_remVariants.remDestRsdIncr[channel]) {
case MINUS1:
subModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
addModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - addModVal;
LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
bytesNotXfered = (destDiffBytes/MCD_remVariants.remDestIncr[channel]) *
( MCD_remVariants.remDestIncr[channel]
+ MCD_remVariants.remXferSize[channel]);
progRep->dmaSize = destDiffBytes - bytesNotXfered + addModVal - subModVal;
break;
case ZERO:
progRep->lastDestAddr = progRep->currBufDesc->destAddr;
break;
case PLUS1:
/* This value has to be subtracted from the final calculated dCount. */
subModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
/* These bytes are already in lastDestAddr. */
addModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - subModVal;
LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
numIterations = ( LWAlignedCurrDestAddr - LWAlignedInitDestAddr)/MCD_remVariants.remDestIncr[channel];
bytesNotXfered = numIterations *
( MCD_remVariants.remDestIncr[channel]
- MCD_remVariants.remXferSize[channel]);
progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
break;
default:
break;
}
/* This covers M1,P1,Z for source */
switch(MCD_remVariants.remSrcRsdIncr[channel]) {
case MINUS1:
progRep->lastSrcAddr =
progRep->currBufDesc->srcAddr +
( MCD_remVariants.remSrcIncr[channel] *
(progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
break;
case ZERO:
progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
break;
case PLUS1:
progRep->lastSrcAddr =
progRep->currBufDesc->srcAddr +
( MCD_remVariants.remSrcIncr[channel] *
(progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
break;
default: break;
}
return(MCD_OK);
}
/******************* End of MCD_XferProgrQuery() ********************/
/********************************************************************/
/* MCD_resmActions() does the majority of the actions of a DMA resume.
* It is called from MCD_killDma() and MCD_resumeDma(). It has to be
* a separate function because the kill function has to negate the task
* enable before resuming it, but the resume function has to do nothing
* if there is no DMA on that channel (i.e., if the enable bit is 0).
*/
static void MCD_resmActions (int channel)
{
MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; /* This register is selected to know
which initiator is actually asserted. */
if((MCD_dmaBar->ptdDebug >> channel ) & 0x1)
MCD_chStatus[channel] = MCD_RUNNING;
else
MCD_chStatus[channel] = MCD_IDLE;
}
/********************* End of MCD_resmActions() *********************/
/********************************************************************/
/* Function: MCD_killDma
* Purpose: Halt the DMA on the requested channel, without any
* intention of resuming the DMA.
* Arguments: channel - requested channel
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*
* Notes:
* A DMA may be killed from any state, including paused state, and it
* always goes to the MCD_HALTED state even if it is killed while in
* the MCD_NO_DMA or MCD_IDLE states.
*/
int MCD_killDma (int channel)
{
/* MCD_XferProg progRep; */
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
MCD_dmaBar->taskControl[channel] = 0x0;
MCD_resumeDma (channel);
/*
* This must be after the write to the TCR so that the task doesn't
* start up again momentarily, and before the status assignment so
* as to override whatever MCD_resumeDma() may do to the channel
* status.
*/
MCD_chStatus[channel] = MCD_HALTED;
/*
* Update the current buffer descriptor's lastDestAddr field
*
* MCD_XferProgrQuery (channel, &progRep);
* progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
*/
return(MCD_OK);
}
/************************ End of MCD_killDma() **********************/
/********************************************************************/
/* Function: MCD_continDma
* Purpose: Continue a DMA which as stopped due to encountering an
* unready buffer descriptor.
* Arguments: channel - channel to continue the DMA on
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*
* Notes:
* This routine does not check to see if there is a task which can
* be continued. Also this routine should not be used with single DMAs.
*/
int MCD_continDma (int channel)
{
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
MCD_chStatus[channel] = MCD_RUNNING;
return(MCD_OK);
}
/********************** End of MCD_continDma() **********************/
/*********************************************************************
* MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
* to freeze a task and resume it. We freeze a task by breakpointing
* on the stated task. That is, not any specific place in the task,
* but any time that task executes. In particular, when that task
* executes, we want to freeze that task and only that task.
*
* The bits of the debug control register influence interrupts vs.
* breakpoints as follows:
* - Bits 14 and 0 enable or disable debug functions. If enabled, you
* will get the interrupt but you may or may not get a breakpoint.
* - Bits 2 and 1 decide whether you also get a breakpoint in addition
* to an interrupt.
*
* The debug unit can do these actions in response to either internally
* detected breakpoint conditions from the comparators, or in response
* to the external breakpoint pin, or both.
* - Bits 14 and 1 perform the above-described functions for
* internally-generated conditions, i.e., the debug comparators.
* - Bits 0 and 2 perform the above-described functions for external
* conditions, i.e., the breakpoint external pin.
*
* Note that, although you "always" get the interrupt when you turn
* the debug functions, the interrupt can nevertheless, if desired, be
* masked by the corresponding bit in the PTD's IMR. Note also that
* this means that bits 14 and 0 must enable debug functions before
* bits 1 and 2, respectively, have any effect.
*
* NOTE: It's extremely important to not pause more than one DMA channel
* at a time.
********************************************************************/
/********************************************************************/
/* Function: MCD_pauseDma
* Purpose: Pauses the DMA on a given channel (if any DMA is running
* on that channel).
* Arguments: channel
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*/
int MCD_pauseDma (int channel)
{
/* MCD_XferProg progRep; */
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
{
MCD_dmaBar->debugComp1 = channel;
MCD_dmaBar->debugControl = DBG_CTL_ENABLE | (1 << (channel + 16));
MCD_chStatus[channel] = MCD_PAUSED;
/*
* Update the current buffer descriptor's lastDestAddr field
*
* MCD_XferProgrQuery (channel, &progRep);
* progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
*/
}
return(MCD_OK);
}
/************************* End of MCD_pauseDma() ********************/
/********************************************************************/
/* Function: MCD_resumeDma
* Purpose: Resumes the DMA on a given channel (if any DMA is
* running on that channel).
* Arguments: channel - channel on which to resume DMA
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*/
int MCD_resumeDma (int channel)
{
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
MCD_resmActions (channel);
return(MCD_OK);
}
/************************ End of MCD_resumeDma() ********************/
/********************************************************************/
/* Function: MCD_csumQuery
* Purpose: Provide the checksum after performing a non-chained DMA
* Arguments: channel - channel to report on
* csum - pointer to where to write the checksum/CRC
* Returns: MCD_ERROR if the channel is invalid, else MCD_OK
*
* Notes:
*
*/
int MCD_csumQuery (int channel, u32 *csum)
{
#ifdef MCD_INCLUDE_EU
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
*csum = MCD_relocBuffDesc[channel].csumResult;
return(MCD_OK);
#else
return(MCD_ERROR);
#endif
}
/*********************** End of MCD_resumeDma() *********************/
/********************************************************************/
/* Function: MCD_getCodeSize
* Purpose: Provide the size requirements of the microcoded tasks
* Returns: Size in bytes
*/
int MCD_getCodeSize(void)
{
#ifdef MCD_INCLUDE_EU
return(0x2b5c);
#else
return(0x173c);
#endif
}
/********************** End of MCD_getCodeSize() ********************/
/********************************************************************/
/* Function: MCD_getVersion
* Purpose: Provide the version string and number
* Arguments: longVersion - user supplied pointer to a pointer to a char
* which points to the version string
* Returns: Version number and version string (by reference)
*/
char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
#define MCD_REV_MAJOR 0x00
#define MCD_REV_MINOR 0x03
int MCD_getVersion(char **longVersion)
{
*longVersion = MCD_versionString;
return((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
}
/********************** End of MCD_getVersion() *********************/
/********************************************************************/
/* Private version of memcpy()
* Note that everything this is used for is longword-aligned.
*/
static void MCD_memcpy (int *dest, int *src, u32 size)
{
u32 i;
for (i = 0; i < size; i += sizeof(int), dest++, src++)
*dest = *src;
}
/********************************************************************/

5
headers/MCD_progCheck.h Normal file
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@@ -0,0 +1,5 @@
/* This file is autogenerated. Do not change */
#define CURRBD 4
#define DCOUNT 6
#define DESTPTR 5
#define SRCPTR 7

2449
headers/MCD_tasks.c Normal file
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File diff suppressed because it is too large Load Diff

224
headers/MCD_tasksInit.c Normal file
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@@ -0,0 +1,224 @@
/*
* File: MCD_tasksInit.c
* Purpose: Functions for initializing variable tables of different
* types of tasks.
*
* Notes:
*/
/*
* Do not edit!
*/
#include "MCD_dma.h"
extern dmaRegs *MCD_dmaBar;
/*
* Task 0
*/
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 1
*/
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */
MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 2
*/
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); /* var[12] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */
MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */
MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 3
*/
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 4
*/
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 5
*/
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}

44
headers/MCD_tasksInit.h Normal file
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@@ -0,0 +1,44 @@
#ifndef MCD_TSK_INIT_H
#define MCD_TSK_INIT_H 1
/*
* Do not edit!
*/
/*
* Task 0
*/
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
/*
* Task 1
*/
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
/*
* Task 2
*/
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
/*
* Task 3
*/
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
/*
* Task 4
*/
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
/*
* Task 5
*/
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
#endif /* MCD_TSK_INIT_H */

581
headers/ii_add.h Normal file
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@@ -0,0 +1,581 @@
//--------------------------------------------------------------------
// add
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// add.b #im,dx
//--------------------------------------------------------------------
addbir_macro:.macro
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
add.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add ea,dx
//--------------------------------------------------------------------
adddd:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add ea,dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addddd:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add (ea),dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
adddda:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add (ay)+,dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addddai:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add -(ay),dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addddad:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d16(ay),dx
//--------------------------------------------------------------------
addd16ad:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d8(ay,dy),dx
//--------------------------------------------------------------------
addd8ad:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add xxx.w,dx
//--------------------------------------------------------------------
addxwd:.macro
#ifdef halten_add
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add xxx.l,dx
//--------------------------------------------------------------------
addxld:.macro
#ifdef halten_add
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d16(pc),dx
//--------------------------------------------------------------------
addd16pcd:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d8(pc,dy),dx
//--------------------------------------------------------------------
addd8pcd:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// add dy,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // add dx,(ay) (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addeda:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,(ay)+ (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addedai:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,(ay)+
//--------------------------------------------------------------------
addedaid:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,-(ay)
//--------------------------------------------------------------------
addedad:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,-(ay)
//--------------------------------------------------------------------
addedadd:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,d16(ay)
//--------------------------------------------------------------------
adde16ad:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add.w d8(ay,dy),dx
//--------------------------------------------------------------------
adde8ad:.macro
#ifdef halten_add
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,xxx.w
//--------------------------------------------------------------------
addxwe:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,xxx.l
//--------------------------------------------------------------------
addxle:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
/******************************************************/
// adress register
/******************************************************/
//--------------------------------------------------------------------
// // adda.w ea,ax (ea = dx;ax;(ax);(ax)+,-(ax)
//--------------------------------------------------------------------
addaw:.macro
#ifdef halten_add
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
mvs.w \1,d0
adda.l d0,\2
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// add.w ea,usp
//--------------------------------------------------------------------
addawa7:.macro
#ifdef halten_add
halt
#endif
mvs.w \1,d0
move.l usp,a1
add.l d0,a1
move.l a1,usp
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w ea,usp (ea = dx;ax;(ax);(ax)+,-(ax)
//--------------------------------------------------------------------
addawu:.macro
#ifdef halten_add
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
move.l a7,_a7_save
move.l usp,a7
move.l \1,d0
adda.l d0,\2
move.l a7,usp
move.l _a7_save,a7
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// // adda.w ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax)
//--------------------------------------------------------------------
addawua7:.macro
addawu \1,\2
.endm;
//--------------------------------------------------------------------
// // adda.w d16(ay),ax
//--------------------------------------------------------------------
addawd16a:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
adda.l d0,a1
mvs.w (a1),d0
move.l \2,a1
add.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w d8(ay,dy),ax
//--------------------------------------------------------------------
addawd8a:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
add.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w xxx.w,ax
//--------------------------------------------------------------------
addawxwax:.macro
#ifdef halten_add
halt
#endif
move.w \1,a1
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w xxx.l,ax
//--------------------------------------------------------------------
addawxlax:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w d16(pc),ax
//--------------------------------------------------------------------
addawd16pcax:.macro
#ifdef halten_add
halt
#endif
move.w \1,a1
adda.l a0,a1
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w d8(pc,dy),ax
//--------------------------------------------------------------------
addawd8pcax:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w #im,ax
//--------------------------------------------------------------------
addawim:.macro
#ifdef halten_add
halt
#endif
mvs.w \1,d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.l d8(ay,dy),ax
//--------------------------------------------------------------------
addald8a:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.l d8(pc,dy),ax
//--------------------------------------------------------------------
addakd8pcax:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//*****************************************************************************************
// addx
//*****************************************************************************************
//--------------------------------------------------------------------
// // addx dy,dx
//--------------------------------------------------------------------
adddx:.macro
#ifdef halten_add
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
mvs.\3 \2,d0
mvs.\3 \1,d1
addx.l d0,d1
set_cc0
move.\3 d1,\1
ii_end
.endm;
//--------------------------------------------------------------------
// // addx -(ay),-(ax)
//--------------------------------------------------------------------
adddax:.macro
#ifdef halten_add
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
move.l \1,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d0
.endif
move.l \2,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d1
.endif
addx.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------

441
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//--------------------------------------------------------------------
// and
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// and.b #im,dx
//--------------------------------------------------------------------
andbir_macro:.macro
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
and.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea,dx
//--------------------------------------------------------------------
anddd:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea(l)->dy(w),dx z.B. f<>r USP
//--------------------------------------------------------------------
andddd:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and (ea)->dy,dx
//--------------------------------------------------------------------
anddda:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea->ay,(ay)+,dx
//--------------------------------------------------------------------
andddai:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea->ay,-(ay),dx
//--------------------------------------------------------------------
andddad:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d16(ay),dx
//--------------------------------------------------------------------
andd16ad:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d8(ay,dy),dx
//--------------------------------------------------------------------
andd8ad:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and xxx.w,dx
//--------------------------------------------------------------------
andxwd:.macro
#ifdef halten_and
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and xxx.l,dx
//--------------------------------------------------------------------
andxld:.macro
#ifdef halten_and
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d16(pc),dx
//--------------------------------------------------------------------
andd16pcd:.macro
#ifdef halten_and
halt
#endif
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d8(pc,dy),dx
//--------------------------------------------------------------------
andd8pcd:.macro
#ifdef halten_and
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// and dx,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // and dx,(ea)->dy
//--------------------------------------------------------------------
andeda:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,(ay)+
//--------------------------------------------------------------------
andedai:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,(ay)+
//--------------------------------------------------------------------
andedaid:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,-(ay)
//--------------------------------------------------------------------
andedad:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,-(ay)
//--------------------------------------------------------------------
andedadd:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,d16(ay)
//--------------------------------------------------------------------
ande16ad:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and.w dx,d8(ay,dy)
//--------------------------------------------------------------------
ande8ad:.macro
#ifdef halten_and
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,xxx.w
//--------------------------------------------------------------------
andxwe:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,xxx.l
//--------------------------------------------------------------------
andxle:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // anda.w ea,ax
//--------------------------------------------------------------------
andaw:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// and.w ea,usp
//--------------------------------------------------------------------
andawa7:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w usp?,ax
//--------------------------------------------------------------------
andawu:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w usp?,usp
//--------------------------------------------------------------------
andawua7:.macro
andawu \1,\2
.endm;
//--------------------------------------------------------------------
// // anda.w d16(ay),ax
//--------------------------------------------------------------------
andawd16a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w d8(ay,dy),ax
//--------------------------------------------------------------------
andawd8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w xxx.w,ax
//--------------------------------------------------------------------
andawxwax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w xxx.l,ax
//--------------------------------------------------------------------
andawxlax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w d16(pc),ax
//--------------------------------------------------------------------
andawd16pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w d8(pc,dy),ax
//--------------------------------------------------------------------
andawd8pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w #im,ax
//--------------------------------------------------------------------
andawim:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.l d8(ay,dy),ax
//--------------------------------------------------------------------
andald8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.l d8(pc,dy),ax
//--------------------------------------------------------------------
andald8pcax:.macro
jmp ii_error
.endm;
//*****************************************************************************************
// spezial addx subx etc.
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // addx dy,dx
//--------------------------------------------------------------------
anddx:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // addx -(ay),-(ax)
//--------------------------------------------------------------------
anddax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------

117
headers/ii_dbcc.h Normal file
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//--------------------------------------------------------------------
// dbcc,trapcc
//--------------------------------------------------------------------
.text
ii_lset_dbcc:.macro
// dbra
ii_lset_opeau 51,c
ii_lset_opeau 52,c
ii_lset_opeau 53,c
ii_lset_opeau 54,c
ii_lset_opeau 55,c
ii_lset_opeau 56,c
ii_lset_opeau 57,c
ii_lset_opeau 58,c
ii_lset_opeau 59,c
ii_lset_opeau 5a,c
ii_lset_opeau 5b,c
ii_lset_opeau 5c,c
ii_lset_opeau 5d,c
ii_lset_opeau 5e,c
ii_lset_opeau 5f,c
.endm
ii_dbcc_func:.macro
ii_0x51c8:
dbra_macro d0_off+2(a7)
ii_0x51c9:
dbra_macro d1_off+2(a7)
ii_0x51ca:
dbra_macro d2
ii_0x51cb:
dbra_macro d3
ii_0x51cc:
dbra_macro d4
ii_0x51cd:
dbra_macro d5
ii_0x51ce:
dbra_macro d6
ii_0x51cf:
dbra_macro d7
//---------------------------------------------------------------------------------------------
// dbcc dx
//---------------------------------------------------------------------------------------------
ii_dbcc 2,hi
ii_dbcc 3,ls
ii_dbcc 4,cc
ii_dbcc 5,cs
ii_dbcc 6,ne
ii_dbcc 7,eq
ii_dbcc 8,vc
ii_dbcc 9,vs
ii_dbcc a,pl
ii_dbcc b,mi
ii_dbcc c,ge
ii_dbcc d,lt
ii_dbcc e,gt
ii_dbcc f,le
.endm
//---------------------------------------------------------------------------------------------
// dbra dx
//---------------------------------------------------------------------------------------------
dbra_macro:.macro
#ifdef halten_dbcc
halt
#endif
mvz.w \1,d1 // dx holen
subq.l #1,d1 // dx-1
bcc dbra\@ // bra if plus?
addq.l #2,a0 // offset <20>berspringen
move.w d1,\1 // dx sichern
ii_end
dbra\@:
move.w (a0),a1 // offset (wird auf long erweitert)
add.l a1,a0 // dazuadieren
move.w d1,\1 // dx sichern
ii_end
.endm
//---------------------------------------------------------------------------------------------
// dbcc dx
//---------------------------------------------------------------------------------------------
dbcc_macro:.macro
#ifdef halten_dbcc
halt
#endif
b\2 dbncc\@
mvz.w \1,d1 // dx holen
subq.l #1,d1 // dx-1
bcc dbcc\@ // bra if plus?
dbncc\@:
addq.l #2,a0 // offset <20>berspringen
move.w d1,\1 // dx sichern
ii_end
dbcc\@:
move.w (a0),a1 // offset (wird auf long erweitert)
add.l a1,a0 // dazuadieren
move.w d1,\1 // dx sichern
ii_end
.endm
//db
ii_dbcc:.macro
ii_0x5\1c8:
dbcc_macro d0_off+2(a7),\2
ii_0x5\1c9:
dbcc_macro d1_off+2(a7),\2
ii_0x5\1ca:
dbcc_macro d2,\2
ii_0x5\1cb:
dbcc_macro d3,\2
ii_0x5\1cc:
dbcc_macro d4,\2
ii_0x5\1cd:
dbcc_macro d5,\2
ii_0x5\1ce:
dbcc_macro d6,\2
ii_0x5\1cf:
dbcc_macro d7,\2
.endm

181
headers/ii_ewf.h Normal file
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//--------------------------------------------------------------------
// extension word format missing
//--------------------------------------------------------------------
.text
ii_ewf_lset:.macro
// pea
ii_lset_opeag 48,7
ii_lset 0x487b
// jmp
ii_lset_opeag 4e,f
ii_lset 0x4efb
// jsr
ii_lset_opeag 4e,b
ii_lset 0x4ebb
// tas
ii_lset_opeag 4a,f
ii_lset 0x4ebb
// tst.b
ii_lset_opeag 4a,3
ii_lset 0x4ebb
// tst.w
ii_lset_opeag 4a,7
ii_lset 0x4ebb
// tst.l
ii_lset_opeag 4a,b
ii_lset 0x4ebb
// clr.b
ii_lset_opeag 42,3
ii_lset 0x423b
// clr.w
ii_lset_opeag 42,7
ii_lset 0x423b
// clr.l
ii_lset_opeag 42,b
ii_lset 0x423b
.endm
//---------------------------------------------------------------------------------------------
ii_ewf_func:.macro
ewf_func_macro pea,487
ewf_func_macro jmp,4ef
ewf_func_macro jsr,4eb
ewf_func_macro tas,4af
ewf_func_macro tstb,4a3
ewf_func_macro tstw,4a7
ewf_func_macro tstl,4ab
ewf_func_macro clrb,423
ewf_func_macro clrw,427
ewf_func_macro clrl,42b
.endm
//---------------------------------------------------------------------------------------------
pea_macro:.macro
jsr ewf
move.l (a1),d0
move.l usp,a1
move.l d0,-(a1)
move.l a1,usp
ii_end
.endm
jmp_macro:.macro
jsr ewf
move.l a1,a0
ii_end
.endm
jsr_macro:.macro
jsr ewf
move.l a1,d0
move.l usp,a1
move.l a0,-(a1)
move.l a1,usp
move.l d0,a0
ii_end
.endm
tas_macro:.macro
jsr ewf
tas (a1)
set_cc0
ii_end
.endm
tstb_macro:.macro
jsr ewf
tst.b (a1)
set_cc0
ii_end
.endm
tstw_macro:.macro
jsr ewf
tst.w (a1)
set_cc0
ii_end
.endm
tstl_macro:.macro
jsr ewf
tst.l (a1)
set_cc0
ii_end
.endm
clrb_macro:.macro
jsr ewf
clr.b (a1)
set_cc0
ii_end
.endm
clrw_macro:.macro
jsr ewf
clr.w (a1)
set_cc0
ii_end
.endm
clrl_macro:.macro
jsr ewf
clr.l (a1)
set_cc0
ii_end
.endm
//--------------------------------------------------------------------
ewf_func_macro:.macro //1=art 2=code
ii_0x\20:
#ifdef halten_ewf
halt
#endif
move.l a0_off(a7),a1
\1_macro
ii_0x\21:
#ifdef halten_ewf
halt
#endif
move.l a1_off(a7),a1
\1_macro
ii_0x\22:
#ifdef halten_ewf
halt
#endif
move.l a2,a1
\1_macro
ii_0x\23:
#ifdef halten_ewf
halt
#endif
move.l a3,a1
\1_macro
ii_0x\24:
#ifdef halten_ewf
halt
#endif
move.l a4,a1
\1_macro
ii_0x\25:
#ifdef halten_ewf
halt
#endif
move.l a5,a1
\1_macro
ii_0x\26:
#ifdef halten_ewf
halt
#endif
move.l a6,a1
\1_macro
ii_0x\27:
#ifdef halten_ewf
halt
#endif
move.l usp,a1
\1_macro
ii_0x\2b:
#ifdef halten_ewf
halt
#endif
move.l a0,a1
\1_macro
.endm

120
headers/ii_exg.h Normal file
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//--------------------------------------------------------------------
// exg
//--------------------------------------------------------------------
.text
ii_exg_lset:.macro
/* ii_lset_dxu c,40 //dx,d0
ii_lset_dxu c,41 //dx,d1
ii_lset_dxu c,42 //dx,d2
ii_lset_dxu c,43 //dx,d3
ii_lset_dxu c,44 //dx,d4
ii_lset_dxu c,45 //dx,d5
ii_lset_dxu c,46 //dx,d6
ii_lset_dxu c,47 //dx,d7
ii_lset_dxu c,48 //ax,a0
ii_lset_dxu c,49 //ax,a1
ii_lset_dxu c,4a //ax,a2
ii_lset_dxu c,4b //ax,a3
ii_lset_dxu c,4c //ax,a4
ii_lset_dxu c,4d //ax,a5
ii_lset_dxu c,4e //ax,a6
ii_lset_dxu c,4f //ax,a7 */ -->setting by "and"
ii_lset_dxu c,88 //dx,a0
ii_lset_dxu c,89 //dx,a1
ii_lset_dxu c,8a //dx,a2
ii_lset_dxu c,8b //dx,a3
ii_lset_dxu c,8c //dx,a4
ii_lset_dxu c,8d //dx,a5
ii_lset_dxu c,8e //dx,a6
ii_lset_dxu c,8f //dx,a7
.endm
//---------------------------------------------------------------------------------------------
ii_exg_func:.macro
// exg dx,dy
ii_exg_dx_dx 14,d0_off(a7)
ii_exg_dx_dx 34,d1_off(a7)
ii_exg_dx_dx 54,d2
ii_exg_dx_dx 74,d3
ii_exg_dx_dx 94,d4
ii_exg_dx_dx b4,d5
ii_exg_dx_dx d4,d6
ii_exg_dx_dx f4,d7
// exg ax,ay
ii_exg_to_ax 14,a0_off(a7)
ii_exg_to_ax 34,a1_off(a7)
ii_exg_to_ax 54,a2
ii_exg_to_ax 74,a3
ii_exg_to_ax 94,a4
ii_exg_to_ax b4,a5
ii_exg_to_ax d4,a6
ii_exg_to_ax f4,usp
// exg dx,ay
ii_exg_to_ax 18,d0_off(a7)
ii_exg_to_ax 38,d1_off(a7)
ii_exg_to_ax 58,d2
ii_exg_to_ax 78,d3
ii_exg_to_ax 98,d4
ii_exg_to_ax b8,d5
ii_exg_to_ax d8,d6
ii_exg_to_ax f8,d7
.endm
//---------------------------------------------------------------------------------------------
exg_macro:.macro
#ifdef halten_exg
halt
#endif
move.l \1,a1
.ifc \2,usp
move.l a1,d0
move.l \2,a1
move.l a1,\1
move.l d0,a1
.else
.ifc \1,usp
move.l a1,d0
move.l \2,a1
move.l a1,\1
move.l d0,a1
.else
move.l \2,\1
.endif
.endif
move.l a1,\2
ii_end
.endm
ii_exg_dx_dx:.macro
ii_0xc\10:
exg_macro \2,d0_off(a7)
ii_0xc\11:
exg_macro \2,d1_off(a7)
ii_0xc\12:
exg_macro \2,d2
ii_0xc\13:
exg_macro \2,d3
ii_0xc\14:
exg_macro \2,d4
ii_0xc\15:
exg_macro \2,d5
ii_0xc\16:
exg_macro \2,d6
ii_0xc\17:
exg_macro \2,d7
.endm
ii_exg_to_ax:.macro
ii_0xc\18:
exg_macro \2,a0_off(a7)
ii_0xc\19:
exg_macro \2,a1_off(a7)
ii_0xc\1a:
exg_macro \2,a2
ii_0xc\1b:
exg_macro \2,a3
ii_0xc\1c:
exg_macro \2,a4
ii_0xc\1d:
exg_macro \2,a5
ii_0xc\1e:
exg_macro \2,a6
ii_0xc\1f:
exg_macro \2,usp
.endm

945
headers/ii_func.h Normal file
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@@ -0,0 +1,945 @@
//--------------------------------------------------------------------
// functionen macros
//--------------------------------------------------------------------
ii_lset_func:.macro
/******************************************************/
// byt
/******************************************************/
// func.b dy,dx
ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,01
ii_lset_dx \1,02
ii_lset_dx \1,03
ii_lset_dx \1,04
ii_lset_dx \1,05
ii_lset_dx \1,06
ii_lset_dx \1,07
// func.b ax,dx
ii_lset_dxu \1,08
ii_lset_dxu \1,09
ii_lset_dxu \1,0a
ii_lset_dxu \1,0b
ii_lset_dxu \1,0c
ii_lset_dxu \1,0d
ii_lset_dxu \1,0e
ii_lset_dxu \1,0f
// func.b (ax),dx
ii_lset_dx \1,10
ii_lset_dx \1,11
ii_lset_dx \1,12
ii_lset_dx \1,13
ii_lset_dx \1,14
ii_lset_dx \1,15
ii_lset_dx \1,16
ii_lset_dx \1,17
// func.b (ax)+,dx
ii_lset_dx \1,18
ii_lset_dx \1,19
ii_lset_dx \1,1a
ii_lset_dx \1,1b
ii_lset_dx \1,1c
ii_lset_dx \1,1d
ii_lset_dx \1,1e
ii_lset_dx \1,1f
// func.b -(ax),dx
ii_lset_dx \1,20
ii_lset_dx \1,21
ii_lset_dx \1,22
ii_lset_dx \1,23
ii_lset_dx \1,24
ii_lset_dx \1,25
ii_lset_dx \1,26
ii_lset_dx \1,27
// func.b d16(ax),dx
ii_lset_dx \1,28
ii_lset_dx \1,29
ii_lset_dx \1,2a
ii_lset_dx \1,2b
ii_lset_dx \1,2c
ii_lset_dx \1,2d
ii_lset_dx \1,2e
ii_lset_dx \1,2f
// func.b dd8(ax,dy),dx
ii_lset_dx \1,30
ii_lset_dx \1,31
ii_lset_dx \1,32
ii_lset_dx \1,33
ii_lset_dx \1,34
ii_lset_dx \1,35
ii_lset_dx \1,36
ii_lset_dx \1,37
// func.b xxx.w,dx
ii_lset_dx \1,38 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b xxx.l,dx
ii_lset_dx \1,39 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b d16(pc),dx
ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b d8(pc,dy),dx
ii_lset_dxg \1,3b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b #im,dx
ii_lset_dxg \1,3c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
/******************************************************/
// word
/******************************************************/
// func.w dy,dx
ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,41
ii_lset_dx \1,42
ii_lset_dx \1,43
ii_lset_dx \1,44
ii_lset_dx \1,45
ii_lset_dx \1,46
ii_lset_dx \1,47
// func.w ax,dx
ii_lset_dx \1,48
ii_lset_dx \1,49
ii_lset_dx \1,4a
ii_lset_dx \1,4b
ii_lset_dx \1,4c
ii_lset_dx \1,4d
ii_lset_dx \1,4e
ii_lset_dx \1,4f
// func.w (ax),dx
ii_lset_dx \1,50
ii_lset_dx \1,51
ii_lset_dx \1,52
ii_lset_dx \1,53
ii_lset_dx \1,54
ii_lset_dx \1,55
ii_lset_dx \1,56
ii_lset_dx \1,57
// func.w (ax)+,dx
ii_lset_dx \1,58
ii_lset_dx \1,59
ii_lset_dx \1,5a
ii_lset_dx \1,5b
ii_lset_dx \1,5c
ii_lset_dx \1,5d
ii_lset_dx \1,5e
ii_lset_dx \1,5f
// func.w -(ax),dx
ii_lset_dx \1,60
ii_lset_dx \1,61
ii_lset_dx \1,62
ii_lset_dx \1,63
ii_lset_dx \1,64
ii_lset_dx \1,65
ii_lset_dx \1,66
ii_lset_dx \1,67
// func.w d16(ax),dx
ii_lset_dx \1,68
ii_lset_dx \1,69
ii_lset_dx \1,6a
ii_lset_dx \1,6b
ii_lset_dx \1,6c
ii_lset_dx \1,6d
ii_lset_dx \1,6e
ii_lset_dx \1,6f
// func.w d8(ax,dy),dx
ii_lset_dx \1,70
ii_lset_dx \1,71
ii_lset_dx \1,72
ii_lset_dx \1,73
ii_lset_dx \1,74
ii_lset_dx \1,75
ii_lset_dx \1,76
ii_lset_dx \1,77
// func.w xxx.w,dx
ii_lset_dx \1,78 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w xxx.l,dx
ii_lset_dx \1,79 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w d16(pc),dx
ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w d8(pc,dy),dx
ii_lset_dxg \1,7b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w #im,dx
ii_lset_dxg \1,7c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
/******************************************************/
// long
/******************************************************/
// func.l ax,dx -> -(ay),-(ax)
ii_lset_dxu \1,c8
ii_lset_dxu \1,c9
ii_lset_dxu \1,ca
ii_lset_dxu \1,cb
ii_lset_dxu \1,cc
ii_lset_dxu \1,cd
ii_lset_dxu \1,ce
ii_lset_dxu \1,cf
// func.w d8(ax,dy),dx
ii_lset_dx \1,b0
ii_lset_dx \1,b1
ii_lset_dx \1,b2
ii_lset_dx \1,b3
ii_lset_dx \1,b4
ii_lset_dx \1,b5
ii_lset_dx \1,b6
ii_lset_dx \1,b7
// func.l d8(pc,dy),dx
ii_lset_dxg \1,bb // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
/******************************************************/
// adress register
/******************************************************/
//func.w dy,ax
ii_lset_dxg \1,c0
ii_lset_dxg \1,c1
ii_lset_dxg \1,c2
ii_lset_dxg \1,c3
ii_lset_dxg \1,c4
ii_lset_dxg \1,c5
ii_lset_dxg \1,c6
ii_lset_dxg \1,c7
//func.w ay,ax
ii_lset_dxg \1,c8
ii_lset_dxg \1,c9
ii_lset_dxg \1,ca
ii_lset_dxg \1,cb
ii_lset_dxg \1,cc
ii_lset_dxg \1,cd
ii_lset_dxg \1,ce
ii_lset_dxg \1,cf
//func.w (ay),ax
ii_lset_dxg \1,d0
ii_lset_dxg \1,d1
ii_lset_dxg \1,d2
ii_lset_dxg \1,d3
ii_lset_dxg \1,d4
ii_lset_dxg \1,d5
ii_lset_dxg \1,d6
ii_lset_dxg \1,d7
//func.w (ay)+,ax
ii_lset_dxg \1,d8
ii_lset_dxg \1,d9
ii_lset_dxg \1,da
ii_lset_dxg \1,db
ii_lset_dxg \1,dc
ii_lset_dxg \1,dd
ii_lset_dxg \1,de
ii_lset_dxg \1,df
//func.w -(ay),ax
ii_lset_dxg \1,e0
ii_lset_dxg \1,e1
ii_lset_dxg \1,e2
ii_lset_dxg \1,e3
ii_lset_dxg \1,e4
ii_lset_dxg \1,e5
ii_lset_dxg \1,e6
ii_lset_dxg \1,e7
//func.w d16(ay),ax
ii_lset_dxg \1,e8
ii_lset_dxg \1,e9
ii_lset_dxg \1,ea
ii_lset_dxg \1,eb
ii_lset_dxg \1,ec
ii_lset_dxg \1,ed
ii_lset_dxg \1,ee
ii_lset_dxg \1,ef
//func.w d8(ay,dy),ax
ii_lset_dxg \1,f0
ii_lset_dxg \1,f1
ii_lset_dxg \1,f2
ii_lset_dxg \1,f3
ii_lset_dxg \1,f4
ii_lset_dxg \1,f5
ii_lset_dxg \1,f6
ii_lset_dxg \1,f7
// func.w xxx.w,ax
ii_lset_dxg \1,f8
// func.w xxx.l,ax
ii_lset_dxg \1,f9
// func.w d16(pc),ax
ii_lset_dxg \1,fa
// func.w d8(pc,dy),ax
ii_lset_dxg \1,fb
// func.w #im,ax
ii_lset_dxg \1,fc
//--------------------------------------------------------------------
// ende
.endm;
/*****************************************************************************************/
ii_func:.macro
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
///--------------------------------------------------------------------
// func.b ds,dx
//--------------------------------------------------------------------
funcbeadx \1,00,\2dd,d0_off+3(a7)
funcbeadx \1,01,\2dd,d1_off+3(a7)
funcbeadx \1,02,\2dd,d2
funcbeadx \1,03,\2dd,d3
funcbeadx \1,04,\2dd,d4
funcbeadx \1,05,\2dd,d5
funcbeadx \1,06,\2dd,d6
funcbeadx \1,07,\2dd,d7
//--------------------------------------------------------------------
// func.b (ax),dx
//--------------------------------------------------------------------
funcbeadx \1,10,\2dda,a0_off(a7)
funcbeadx \1,11,\2dda,a1_off(a7)
funcbeadx \1,12,\2dd,(a2)
funcbeadx \1,13,\2dd,(a3)
funcbeadx \1,14,\2dd,(a4)
funcbeadx \1,15,\2dd,(a5)
funcbeadx \1,16,\2dd,(a6)
funcbeadx \1,17,\2dda,usp
//--------------------------------------------------------------------
// func.b (ax)+,dx
//--------------------------------------------------------------------
funcbeadx \1,18,\2ddai,a0_off(a7)
funcbeadx \1,19,\2ddai,a1_off(a7)
funcbeadx \1,1a,\2dd,(a2)+
funcbeadx \1,1b,\2dd,(a3)+
funcbeadx \1,1c,\2dd,(a4)+
funcbeadx \1,1d,\2dd,(a5)+
funcbeadx \1,1e,\2dd,(a6)+
funcbeadx \1,1f,\2ddai,usp
//--------------------------------------------------------------------
// func.b -(ax),dx
//--------------------------------------------------------------------
funcbeadx \1,20,\2ddad,a0_off(a7)
funcbeadx \1,21,\2ddad,a1_off(a7)
funcbeadx \1,22,\2dd,-(a2)
funcbeadx \1,23,\2dd,-(a3)
funcbeadx \1,24,\2dd,-(a4)
funcbeadx \1,25,\2dd,-(a5)
funcbeadx \1,26,\2dd,-(a6)
funcbeadx \1,27,\2ddad,usp
//--------------------------------------------------------------------
// func.b d16(ax),dx
//--------------------------------------------------------------------
funcbeadx \1,28,\2d16ad,a0_off(a7)
funcbeadx \1,29,\2d16ad,a1_off(a7)
funcbeadx \1,2a,\2d16ad,a2
funcbeadx \1,2b,\2d16ad,a3
funcbeadx \1,2c,\2d16ad,a4
funcbeadx \1,2d,\2d16ad,a5
funcbeadx \1,2e,\2d16ad,a6
funcbeadx \1,2f,\2d16ad,usp
//--------------------------------------------------------------------
// func.b d8(ax,dy),dx
//--------------------------------------------------------------------
funcbeadx \1,30,\2d8ad,a0_off(a7)
funcbeadx \1,31,\2d8ad,a1_off(a7)
funcbeadx \1,32,\2d8ad,a2
funcbeadx \1,33,\2d8ad,a3
funcbeadx \1,34,\2d8ad,a4
funcbeadx \1,35,\2d8ad,a5
funcbeadx \1,36,\2d8ad,a6
funcbeadx \1,37,\2d8ad,usp
//--------------------------------------------------------------------
// func.b xxx.w,dx
//--------------------------------------------------------------------
funcbeadx \1,38,\2xwd,(a0)+
//--------------------------------------------------------------------
// func.b xxx.w,dx
//--------------------------------------------------------------------
funcbeadx \1,39,\2xld,(a0)+
//--------------------------------------------------------------------
// func.b d16(pc),dx
//--------------------------------------------------------------------
funcbeadx \1,3a,\2d16pcd,(a0)+
//--------------------------------------------------------------------
// func.b d8(pc,dy),dx
//--------------------------------------------------------------------
funcbeadx \1,3b,\2d8pcd,(a0)+ (a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.b #im,dx
//--------------------------------------------------------------------
funcbeadx \1,3c,\2bir_macro,(a0)+
//--------------------------------------------------------------------
// func.b dy,ea
//--------------------------------------------------------------------
///--------------------------------------------------------------------
// func.b dx,dd -> addx subx etc. src und dest vertauscht!
//--------------------------------------------------------------------
funcbdxea \1,00,\2dx,d0_off+3(a7)
funcbdxea \1,01,\2dx,d1_off+3(a7)
funcbdxea \1,02,\2dx,d2
funcbdxea \1,03,\2dx,d3
funcbdxea \1,04,\2dx,d4
funcbdxea \1,05,\2dx,d5
funcbdxea \1,06,\2dx,d6
funcbdxea \1,07,\2dx,d7
//--------------------------------------------------------------------
// func.b -(ax),-(ay) addx subx etc. src und dest vertauscht!
//--------------------------------------------------------------------
funcaxay \1,08,\2dax,a0_off(a7),b
funcaxay \1,09,\2dax,a1_off(a7).b
funcaxay \1,0a,\2dax,a2,b
funcaxay \1,0b,\2dax,a3,b
funcaxay \1,0c,\2dax,a4,b
funcaxay \1,0d,\2dax,a5,b
funcaxay \1,0e,\2dax,a6,b
funcaxay \1,0f,\2dax,usp,b
//--------------------------------------------------------------------
// func.b dy,(ax)
//--------------------------------------------------------------------
funcbdxea \1,10,\2eda,a0_off(a7)
funcbdxea \1,11,\2eda,a1_off(a7)
funcbdxea \1,12,\2dd,(a2)
funcbdxea \1,13,\2dd,(a3)
funcbdxea \1,14,\2dd,(a4)
funcbdxea \1,15,\2dd,(a5)
funcbdxea \1,16,\2dd,(a6)
funcbdxea \1,17,\2eda,usp
//--------------------------------------------------------------------
// func.b dy,(ax)+
//--------------------------------------------------------------------
funcbdxea \1,18,\2edai,a0_off(a7)
funcbdxea \1,19,\2edai,a1_off(a7)
funcbdxea \1,1a,\2edaid,(a2)
funcbdxea \1,1b,\2edaid,(a3)
funcbdxea \1,1c,\2edaid,(a4)
funcbdxea \1,1d,\2edaid,(a5)
funcbdxea \1,1e,\2edaid,(a6)
funcbdxea \1,1f,\2edai,usp
//--------------------------------------------------------------------
// func.b dy,-(ax)
//--------------------------------------------------------------------
funcbdxea \1,20,\2edad,a0_off(a7)
funcbdxea \1,21,\2edad,a1_off(a7)
funcbdxea \1,22,\2edadd,(a2)
funcbdxea \1,23,\2edadd,(a3)
funcbdxea \1,24,\2edadd,(a4)
funcbdxea \1,25,\2edadd,(a5)
funcbdxea \1,26,\2edadd,(a6)
funcbdxea \1,27,\2edad,usp
//--------------------------------------------------------------------
// func.b dy,d16(ax)
//--------------------------------------------------------------------
funcbdxea \1,28,\2e16ad,a0_off(a7)
funcbdxea \1,29,\2e16ad,a1_off(a7)
funcbdxea \1,2a,\2e16ad,a2
funcbdxea \1,2b,\2e16ad,a3
funcbdxea \1,2c,\2e16ad,a4
funcbdxea \1,2d,\2e16ad,a5
funcbdxea \1,2e,\2e16ad,a6
funcbdxea \1,2f,\2e16ad,usp
//--------------------------------------------------------------------
// func.b dy,d8(ax,dy)
//--------------------------------------------------------------------
funcbdxea \1,30,\2e8ad,a0_off(a7)
funcbdxea \1,31,\2e8ad,a1_off(a7)
funcbdxea \1,32,\2e8ad,a2
funcbdxea \1,33,\2e8ad,a3
funcbdxea \1,34,\2e8ad,a4
funcbdxea \1,35,\2e8ad,a5
funcbdxea \1,36,\2e8ad,a6
funcbdxea \1,37,\2e8ad,usp
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,38,\2xwe,(a0)+
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,39,\2xld,(a0)+
/*****************************************************************************************/
// word
/*****************************************************************************************/
// func.w ds,dx
//--------------------------------------------------------------------
funcweadx \1,40,\2dd,d0_off+2(a7)
funcweadx \1,41,\2dd,d1_off+2(a7)
funcweadx \1,42,\2dd,d2
funcweadx \1,43,\2dd,d3
funcweadx \1,44,\2dd,d4
funcweadx \1,45,\2dd,d5
funcweadx \1,46,\2dd,d6
funcweadx \1,47,\2dd,d7
//--------------------------------------------------------------------
// func.w ax,dx
//--------------------------------------------------------------------
funcweadx \1,48,\2dd,a0_off+2(a7)
funcweadx \1,49,\2dd,a1_off+2(a7)
funcweadx \1,4a,\2dd,a2
funcweadx \1,4b,\2dd,a3
funcweadx \1,4c,\2dd,a4
funcweadx \1,4d,\2dd,a5
funcweadx \1,4e,\2dd,a6
funcweadx \1,4f,\2ddd,usp
//--------------------------------------------------------------------
// func.w (ax),dx
//--------------------------------------------------------------------
funcweadx \1,50,\2dda,a0_off(a7)
funcweadx \1,51,\2dda,a1_off(a7)
funcweadx \1,52,\2dd,(a2)
funcweadx \1,53,\2dd,(a3)
funcweadx \1,54,\2dd,(a4)
funcweadx \1,55,\2dd,(a5)
funcweadx \1,56,\2dd,(a6)
funcweadx \1,57,\2dda,usp
//--------------------------------------------------------------------
// func.w (ax)+,dx
//--------------------------------------------------------------------
funcweadx \1,58,\2ddai,a0_off(a7)
funcweadx \1,59,\2ddai,a1_off(a7)
funcweadx \1,5a,\2dd,(a2)+
funcweadx \1,5b,\2dd,(a3)+
funcweadx \1,5c,\2dd,(a4)+
funcweadx \1,5d,\2dd,(a5)+
funcweadx \1,5e,\2dd,(a6)+
funcweadx \1,5f,\2ddai,usp
//--------------------------------------------------------------------
// func.w -(ax),dx
//--------------------------------------------------------------------
funcweadx \1,60,\2ddad,a0_off(a7)
funcweadx \1,61,\2ddad,a1_off(a7)
funcweadx \1,62,\2dd,-(a2)
funcweadx \1,63,\2dd,-(a3)
funcweadx \1,64,\2dd,-(a4)
funcweadx \1,65,\2dd,-(a5)
funcweadx \1,66,\2dd,-(a6)
funcweadx \1,67,\2ddad,usp
//--------------------------------------------------------------------
// func.w d16(ax),dx
//--------------------------------------------------------------------
funcweadx \1,68,\2d16ad,a0_off(a7)
funcweadx \1,69,\2d16ad,a1_off(a7)
funcweadx \1,6a,\2d16ad,a2
funcweadx \1,6b,\2d16ad,a3
funcweadx \1,6c,\2d16ad,a4
funcweadx \1,6d,\2d16ad,a5
funcweadx \1,6e,\2d16ad,a6
funcweadx \1,6f,\2d16ad,usp
//--------------------------------------------------------------------
// func.w d8(ax,dy),dx
//--------------------------------------------------------------------
funcweadx \1,70,\2d8ad,a0_off(a7)
funcweadx \1,71,\2d8ad,a1_off(a7)
funcweadx \1,72,\2d8ad,a2
funcweadx \1,73,\2d8ad,a3
funcweadx \1,74,\2d8ad,a4
funcweadx \1,75,\2d8ad,a5
funcweadx \1,76,\2d8ad,a6
funcweadx \1,77,\2d8ad,usp
//--------------------------------------------------------------------
// func.w xxx.w,dx
//--------------------------------------------------------------------
funcweadx \1,78,\2xwd,(a0)+
//--------------------------------------------------------------------
// func.w xxx.w,dx
//--------------------------------------------------------------------
funcweadx \1,79,\2xld,(a0)+
//--------------------------------------------------------------------
// func.w d16(pc),dx
//--------------------------------------------------------------------
funcweadx \1,7a,\2d16pcd,(a0)+
//--------------------------------------------------------------------
// func.w d8(pc,dy),dx
//--------------------------------------------------------------------
funcweadx \1,7b,\2d8pcd,(a0)+ (a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.w #im,dx
//--------------------------------------------------------------------
funcweadx \1,7c,\2dd,(a0)+
//--------------------------------------------------------------------
// func.w dy,ea
//--------------------------------------------------------------------
///--------------------------------------------------------------------
// func.w dx,dd -> addx subx etc.
//--------------------------------------------------------------------
.ifnc \2,and //platz f<>r exg
funcwdxea \1,40,\2dx,d0_off+2(a7)
funcwdxea \1,41,\2dx,d1_off+2(a7)
funcwdxea \1,42,\2dx,d2
funcwdxea \1,43,\2dx,d3
funcwdxea \1,44,\2dx,d4
funcwdxea \1,45,\2dx,d5
funcwdxea \1,46,\2dx,d6
funcwdxea \1,47,\2dx,d7
//--------------------------------------------------------------------
// func.w -(ax),-(ay) -> addx,subx
//--------------------------------------------------------------------
funcaxay \1,48,\2dax,a0_off(a7),w
funcaxay \1,49,\2dax,a1_off(a7).w
funcaxay \1,4a,\2dax,a2,w
funcaxay \1,4b,\2dax,a3,w
funcaxay \1,4c,\2dax,a4,w
funcaxay \1,4d,\2dax,a5,w
funcaxay \1,4e,\2dax,a6,w
funcaxay \1,4f,\2dax,usp,w
.endif
//--------------------------------------------------------------------
// func.w dy,(ax)
//--------------------------------------------------------------------
funcwdxea \1,50,\2eda,a0_off(a7)
funcwdxea \1,51,\2eda,a1_off(a7)
funcwdxea \1,52,\2dd,(a2)
funcwdxea \1,53,\2dd,(a3)
funcwdxea \1,54,\2dd,(a4)
funcwdxea \1,55,\2dd,(a5)
funcwdxea \1,56,\2dd,(a6)
funcwdxea \1,57,\2eda,usp
//--------------------------------------------------------------------
// func.w dy,(ax)+
//--------------------------------------------------------------------
funcwdxea \1,58,\2edai,a0_off(a7)
funcwdxea \1,59,\2edai,a1_off(a7)
funcwdxea \1,5a,\2edaid,(a2)
funcwdxea \1,5b,\2edaid,(a3)
funcwdxea \1,5c,\2edaid,(a4)
funcwdxea \1,5d,\2edaid,(a5)
funcwdxea \1,5e,\2edaid,(a6)
funcwdxea \1,5f,\2edai,usp
//--------------------------------------------------------------------
// func.w dy,-(ax)
//--------------------------------------------------------------------
funcwdxea \1,60,\2edad,a0_off(a7)
funcwdxea \1,61,\2edad,a1_off(a7)
funcwdxea \1,62,\2edadd,(a2)
funcwdxea \1,63,\2edadd,(a3)
funcwdxea \1,64,\2edadd,(a4)
funcwdxea \1,65,\2edadd,(a5)
funcwdxea \1,66,\2edadd,(a6)
funcwdxea \1,67,\2edad,usp
//--------------------------------------------------------------------
// func.w dy,d16(ax)
//--------------------------------------------------------------------
funcwdxea \1,68,\2e16ad,a0_off(a7)
funcwdxea \1,69,\2e16ad,a1_off(a7)
funcwdxea \1,6a,\2e16ad,a2
funcwdxea \1,6b,\2e16ad,a3
funcwdxea \1,6c,\2e16ad,a4
funcwdxea \1,6d,\2e16ad,a5
funcwdxea \1,6e,\2e16ad,a6
funcwdxea \1,6f,\2e16ad,usp
//--------------------------------------------------------------------
// func.w dy,d8(ax,dy)
//--------------------------------------------------------------------
funcwdxea \1,70,\2e8ad,a0_off(a7)
funcwdxea \1,71,\2e8ad,a1_off(a7)
funcwdxea \1,72,\2e8ad,a2
funcwdxea \1,73,\2e8ad,a3
funcwdxea \1,74,\2e8ad,a4
funcwdxea \1,75,\2e8ad,a5
funcwdxea \1,76,\2e8ad,a6
funcwdxea \1,77,\2e8ad,usp
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,78,\2xwe,(a0)+
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,79,\2xld,(a0)+
/*****************************************************************************************/
// long
/*****************************************************************************************/
//--------------------------------------------------------------------
// func.l -(ax),-(ay)
//--------------------------------------------------------------------
funcaxay \1,c8,\2dax,a0_off(a7),l
funcaxay \1,c9,\2dax,a1_off(a7).l
funcaxay \1,ca,\2dax,a2,l
funcaxay \1,cb,\2dax,a3,l
funcaxay \1,cc,\2dax,a4,l
funcaxay \1,cd,\2dax,a5,l
funcaxay \1,ce,\2dax,a6,l
funcaxay \1,cf,\2dax,usp,l
//--------------------------------------------------------------------
// func.l d8(ax,dy),dx
//--------------------------------------------------------------------
funcleadx \1,b0,\2d8ad,a0_off(a7)
funcleadx \1,b1,\2d8ad,a1_off(a7)
funcleadx \1,b2,\2d8ad,a2
funcleadx \1,b3,\2d8ad,a3
funcleadx \1,b4,\2d8ad,a4
funcleadx \1,b5,\2d8ad,a5
funcleadx \1,b6,\2d8ad,a6
funcleadx \1,b7,\2d8ad,usp
//--------------------------------------------------------------------
// func.l d8(pc,dy),dx
//--------------------------------------------------------------------
funcleadx \1,bb,\2d8pcd,(a0)+ (a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.l dy,d8(ax,dy)
//--------------------------------------------------------------------
funcldxea \1,b0,\2e8ad,a0_off(a7)
funcldxea \1,b1,\2e8ad,a1_off(a7)
funcldxea \1,b2,\2e8ad,a2
funcldxea \1,b3,\2e8ad,a3
funcldxea \1,b4,\2e8ad,a4
funcldxea \1,b5,\2e8ad,a5
funcldxea \1,b6,\2e8ad,a6
funcldxea \1,b7,\2e8ad,usp
/******************************************************/
// adress register
/******************************************************/
//--------------------------------------------------------------------
// func.w ea,ax
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// func.w dx,ax
//--------------------------------------------------------------------
funcweaax \1,c0,\2aw,d0
funcweaax \1,c1,\2aw,d1
funcweaax \1,c2,\2aw,d2
funcweaax \1,c3,\2aw,d3
funcweaax \1,c4,\2aw,d4
funcweaax \1,c5,\2aw,d5
funcweaax \1,c6,\2aw,d6
funcweaax \1,c7,\2aw,d7
//--------------------------------------------------------------------
// func.w ay,ax
//--------------------------------------------------------------------
funcweaax \1,c8,\2aw,a0
funcweaax \1,c9,\2aw,a1
funcweaax \1,ca,\2aw,a2
funcweaax \1,cb,\2aw,a3
funcweaax \1,cc,\2aw,a4
funcweaax \1,cd,\2aw,a5
funcweaax \1,ce,\2aw,a6
funcweaax \1,cf,\2awu,a7
//--------------------------------------------------------------------
// func.w (ay),ax
//--------------------------------------------------------------------
funcweaax \1,d0,\2aw,(a0)
funcweaax \1,d1,\2aw,(a1)
funcweaax \1,d2,\2aw,(a2)
funcweaax \1,d3,\2aw,(a3)
funcweaax \1,d4,\2aw,(a4)
funcweaax \1,d5,\2aw,(a5)
funcweaax \1,d6,\2aw,(a6)
funcweaax \1,d7,\2awu,(a7)
//--------------------------------------------------------------------
// func.w (ay)+,ax
//--------------------------------------------------------------------
funcweaax \1,d8,\2aw,(a0)+
funcweaax \1,d9,\2aw,(a1)+
funcweaax \1,da,\2aw,(a2)+
funcweaax \1,db,\2aw,(a3)+
funcweaax \1,dc,\2aw,(a4)+
funcweaax \1,dd,\2aw,(a5)+
funcweaax \1,de,\2aw,(a6)+
funcweaax \1,df,\2awu,(a7)+
//--------------------------------------------------------------------
// func.w -(ay),ax
//--------------------------------------------------------------------
funcweaax \1,e0,\2aw,-(a0)
funcweaax \1,e1,\2aw,-(a1)
funcweaax \1,e2,\2aw,-(a2)
funcweaax \1,e3,\2aw,-(a3)
funcweaax \1,e4,\2aw,-(a4)
funcweaax \1,e5,\2aw,-(a5)
funcweaax \1,e6,\2aw,-(a6)
funcweaax \1,e7,\2awu,-(a7)
//--------------------------------------------------------------------
// func.w d16(ay),ax
//--------------------------------------------------------------------
funcweaaxn \1,e8,\2awd16a,a0_off(a7)
funcweaaxn \1,e9,\2awd16a,a1_off(a7)
funcweaaxn \1,ea,\2awd16a,a2
funcweaaxn \1,eb,\2awd16a,a3
funcweaaxn \1,ec,\2awd16a,a4
funcweaaxn \1,ed,\2awd16a,a5
funcweaaxn \1,ee,\2awd16a,a6
funcweaaxn \1,ef,\2awd16a,usp
//--------------------------------------------------------------------
// func.w d8(ay,dy),ax
//--------------------------------------------------------------------
funcweaaxn \1,f0,\2awd8a,a0_off(a7)
funcweaaxn \1,f1,\2awd8a,a1_off(a7)
funcweaaxn \1,f2,\2awd8a,a2
funcweaaxn \1,f3,\2awd8a,a3
funcweaaxn \1,f4,\2awd8a,a4
funcweaaxn \1,f5,\2awd8a,a5
funcweaaxn \1,f6,\2awd8a,a6
funcweaaxn \1,f7,\2awd8a,usp
//--------------------------------------------------------------------
// func.w xxx.w,ax
//--------------------------------------------------------------------
funcweaaxn \1,f8,\2awxwax,(a0)+
//--------------------------------------------------------------------
// func.w xxxlw,ax
//--------------------------------------------------------------------
funcweaaxn \1,f9,\2awxlax,(a0)+
//--------------------------------------------------------------------
// func.w d16(pc),ax
//--------------------------------------------------------------------
funcweaaxn \1,fa,\2awd16pcax,(a0)+
//--------------------------------------------------------------------
// func.w d8(pc,dy),ax
//--------------------------------------------------------------------
funcweaaxn \1,fb,\2awd8pcax,(a0)+ //(a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.w #im,ax
//--------------------------------------------------------------------
funcweaaxn \1,fc,\2awim,(a0)+
//--------------------------------------------------------------------
// ende
.endm;
//--------------------------------------------------------------------
// byt
funcbeadx:.macro // function byt: im,dx
ii_0x\10\2:
\3 \4,d0_off+3(a7),b
ii_0x\12\2:
\3 \4,d1_off+3(a7),b
ii_0x\14\2:
\3 \4,d2,b
ii_0x\16\2:
\3 \4,d3,b
ii_0x\18\2:
\3 \4,d4,b
ii_0x\1a\2:
\3 \4,d5,b
ii_0x\1c\2:
\3 \4,d6,b
ii_0x\1e\2:
\3 \4,d7,b
.endm;
funcbdxea:.macro // ea(\4) function(\3) dx -> ea
ii_0x\11\2:
\3 d0_off+3(a7),\4,b
ii_0x\13\2:
\3 d1_off+3(a7),\4,b
ii_0x\15\2:
\3 d2,\4,b
ii_0x\17\2:
\3 d3,\4,b
ii_0x\19\2:
\3 d4,\4,b
ii_0x\1b\2:
\3 d5,\4,b
ii_0x\1d\2:
\3 d6,\4,b
ii_0x\1f\2:
\3 d7,\4,b
.endm;
//--------------------------------------------------------------------
// word
funcweadx:.macro // dx function(\3) ea(\4) -> dx
ii_0x\10\2:
\3 \4,d0_off+2(a7),w
ii_0x\12\2:
\3 \4,d1_off+2(a7),w
ii_0x\14\2:
\3 \4,d2,w
ii_0x\16\2:
\3 \4,d3,w
ii_0x\18\2:
\3 \4,d4,w
ii_0x\1a\2:
\3 \4,d5,w
ii_0x\1c\2:
\3 \4,d6,w
ii_0x\1e\2:
\3 \4,d7,w
.endm;
funcwdxea:.macro // ea(\4) function(\3) dx -> ea
ii_0x\11\2:
\3 d0_off+2(a7),\4,w
ii_0x\13\2:
\3 d1_off+2(a7),\4,w
ii_0x\15\2:
\3 d2,\4,w
ii_0x\17\2:
\3 d3,\4,w
ii_0x\19\2:
\3 d4,\4,w
ii_0x\1b\2:
\3 d5,\4,w
ii_0x\1d\2:
\3 d6,\4,w
ii_0x\1f\2:
\3 d7,\4,w
.endm;
//--------------------------------------------------------------------
// long
funcleadx:.macro // dx function(\3) ea(\4) -> dx
ii_0x\10\2:
\3 \4,d0_off(a7),w
ii_0x\12\2:
\3 \4,d1_off(a7),w
ii_0x\14\2:
\3 \4,d2,w
ii_0x\16\2:
\3 \4,d3,w
ii_0x\18\2:
\3 \4,d4,w
ii_0x\1a\2:
\3 \4,d5,w
ii_0x\1c\2:
\3 \4,d6,w
ii_0x\1e\2:
\3 \4,d7,w
.endm;
funcldxea:.macro // ea(\4) function(\3) dx -> ea
ii_0x\11\2:
\3 d0_off(a7),\4,w
ii_0x\13\2:
\3 d1_off(a7),\4,w
ii_0x\15\2:
\3 d2,\4,w
ii_0x\17\2:
\3 d3,\4,w
ii_0x\19\2:
\3 d4,\4,w
ii_0x\1b\2:
\3 d5,\4,w
ii_0x\1d\2:
\3 d6,\4,w
ii_0x\1f\2:
\3 d7,\4,w
.endm;
//--------------------------------------------------------------
// address
funcweaax:.macro // ax function(\3) ea(\4)(ext long!) -> ax
ii_0x\10\2:
\3 \4,a0
ii_0x\12\2:
\3 \4,a1
ii_0x\14\2:
\3 \4,a2
ii_0x\16\2:
\3 \4,a3
ii_0x\18\2:
\3 \4,a4
ii_0x\1a\2:
\3 \4,a5
ii_0x\1c\2:
\3 \4,a6
ii_0x\1e\2:
\3a7 \4,a7 // "a7" beachten wegen usp
.endm;
funcweaaxn:.macro // ax function(\3) ea(\4)(ext long!) -> ax
ii_0x\10\2:
\3 \4,a0_off(a7)
ii_0x\12\2:
\3 \4,a1_off(a7)
ii_0x\14\2:
\3 \4,a2
ii_0x\16\2:
\3 \4,a3
ii_0x\18\2:
\3 \4,a4
ii_0x\1a\2:
\3 \4,a5
ii_0x\1c\2:
\3 \4,a6
ii_0x\1e\2:
\3 \4,usp
.endm;
//--------------------------------------------------------------
// byt, word, long
//--------------------------------------------------------------
funcaxay:.macro // ea(\4) function(\3) dx -> ea,\5 = size
ii_0x\11\2:
\3 a0_off(a7),\4,\5
ii_0x\13\2:
\3 a1_off(a7),\4,\5
ii_0x\15\2:
\3 a2,\4,\5
ii_0x\17\2:
\3 a3,\4,\5
ii_0x\19\2:
\3 a4,\4,\5
ii_0x\1b\2:
\3 a5,\4,\5
ii_0x\1d\2:
\3 a6,\4,\5
ii_0x\1f\2:
\3 usp,\4,\5
.endm;

59
headers/ii_jmp.h Normal file
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//--------------------------------------------------------------------
// extension word format missing
//--------------------------------------------------------------------
ii_\1_func:.macro
ii_0x\20:
#ifdef halten_\1
halt
#endif
move.l a0_off(a7),a1
\1_macro
ii_0x\21:
#ifdef halten_\1
halt
#endif
move.l a1_off(a7),a1
\1_macro
ii_0x\22:
#ifdef halten_\1
halt
#endif
move.l a2,a1
\1_macro
ii_0x\23:
#ifdef halten_\1
halt
#endif
move.l a3,a1
\1_macro
ii_0x\24:
#ifdef halten_\1
halt
#endif
move.l a4,a1
\1_macro
ii_0x\25:
#ifdef halten_\1
halt
#endif
move.l a5,a1
\1_macro
ii_0x\26:
#ifdef halten_\1
halt
#endif
move.l a6,a1
\1_macro
ii_0x\27:
#ifdef halten_\1
halt
#endif
move.l usp,a1
\1_macro
ii_0x\2b:
#ifdef halten_\1
halt
#endif
move.l a0,a1
\1_macro
.endm

105
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//-------------------------------------------------------------------
// lea
//-------------------------------------------------------------------
.text
ii_lea_lset:.macro
ii_lset_dxu 4,f0 // lea d8(a0,dy.w),a0-a7
ii_lset_dxu 4,f1 // lea d8(a1,dy.w),a0-a7
ii_lset_dxu 4,f2 // lea d8(a2,dy.w),a0-a7
ii_lset_dxu 4,f3 // lea d8(a3,dy.w),a0-a7
ii_lset_dxu 4,f4 // lea d8(a4,dy.w),a0-a7
ii_lset_dxu 4,f5 // lea d8(a5,dy.w),a0-a7
ii_lset_dxu 4,f6 // lea d8(a6,dy.w),a0-a7
ii_lset_dxu 4,f7 // lea d8(a7,dy.w),a0-a7
ii_lset_dxu 4,fb // lea d8(pc,dy.w),a0-a7
.endm
//---------------------------------------------------------------------------------------------
// function
//---------------------------------------------------------------------------------------------
ii_lea_sub:.macro
ii_0x4\1\2:
#ifdef halten_lea
halt
#endif
move.l \4,a1
jsr ewf
move.l a1,\3
ii_end
.endm
ii_lea_func:.macro
//lea d8(ax,dy.w),a0-a7
ii_lea_sub 1,f0,a0_off(a7),a0_off(a7)
ii_lea_sub 1,f1,a0_off(a7),a1_off(a7)
ii_lea_sub 1,f2,a0_off(a7),a2
ii_lea_sub 1,f3,a0_off(a7),a3
ii_lea_sub 1,f4,a0_off(a7),a4
ii_lea_sub 1,f5,a0_off(a7),a5
ii_lea_sub 1,f6,a0_off(a7),a6
ii_lea_sub 1,f7,a0_off(a7),usp
ii_lea_sub 3,f0,a1_off(a7),a0_off(a7)
ii_lea_sub 3,f1,a1_off(a7),a1_off(a7)
ii_lea_sub 3,f2,a1_off(a7),a2
ii_lea_sub 3,f3,a1_off(a7),a3
ii_lea_sub 3,f4,a1_off(a7),a4
ii_lea_sub 3,f5,a1_off(a7),a5
ii_lea_sub 3,f6,a1_off(a7),a6
ii_lea_sub 3,f7,a1_off(a7),usp
ii_lea_sub 5,f0,a2,a0_off(a7)
ii_lea_sub 5,f1,a2,a1_off(a7)
ii_lea_sub 5,f2,a2,a2
ii_lea_sub 5,f3,a2,a3
ii_lea_sub 5,f4,a2,a4
ii_lea_sub 5,f5,a2,a5
ii_lea_sub 5,f6,a2,a6
ii_lea_sub 5,f7,a2,usp
ii_lea_sub 7,f0,a3,a0_off(a7)
ii_lea_sub 7,f1,a3,a1_off(a7)
ii_lea_sub 7,f2,a3,a2
ii_lea_sub 7,f3,a3,a3
ii_lea_sub 7,f4,a3,a4
ii_lea_sub 7,f5,a3,a5
ii_lea_sub 7,f6,a3,a6
ii_lea_sub 7,f7,a3,usp
ii_lea_sub 9,f0,a4,a0_off(a7)
ii_lea_sub 9,f1,a4,a1_off(a7)
ii_lea_sub 9,f2,a4,a2
ii_lea_sub 9,f3,a4,a3
ii_lea_sub 9,f4,a4,a4
ii_lea_sub 9,f5,a4,a5
ii_lea_sub 9,f6,a4,a6
ii_lea_sub 9,f7,a4,usp
ii_lea_sub b,f0,a5,a0_off(a7)
ii_lea_sub b,f1,a5,a1_off(a7)
ii_lea_sub b,f2,a5,a2
ii_lea_sub b,f3,a5,a3
ii_lea_sub b,f4,a5,a4
ii_lea_sub b,f5,a5,a5
ii_lea_sub b,f6,a5,a6
ii_lea_sub b,f7,a6,usp
ii_lea_sub d,f0,a6,a0_off(a7)
ii_lea_sub d,f1,a6,a1_off(a7)
ii_lea_sub d,f2,a6,a2
ii_lea_sub d,f3,a6,a3
ii_lea_sub d,f4,a6,a4
ii_lea_sub d,f5,a6,a5
ii_lea_sub d,f6,a6,a6
ii_lea_sub d,f7,a6,usp
ii_lea_sub f,f0,usp,a0_off(a7)
ii_lea_sub f,f1,usp,a1_off(a7)
ii_lea_sub f,f2,usp,a2
ii_lea_sub f,f3,usp,a3
ii_lea_sub f,f4,usp,a4
ii_lea_sub f,f5,usp,a5
ii_lea_sub f,f6,usp,a6
ii_lea_sub f,f7,usp,usp
// lea d8(pc,dy.w),az
ii_lea_sub 1,fb,a0_off(a7),a0
ii_lea_sub 3,fb,a1_off(a7),a0
ii_lea_sub 5,fb,a2,a0
ii_lea_sub 7,fb,a3,a0
ii_lea_sub 9,fb,a4,a0
ii_lea_sub b,fb,a5,a0
ii_lea_sub d,fb,a6,a0
ii_lea_sub f,fb,usp,a0
.endm

144
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/*******************************************************/
// constanten
/*******************************************************/
.extern ___RAMBAR1
.extern _rt_cacr
.extern _rt_mod
.extern _rt_ssp
.extern _rt_usp
.extern _rt_vbr
.extern _d0_save
.extern _a7_save
ii_ss = 16
d0_off = 0
d1_off = 4
a0_off = 8
a1_off = 12
format_off = 16
sr_off = 18
ccr_off = 19
pc_off = 20
#define table 0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle -> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle
/*******************************************************/
// allgemeine macros
/*******************************************************/
ii_end: .macro
move.l a0,pc_off(a7)
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7
rte
.endm;
set_cc0:.macro
move.w ccr,d0
move.b d0,ccr_off(a7)
.endm;
ii_esr: .macro // geht nicht!!??
movem.l (a7),d0/d1/a0/a1
lea ii_ss+8(a7),a7 // stack erh<72>hen
move.w d0,_d0_save // d0.w sicheren
move.w -6(a7),d0 // sr holen
move.w d0,sr // sr setzen
nop
move.w _d0_save,d0 // d0.w zur<75>ck
.endm;
ii_end_mvm:.macro
move.l a0_off(a7),a0
lea 16(a7),a7
rte
.endm;
ii_endj:.macro
movem.l (a7),d0/d1/a0/a1 // register zur<75>ck
lea ii_ss(a7),a7 // korr
rte // ende
.endm;
set_nzvc:.macro // set ccr bits nzvc
move.w ccr,d1
bclr #4,d1
btst #4,ccr_off(a7)
beq snzvc2\@
bset #4,d1
snzvc2\@:
move.b d1,ccr_off(a7)
.endm;
set_cc1:.macro
move.w ccr,d1
move.b d1,ccr_off(a7)
.endm;
set_cc_b:.macro
move.w ccr,d1
btst #7,d0 // byt negativ?
beq set_cc_b2\@
bset #3,d1 // make negativ
set_cc_b2\@:
move.b d1,ccr_off(a7)
.endm;
set_cc_w:.macro
move.w ccr,d1
btst #15,d0 // byt negativ?
beq set_cc_w2\@
bset #3,d1 // make negativ
set_cc_w2\@:
move.b d1,ccr_off(a7)
.endm;
get_pc: .macro
lea.l (a0),a1
.endm;
//--------------------------------------------------------------------
ii_lset:.macro
lea table+\1*4,a0
move.l #ii_\1,(a0)
.endm;
ii_lset_dx:.macro // 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40
ii_lset_dxg \1,\2
ii_lset_dxu \1,\2
.endm;
ii_lset_dxg:.macro // gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40
lea table+0x\10\2*4,a0
move.l #ii_0x\10\2,(a0)
lea 0x800(a0),a0 // 4 * 0x200
move.l #ii_0x\12\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\14\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\16\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\18\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1a\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1c\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1e\2,(a0)
.endm;
ii_lset_dxu:.macro // ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40
lea table+0x\11\2*4,a0
move.l #ii_0x\11\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\13\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\15\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\17\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\19\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1b\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1d\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1f\2,(a0)
.endm;

1271
headers/ii_move.h Normal file
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//***********************************************************************************/
// movem
//***********************************************************************************/
ii_movem_lset: .macro
// movem.l rx,xxx.L
ii_lset 0x48f9
// movem.l xxx.L,rx
ii_lset 0x4cf9
// movem.w rx,xxx.L
ii_lset 0x48b9
// movem.w xxx.L,rx
ii_lset 0x4cb9
// movem.l rx,-(ax)
ii_lset 0x48e0
ii_lset 0x48e1
ii_lset 0x48e2
ii_lset 0x48e3
ii_lset 0x48e4
ii_lset 0x48e5
ii_lset 0x48e6
ii_lset 0x48e7
// movem.l (ax)+,rx
ii_lset 0x4cd8
ii_lset 0x4cd9
ii_lset 0x4cda
ii_lset 0x4cdb
ii_lset 0x4cdc
ii_lset 0x4cdd
ii_lset 0x4cde
ii_lset 0x4cdf
.endm
//***********************************************************************************/
ii_movem_func: .macro
//-------------------------------------------------------------------
// movem.l
//--------------------------------------------------------------------
// movem.l (ax)+,reg
//--------------------------------------------------------------------
.long 0
az_reg_table:
.byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0
.byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0
//-------------------------------------------------------------------------------
ii_0x48e0: // movem.l reglist,-(a0)
mvm_mem_macro 0x48d0,a0_off(a7),2
ii_0x48e1: // movem.l reglist,-(a1)
mvm_mem_macro 0x48d1,a1_off(a7),2
ii_0x48e2: // movem.l reglist,-(a2)
mvm_mem_macro 0x48d2,a2,2
ii_0x48e3: // movem.l reglist,-(a3)
mvm_mem_macro 0x48d3,a3,2
ii_0x48e4: // movem.l reglist,-(a4)
mvm_mem_macro 0x48d4,a4,2
ii_0x48e5: // movem.l reglist,-(a5)
mvm_mem_macro 0x48d5,a5,2
ii_0x48e6: // movem.l reglist,-(a6)
mvm_mem_macro 0x48d6,a6,2
ii_0x48e7: // movem.l reglist,-(a7)
mvm_mem_macro 0x48d7,usp,2
//-------------------------------------------------------------------------------
ii_0x4cd8: // movem.l (a0)+,reglist
mvm_reg_macro 0x4cd0,0x41e8,2
ii_0x4cd9: // movem.l (a1)+,reglist
mvm_reg_macro 0x4cd1,0x43e9,2
ii_0x4cda: // movem.l (a2)+,reglist
mvm_reg_macro 0x4cd2,0x45ea,2
ii_0x4cdb: // movem.l (a3)+,reglist
mvm_reg_macro 0x4cd3,0x47eb,2
ii_0x4cdc: // movem.l (a4)+,reglist
mvm_reg_macro 0x4cd4,0x49ec,2
ii_0x4cdd: // movem.l (a5)+,reglist
mvm_reg_macro 0x4cd5,0x4bed,2
ii_0x4cde: // movem.l (a6)+,reglist
mvm_reg_macro 0x4cd6,0x4dee,2
ii_0x4cdf: // movem.l (a7)+,reglist
mvm_reg_macro 0x4cd7,0x4fef,2
//----------------------------------------------------------------------------
ii_0x48f9: // movem.l reg,xxx.L
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemrm_macro l
//---------------------------------------------------------------------------------------------
ii_0x4cf9: // movem.l xxx.L,reg
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemmr_macro l
//----------------------------------------------------------------------------
ii_0x48b9: // movem.w reg,xxx.L
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemrm_macro w
//---------------------------------------------------------------------------------------------
ii_0x4cb9: // movem.w xxx.L,reg
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemmr_macro w
.endm
//==============================================================
mvm_mem_macro:.macro
#ifdef halten_movem
halt
#endif
lea az_reg_table,a1
mvz.b (a0),d1
mvz.b 0(a1,d1)+,d0
mvz.b 1(a0),d1
mvz.b 0(a1,d1)+,d1
add.l d0,d1
lsl.l #\3,d1 // * anzahl byts pro wert
move.l \2,a1
sub.l d1,a1 // ax-anzahl byts
move.l a1,\2
lea ___RAMBAR1,a1
move.l a1,pc_off(a7)
move.l a1,d0
addq.l #1,d0
movec d0,RAMBAR1
move.w #\1,(a1)+ // movem.x reg_list,-(a7)
move.w (a0)+,(a1)+ // register list
move.w #0x4ef9,(a1)+ // jmp.l
move.l a0,(a1) // r<>cksprungadresse
move.l #___RAMBAR1 + 0x81,d0 // instruction
movec d0,RAMBAR1
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm
//---------------------------------------------------------------------------------
mvm_reg_macro:.macro
#ifdef halten_movem
halt
#endif
lea az_reg_table,a1
mvz.b (a0),d1
mvz.b 0(a1,d1)+,d0
mvz.b 1(a0),d1
mvz.b 0(a1,d1)+,d1
add.l d0,d1
lea ___RAMBAR1,a1
move.l a1,pc_off(a7)
move.l a1,d0
addq.l #1,d0
movec d0,RAMBAR1
move.w #\1,(a1)+ // movem.x (ax),reg_list
move.w (a0)+,(a1)+ // register list
move.w #\2,(a1)+ // lea 0(ax),ax
lsl.l #\3,d1 // * anzahl byts pro wert
move.w d1,(a1)+ // offset von lea
move.w #0x4ef9,(a1)+ // jmp.l
move.l a0,(a1) // r<>cksprungadresse
move.l #___RAMBAR1 + 0x81,d0 // instruction
movec d0,RAMBAR1
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm
//---------------------------------------------------------------------------------
movemrm_macro:.macro // in d0 register liste, in a1 zieladresse
#ifdef halten_movem
halt
#endif
tst.b d0 // datenregister zu verschieben?
bne mrm_dx\@ // ja->
lsr.l #8,d0 // sonst zu addressregister
jmp mmrm_nd7\@ // ->
mrm_dx\@:
lsr.l #1,d0
bcc mmrm_nd0\@
.ifc 1,l
move.l d0_off(a7),(a1)+
.else
move.w d0_off+2(a7),(a1)+
.endif
mmrm_nd0\@:
lsr.l #1,d0
bcc mmrm_nd1\@
.ifc 1,l
move.l d1_off(a7),(a1)+
.else
move.w d1_off+2(a7),(a1)+
.endif
mmrm_nd1\@:
lsr.l #1,d0
bcc mmrm_nd2\@
move.\1 d2,(a1)+
mmrm_nd2\@:
lsr.l #1,d0
bcc mmrm_nd3\@
move.\1 d3,(a1)+
mmrm_nd3\@:
lsr.l #1,d0
bcc mmrm_nd4\@
move.\1 d4,(a1)+
mmrm_nd4\@:
lsr.l #1,d0
bcc mmrm_nd5\@
move.\1 d5,(a1)+
mmrm_nd5\@:
lsr.l #1,d0
bcc mmrm_nd6\@
move.l d6,(a1)+
mmrm_nd6\@:
lsr.l #1,d0
bcc mmrm_nd7\@
move.\1 d7,(a1)+
mmrm_nd7\@:
tst.b d0 // addressregister zu verschieben?
beq mmrm_na7\@
lsr.l #1,d0
bcc mmrm_na0\@
.ifc 1,l
move.l a0_off(a7),(a1)+
.else
move.w a0_off+2(a7),(a1)+
.endif
mmrm_na0\@:
lsr.l #1,d0
bcc mmrm_na1\@
.ifc 1,l
move.l a1_off(a7),(a1)+
.else
move.w a1_off+2(a7),(a1)+
.endif
mmrm_na1\@:
lsr.l #1,d0
bcc mmrm_na2\@
move.\1 a2,(a1)+
mmrm_na2\@:
lsr.l #1,d0
bcc mmrm_na3\@
move.\1 a3,(a1)+
mmrm_na3\@:
lsr.l #1,d0
bcc mmrm_na4\@
move.\1 a4,(a1)+
mmrm_na4\@:
lsr.l #1,d0
bcc mmrm_na5\@
move.\1 a5,(a1)+
mmrm_na5\@:
lsr.l #1,d0
bcc mmrm_na6\@
move.\1 a6,(a1)+
mmrm_na6\@:
lsr.l #1,d0
bcc mmrm_na7\@
move.l a0,d1 // sichern
move.l usp,a0 // ist ja usp
move.\1 a0,(a1)+ // nach a0
move.l d1,a0 // pc zur<75>ck
mmrm_na7\@:
ii_end
.endm
//---------------------------------------------------------------------------------------------
movemmr_macro:.macro // in d0 register liste, in a1 source adr
#ifdef halten_movem
halt
#endif
tst.b d0 // datenregister zu verschieben?
bne mmr_dx\@ // ja->
lsr.l #8,d0 // sonst zu addressregister
bra mmmr_nd7\@ // ->
mmr_dx\@:
lsr.l #1,d0
bcc mmmr_nd0\@
.ifc 1,l
move.l (a1)+,d0_off(a7)
.else
move.w (a1)+,d0_off+2(a7)
.endif
mmmr_nd0\@:
lsr.l #1,d0
bcc mmmr_nd1\@
.ifc 1,l
move.l (a1)+,d1_off(a7)
.else
move.w (a1)+,d1_off+2(a7)
.endif
mmmr_nd1\@:
lsr.l #1,d0
bcc mmmr_nd2\@
move.\1 (a1)+,d2
mmmr_nd2\@:
lsr.l #1,d0
bcc mmmr_nd3\@
move.\1 (a1)+,d3
mmmr_nd3\@:
lsr.l #1,d0
bcc mmmr_nd4\@
move.\1 (a1)+,d4
mmmr_nd4\@:
lsr.l #1,d0
bcc mmmr_nd5\@
move.\1 (a1)+,d5
mmmr_nd5\@:
lsr.l #1,d0
bcc mmmr_nd6\@
move.\1 (a1)+,d6
mmmr_nd6\@:
lsr.l #1,d0
bcc mmmr_nd7\@
move.\1 (a1)+,d7
mmmr_nd7\@:
tst.b d0 // addressregister zu verschieben?
beq mmmr_na7\@ // nein->
lsr.l #1,d0
bcc mmmr_na0\@
.ifc 1,l
move.l (a1)+,a0_off(a7)
.else
move.w (a1)+,a0_off+2(a7)
.endif
mmmr_na0\@:
lsr.l #1,d0
bcc mmmr_na1\@
.ifc 1,l
move.l (a1)+,a1_off(a7)
.else
move.w (a1)+,a1_off+2(a7)
.endif
mmmr_na1\@:
lsr.l #1,d0
bcc mmmr_na2\@
move.\1 (a1)+,a2
mmmr_na2\@:
lsr.l #1,d0
bcc mmmr_na3\@
move.\1 (a1)+,a3
mmmr_na3\@:
lsr.l #1,d0
bcc mmmr_na4\@
move.\1 (a1)+,a4
mmmr_na4\@:
lsr.l #1,d0
bcc mmmr_na5\@
move.\1 (a1)+,a5
mmmr_na5\@:
lsr.l #1,d0
bcc mmmr_na6\@
move.\1 (a1)+,a6
mmmr_na6\@:
lsr.l #1,d0
bcc mmmr_na7\@
move.\1 (a1)+,a1 // nach a0
move.l a1,usp // war ja usp
mmmr_na7\@:
ii_end
.endm

179
headers/ii_movep.h Normal file
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//--------------------------------------------------------------------
// movep
//--------------------------------------------------------------------
.text
ii_movep_lset:.macro
ii_lset_opeau 01,0 //movep.w d(a0-7),d0
ii_lset_opeau 03,0 //movep.w d(a0-7),d1
ii_lset_opeau 05,0 //movep.w d(a0-7),d2
ii_lset_opeau 07,0 //movep.w d(a0-7),d3
ii_lset_opeau 09,0 //movep.w d(a0-7),d4
ii_lset_opeau 0b,0 //movep.w d(a0-7),d5
ii_lset_opeau 0d,0 //movep.w d(a0-7),d6
ii_lset_opeau 0f,0 //movep.w d(a0-7),d7
ii_lset_opeau 01,4 //movep.w d0,d(a0-7)
ii_lset_opeau 03,4 //movep.w d1,d(a0-7)
ii_lset_opeau 05,4 //movep.w d2,d(a0-7)
ii_lset_opeau 07,4 //movep.w d3,d(a0-7)
ii_lset_opeau 09,4 //movep.w d4,d(a0-7)
ii_lset_opeau 0b,4 //movep.w d5,d(a0-7)
ii_lset_opeau 0d,4 //movep.w d6,d(a0-7)
ii_lset_opeau 0f,4 //movep.w d7,d(a0-7)
ii_lset_opeau 01,8 //movep.l d(a0-7),d0
ii_lset_opeau 03,8 //movep.l d(a0-7),d1
ii_lset_opeau 05,8 //movep.l d(a0-7),d2
ii_lset_opeau 07,8 //movep.l d(a0-7),d3
ii_lset_opeau 09,8 //movep.l d(a0-7),d4
ii_lset_opeau 0b,8 //movep.l d(a0-7),d5
ii_lset_opeau 0d,8 //movep.l d(a0-7),d6
ii_lset_opeau 0f,8 //movep.l d(a0-7),d7
ii_lset_opeau 01,c //movep.l d0,d(a0-7)
ii_lset_opeau 03,c //movep.l d1,d(a0-7)
ii_lset_opeau 05,c //movep.l d2,d(a0-7)
ii_lset_opeau 07,c //movep.l d3,d(a0-7)
ii_lset_opeau 09,c //movep.l d4,d(a0-7)
ii_lset_opeau 0b,c //movep.l d5,d(a0-7)
ii_lset_opeau 0d,c //movep.l d6,d(a0-7)
ii_lset_opeau 0f,c //movep.l d7,d(a0-7)
.endm
//---------------------------------------------------------------------------------------------
ii_movep_func:.macro
//movep.w d(a0-7),d0-7
ii_movep 010,d0_off(a7),wad
ii_movep 030,d1_off(a7),wad
ii_movep 050,d2,wad
ii_movep 070,d3,wad
ii_movep 090,d4,wad
ii_movep 0b0,d5,wad
ii_movep 0d0,d6,wad
ii_movep 0f0,d7,wad
//movep.w d0-7,d(a0-7)
ii_movep 014,d0_off(a7),wda
ii_movep 034,d1_off(a7),wda
ii_movep 054,d2,wda
ii_movep 074,d3,wda
ii_movep 094,d4,wda
ii_movep 0b4,d5,wda
ii_movep 0d4,d6,wda
ii_movep 0f4,d7,wda
//movep.l d(a0-7),d0-7
ii_movep 018,d0_off(a7),lad
ii_movep 038,d1_off(a7),lad
ii_movep 058,d2,lad
ii_movep 078,d3,lad
ii_movep 098,d4,lad
ii_movep 0b8,d5,lad
ii_movep 0d8,d6,lad
ii_movep 0f8,d7,lad
//movep.l d0-7,d(a0-7)
ii_movep 01c,d0_off(a7),lda
ii_movep 03c,d1_off(a7),lda
ii_movep 05c,d2,lda
ii_movep 07c,d3,lda
ii_movep 09c,d4,lda
ii_movep 0bc,d5,lda
ii_movep 0dc,d6,lda
ii_movep 0fc,d7,lda
.endm
//---------------------------------------------------------------------------------------------
ii_movep:.macro //1=code ziffer 1-3 2=register 3=art
ii_0x\18:
#ifdef halten_movep
halt
#endif
move.l a0_off(a7),a1
ii_movep\3_up1 \2
ii_0x\19:
#ifdef halten_movep
halt
#endif
move.l a1_off(a7),a1
ii_movep\3_up1 \2
ii_0x\1a:
#ifdef halten_movep
halt
#endif
move.l a2,a1
ii_movep\3_up1 \2
ii_0x\1b:
#ifdef halten_movep
halt
#endif
move.l a3,a1
ii_movep\3_up1 \2
ii_0x\1c:
#ifdef halten_movep
halt
#endif
move.l a4,a1
ii_movep\3_up1 \2
ii_0x\1d:
#ifdef halten_movep
halt
#endif
move.l a5,a1
ii_movep\3_up1 \2
ii_0x\1e:
#ifdef halten_movep
halt
#endif
move.l a6,a1
ii_movep\3_up1 \2
ii_0x\1f:
#ifdef halten_movep
halt
#endif
move.l usp,a1
ii_movep\3_up1 \2
.endm
ii_movepwad_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.b (a1),d0
lsl.l #8,d0
move.b 2(a1,d1.l),d0
move.w d0,\1
ii_end
.endm
ii_movepwda_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.w \1,d0
move.b d0,2(a1)
lsr.l #8,d0
move.b d0,(a1)
ii_end
.endm
ii_moveplad_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.b (a1),d0
lsl.l #8,d0
move.b 2(a1),d0
lsl.l #8,d0
move.b 4(a1),d0
lsl.l #8,d0
move.b 6(a1),d0
move.l d0,\1
ii_end
.endm
ii_moveplda_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.l \1,d0
move.b d0,6(a1)
lsr.l #8,d0
move.b d0,4(a1)
lsr.l #8,d0
move.b d0,2(a1)
lsr.l #8,d0
move.b d0,(a1)
ii_end
.endm

661
headers/ii_op.h Normal file
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@@ -0,0 +1,661 @@
/*****************************************************************************************/
// opertionen
/*****************************************************************************************/
ii_lset_op:.macro
//byt
ii_lset_opea \1,0 // dx,ax
ii_lset_opea \1,1 // (ax), (ax)+
ii_lset_opea \1,2 // -(ax),d16(ax)
ii_lset_opeag \1,3 // d8(ax,dy)
lea table+0x\1\238*4,a0
move.l #ii_0x\138,(a0)+ // xxx.w
move.l #ii_0x\139,(a0)+ // xxx.l
//word
ii_lset_opea \1,4 // dx,ax
ii_lset_opea \1,5 // (ax), (ax)+
ii_lset_opea \1,6 // -(ax),d16(ax)
ii_lset_opeag \1,7 // d8(ax,dy)
lea table+0x\178*4,a0
move.l #ii_0x\178,(a0)+ // xxx.w
move.l #ii_0x\179,(a0)+ // xxx.l
//long
ii_lset_opea \1,8 // dx,ax
ii_lset_opea \1,9 // (ax), (ax)+
ii_lset_opea \1,a // -(ax),d16(ax)
ii_lset_opeag \1,b // d8(ax,dy)
lea table+0x\1b8*4,a0
move.l #ii_0x\1b8,(a0)+ // xxx.w
move.l #ii_0x\1b9,(a0)+ // xxx.l
.endm
ii_lset_opeag:.macro // 0x1120-0x1127
lea table+0x\1\20*4,a0
move.l #ii_0x\1\20,(a0)+
move.l #ii_0x\1\21,(a0)+
move.l #ii_0x\1\22,(a0)+
move.l #ii_0x\1\23,(a0)+
move.l #ii_0x\1\24,(a0)+
move.l #ii_0x\1\25,(a0)+
move.l #ii_0x\1\26,(a0)+
move.l #ii_0x\1\27,(a0)+
.endm;
ii_lset_opeau:.macro // 0x1128-0x112f
lea table+0x\1\28*4,a0
move.l #ii_0x\1\28,(a0)+
move.l #ii_0x\1\29,(a0)+
move.l #ii_0x\1\2a,(a0)+
move.l #ii_0x\1\2b,(a0)+
move.l #ii_0x\1\2c,(a0)+
move.l #ii_0x\1\2d,(a0)+
move.l #ii_0x\1\2e,(a0)+
move.l #ii_0x\1\2f,(a0)+
.endm;
ii_lset_opea:.macro
ii_lset_opeag \1,\2
ii_lset_opeau \1,\2
.endm
/******************************************************/
ii_op:.macro // 1=code 2=operation 3 = normal oder immediat/quick
// byt
opdx \1,\2,b,0,\3 // dx,ax
opia \1,\2,b,1,\3 // (ax),(ax)+
opdia \1,\2,b,2,\3 // -(ax),d16(ax)
opd8a \1,\2,b,3,\3 // d8(ax),xxx
// word
opdx \1,\2,w,4,\3 // dx,ax
opia \1,\2,w,5,\3 // (ax),(ax)+
opdia \1,\2,w,6,\3 // -(ax),d16(ax)
opd8a \1,\2,w,7,\3 // d8(ax),xxx
// long
opdx \1,\2,l,8,\3 // dx,ax
opia \1,\2,l,9,\3 // (ax),(ax)+
opdia \1,\2,l,a,\3 // -(ax),d16(ax)
opd8a \1,\2,l,b,\3 // d8(ax),xxx
.endm
/******************************************************/
// byt word long
/******************************************************/
opdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
.ifc \3,b
op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3
.else
op\5smd \2,d0_off(a7),d0_off(a7),\3
.endif
.endif
ii_0x\1\41:
.ifc \3,b
op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3
.else
op\5smd \2,d1_off(a7),d1_off(a7),\3
.endif
.endif
ii_0x\1\42:
op\5smd \2,d2,d2,\3
ii_0x\1\43:
op\5smd \2,d3,d3,\3
ii_0x\1\44:
op\5smd \2,d4,d4,\3
ii_0x\1\45:
op\5smd \2,d5,d5,\3
ii_0x\1\46:
op\5smd \2,d6,d6,\3
ii_0x\1\47:
op\5smd \2,d7,d7,\3
//ax
ii_0x\1\48:
opa\5smd \2,a0_off(a7),a0_off(a7),\3
ii_0x\1\49:
opa\5smd \2,a1_off(a7),a1_off(a7),\3
ii_0x\1\4a:
opa\5smd \2,a2,a2,\3
ii_0x\1\4b:
opa\5smd \2,a3,a3,\3
ii_0x\1\4c:
opa\5smd \2,a4,a4,\3
ii_0x\1\4d:
opa\5smd \2,a5,a5,\3
ii_0x\1\4e:
opa\5smd \2,a6,a6,\3
ii_0x\1\4f:
opa\5smd \2,usp,usp,\3
.endm;
//-----------------------------------------------
opia: .macro // (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
//(ax)
ii_0x\1\40:
op\5sia \2,a0_off(a7),(a1),(a1),\3
ii_0x\1\41:
op\5sia \2,a1_off(a7),(a1),(a1),\3
ii_0x\1\42:
op\5smd \2,(a2),(a2),\3
ii_0x\1\43:
op\5smd \2,(a3),(a3),\3
ii_0x\1\44:
op\5smd \2,(a4),(a4),\3
ii_0x\1\45:
op\5smd \2,(a5),(a5),\3
ii_0x\1\46:
op\5smd \2,(a6),(a6),\3
ii_0x\1\47:
op\5sia \2,usp,(a1),(a1),\3
//(ax)+
ii_0x\1\48:
op\5sia \2,a0_off(a7),(a1),(a1)+,\3
ii_0x\1\49:
op\5sia \2,a1_off(a7),(a1),(a1)+,\3
ii_0x\1\4a:
op\5smd \2,(a2),(a2)+,\3
ii_0x\1\4b:
op\5smd \2,(a3),(a3)+,\3
ii_0x\1\4c:
op\5smd \2,(a4),(a4)+,\3
ii_0x\1\4d:
op\5smd \2,(a5),(a5)+,\3
ii_0x\1\4e:
op\5smd \2,(a6),(a6)+,\3
ii_0x\1\4f:
op\5sia \2,usp,(a1),(a1)+,\3
.endm;
//-----------------------------------------------
opdia: .macro // -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
op\5sia \2,a0_off(a7),-(a1),(a1),\3
ii_0x\1\41:
op\5sia \2,a1_off(a7),-(a1),(a1),\3
ii_0x\1\42:
op\5smd \2,-(a2),(a2),\3
ii_0x\1\43:
op\5smd \2,-(a3),(a3),\3
ii_0x\1\44:
op\5smd \2,-(a4),(a4),\3
ii_0x\1\45:
op\5smd \2,-(a5),(a5),\3
ii_0x\1\46:
op\5smd \2,-(a6),(a6),\3
ii_0x\1\47:
op\5sia \2,usp,-(a1),(a1),\3
ii_0x\1\48:
op\5sd16a \2,a0_off(a7),\3
ii_0x\1\49:
op\5sd16a \2,a1_off(a7),\3
ii_0x\1\4a:
op\5sd16a \2,a2,\3
ii_0x\1\4b:
op\5sd16a \2,a3,\3
ii_0x\1\4c:
op\5sd16a \2,a4,\3
ii_0x\1\4d:
op\5sd16a \2,a5,\3
ii_0x\1\4e:
op\5sd16a \2,a6,\3
ii_0x\1\4f:
op\5sd16a \2,usp,\3
.endm;
//-----------------------------------------------
opd8a: .macro // d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
op\5sd8a \2,a0_off(a7),\3
ii_0x\1\41:
op\5sd8a \2,a1_off(a7),\3
ii_0x\1\42:
op\5sd8a \2,a2,\3
ii_0x\1\43:
op\5sd8a \2,a3,\3
ii_0x\1\44:
op\5sd8a \2,a4,\3
ii_0x\1\45:
op\5sd8a \2,a5,\3
ii_0x\1\46:
op\5sd8a \2,a6,\3
ii_0x\1\47:
op\5sd8a \2,usp,\3
ii_0x\1\48:
op\5sxx \2,\3,w
ii_0x\1\49:
op\5sxx \2,\3,l
.endm;
//-----------------------------------------------
opnsmd:.macro // direct dx: 1=operation 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\4 d1,\3
ii_end
.endm;
opansmd:.macro // direct ax: 1=operation 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 d1
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
ii_end
.endm;
opnsia:.macro // indirect: 1=operation 2=adress register 3= src 4=dest 5=size
#ifdef halten_op
halt
#endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\5 d1,\4
ii_end
.endm;
opnsd16a:.macro // indirect: 1=operation 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opnsd8a:.macro // indirect: 1=operation 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opnsxx:.macro // indirect: 1=operation 2=size 3=size adresse
#ifdef halten_op
halt
#endif
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
move.\3 (a0)+,a1
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\2 d1,(a1)
ii_end
.endm;
//*******************************************************************************3
opismd:.macro // immediate dx: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\4 d1,\3
.endif
ii_end
.endm;
opaismd:.macro // immediate ax: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 d0,d1
.ifnc \1,cmp.l
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
.endif
ii_end
.endm;
opisia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
#ifdef halten_op
halt
#endif
.ifc \5,l
move.l (a0)+,d0
.else
.ifc \5,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\5 d1,\4
.endif
ii_end
.endm;
opisd16a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
.ifc \3,l
move.l (a0)+,d0
.else
.ifc \3,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\3 d1,(a1)
.endif
ii_end
.endm;
opisd8a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
.ifc \3,l
move.l (a0)+,d0
.else
.ifc \3,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l d0,_d0_save
move.l \2,a1
jsr ewf
move.l _d0_save,d0
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\3 d1,(a1)
.endif
ii_end
.endm;
opisxx:.macro // immediate: 1=opieration 2=size 3=size adresse
.ifc \2,l
move.l (a0)+,d0
.else
.ifc \2,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.\3 (a0)+,a1
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\2 d1,(a1)
.endif
ii_end
.endm;
//*******************************************************************************3
opqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\4 d1,\3
ii_end
.endm;
opaqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 ,d1
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
ii_end
.endm;
opqsia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
#ifdef halten_op
halt
#endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\5 d1,\4
ii_end
.endm;
opqsd16a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opqsd8a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l d0,_d0_save
move.l \2,a1
jsr ewf
move.l _d0_save,d0
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opqsxx:.macro // quick: 1=opieration 2=size 3=size adresse
#ifdef halten_op
halt
#endif
move.\3 (a0)+,a1
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\2 d1,(a1)
ii_end
.endm;

263
headers/ii_opc.h Normal file
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@@ -0,0 +1,263 @@
/*****************************************************************************************/
// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax
// zusammen mit op.h
/*****************************************************************************************/
ii_lset_opc:.macro
ii_lset_opeag \1,c // dx,ax
ii_lset_opea \1,d // (ax), (ax)+
ii_lset_opea \1,e // -(ax),d16(ax)
ii_lset_opeag \1,f // d8(ax,dy)
lea table+0x\1b8*4,a0
move.l #ii_0x\1b8,(a0)+ // xxx.w
move.l #ii_0x\1b9,(a0)+ // xxx.l
.endm
/******************************************************/
ii_opc:.macro // 1=code 2=operation 3 = normal oder immediat
opcdx \1,\2,l,c,\3 // dx,ax
opia \1,\2,l,d,\3 // (ax),(ax)+
opdia \1,\2,l,e,\3 // -(ax),d16(ax)
opd8a \1,\2,l,f,\3 // d8(ax),xxx
.endm
//*******************************************************************************3
/******************************************************/
// byt word long
/******************************************************/
opcdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
#ifdef halten_opc
halt
#endif
.ifc \3,b
op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3
.else
op\5smd \2,d0_off(a7),d0_off(a7),\3
.endif
.endif
ii_0x\1\41:
.ifc \3,b
op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3
.else
op\5smd \2,d1_off(a7),d1_off(a7),\3
.endif
.endif
ii_0x\1\42:
op\5smd \2,d2,d2,\3
ii_0x\1\43:
op\5smd \2,d3,d3,\3
ii_0x\1\44:
op\5smd \2,d4,d4,\3
ii_0x\1\45:
op\5smd \2,d5,d5,\3
ii_0x\1\46:
op\5smd \2,d6,d6,\3
ii_0x\1\47:
op\5smd \2,d7,d7,\3
.endm
//-----------------------------------------------------
opcsmd:.macro // dx: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\4 d1,\3
ii_end
.endm;
opacsmd:.macro // ax: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 d1
set_cc0
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
ii_end
.endm;
opcsia:.macro // (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\5 d1,\4
ii_end
.endm;
opcsd16a:.macro // d16(ax): 1=opieration 2=adress register 3=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opcsd8a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l d0,_d0_save
move.l \2,a1
jsr ewf
move.l _d0_save,d0
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opcsxx:.macro // indirect: 1=opieration 2=size 3=size adresse
#ifdef halten_opc
halt
#endif
.ifc \2,l
move.l (a0)+,d0
.else
.ifc \2,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.\3 (a0)+,a1
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\2 d1,(a1)
ii_end
.endm;

442
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//--------------------------------------------------------------------
// or
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// or.b #im,dx
//--------------------------------------------------------------------
orbir_macro:.macro
#ifdef halten_or
halt
#endif
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
or.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea,dx
//--------------------------------------------------------------------
ordd:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea(l)->dy(w),dx z.B. f<>r USP
//--------------------------------------------------------------------
orddd:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or (ea)->dy,dx
//--------------------------------------------------------------------
ordda:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea->ay,(ay)+,dx
//--------------------------------------------------------------------
orddai:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea->ay,-(ay),dx
//--------------------------------------------------------------------
orddad:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d16(ay),dx
//--------------------------------------------------------------------
ord16ad:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d8(ay,dy),dx
//--------------------------------------------------------------------
ord8ad:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or xxx.w,dx
//--------------------------------------------------------------------
orxwd:.macro
#ifdef halten_or
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or xxx.l,dx
//--------------------------------------------------------------------
orxld:.macro
#ifdef halten_or
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d16(pc),dx
//--------------------------------------------------------------------
ord16pcd:.macro
halt
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d8(pc,dy),dx
//--------------------------------------------------------------------
ord8pcd:.macro
#ifdef halten_or
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// or dy,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // or (ea)->dy,dx
//--------------------------------------------------------------------
oreda:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,(ay)+
//--------------------------------------------------------------------
oredai:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,(ay)+
//--------------------------------------------------------------------
oredaid:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,-(ay)
//--------------------------------------------------------------------
oredad:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,-(ay)
//--------------------------------------------------------------------
oredadd:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,d16(ay)
//--------------------------------------------------------------------
ore16ad:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or.w dx,d8(ay,dy)
//--------------------------------------------------------------------
ore8ad:.macro
#ifdef halten_or
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,xxx.w
//--------------------------------------------------------------------
orxwe:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,xxx.l
//--------------------------------------------------------------------
orxle:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // ora.w ea,ax
//--------------------------------------------------------------------
oraw:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// or.w ea,usp
//--------------------------------------------------------------------
orawa7:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w usp?,ax
//--------------------------------------------------------------------
orawu:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w usp?,usp
//--------------------------------------------------------------------
orawua7:.macro
orawu \1,\2
.endm;
//--------------------------------------------------------------------
// // ora.w d16(ay),ax
//--------------------------------------------------------------------
orawd16a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w d8(ay,dy),ax
//--------------------------------------------------------------------
orawd8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w xxx.w,ax
//--------------------------------------------------------------------
orawxwax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w xxx.l,ax
//--------------------------------------------------------------------
orawxlax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w d16(pc),ax
//--------------------------------------------------------------------
orawd16pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w d8(pc,dy),ax
//--------------------------------------------------------------------
orawd8pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w #im,ax
//--------------------------------------------------------------------
orawim:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.l d8(ay,dy),ax
//--------------------------------------------------------------------
orald8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.l d8(pc,dy),ax
//--------------------------------------------------------------------
orald8pcax:.macro
jmp ii_error
.endm;
//*****************************************************************************************
// spezial addx subx etc.
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // addx dy,dx
//--------------------------------------------------------------------
ordx:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // addx -(ay),-(ax)
//--------------------------------------------------------------------
ordax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------

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//--------------------------------------------------------------------
// pea
//--------------------------------------------------------------------
.text
ii_pea_lset:.macro
ii_lset_opeag 48,7
ii_lset 0x487b
.endm
//---------------------------------------------------------------------------------------------
ii_pea_func:.macro
ii_0x4870:
#ifdef halten_pea
halt
#endif
move.l a0_off(a7),a1
pea_macro
ii_0x4871:
#ifdef halten_pea
halt
#endif
move.l a1_off(a7),a1
pea_macro
ii_0x4872:
#ifdef halten_pea
halt
#endif
move.l a2,a1
pea_macro
ii_0x4873:
#ifdef halten_pea
halt
#endif
move.l a3,a1
pea_macro
ii_0x4874:
#ifdef halten_pea
halt
#endif
move.l a4,a1
pea_macro
ii_0x4875:
#ifdef halten_pea
halt
#endif
move.l a5,a1
pea_macro
ii_0x4876:
#ifdef halten_pea
halt
#endif
move.l a6,a1
pea_macro
ii_0x4877:
#ifdef halten_pea
halt
#endif
move.l usp,a1
pea_macro
ii_0x487b:
#ifdef halten_pea
halt
#endif
move.l a0,a1
pea_macro
.endm
//---------------------------------------------------------------------------------------------
pea_macro:.macro
jsr ewf
move.l (a1),d0
move.l usp,a1
move.l d0,-(a1)
move.l a1,usp
ii_end
.endm

247
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/*****************************************************************************************/
// opertionen
/*****************************************************************************************/
ii_lset_shd:.macro
ii_lset_shdx e0 //r d0
ii_lset_shdx e2 //r d1
ii_lset_shdx e4 //r d2
ii_lset_shdx e6 //r d3
ii_lset_shdx e8 //r d4
ii_lset_shdx ea //r d5
ii_lset_shdx ec //r d6
ii_lset_shdx ee //r d7
ii_lset_shdx e1 //l d0
ii_lset_shdx e3 //l d1
ii_lset_shdx e4 //l d2
ii_lset_shdx e5 //l d3
ii_lset_shdx e9 //l d4
ii_lset_shdx eb //l d5
ii_lset_shdx ed //l d6
ii_lset_shdx ef //l d7
.endm
ii_lset_shdx:.macro
//byt
ii_lset_opea \1,0 // as,ls #im,dx
ii_lset_opea \1,1 // rox,ro #im,dx
ii_lset_opea \1,2 // as,ls dy,dx
ii_lset_opea \1,3 // rox,ro dy,dx
//word
ii_lset_opea \1,4 // as,ls #im,dx
ii_lset_opea \1,5 // rox,ro #im,dx
ii_lset_opea \1,6 // as,ls dy,dx
ii_lset_opea \1,7 // rox,ro dy,dx
//long
// ii_lset_opea \1,8 // as,ls #im,dx -> vorhanden
ii_lset_opea \1,9 // rox,ro #im,dx
// ii_lset_opea \1,a // as,ls dy,dx -> vorhanden
ii_lset_opea \1,b // rox,ro dy,dx
.endm
/******************************************************/
ii_shd:.macro // 1=code 2=operation 3 = normal, direct oder immediat
// byt
opdx \1,\2,b,0,\3 // dx
// word
opdx \1,\2,w,4,\3 // dx
// long
opdx \1,\2,l,8,\3 // dx
.endm
/******************************************************/
// byt word long routinen
/******************************************************/
sh_asr: .macro // asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
mvs.\4 \2,d1
sh_shal \1,\2,\3,\4
.endm
sh_lsr: .macro // asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
mvz.\4 \2,d1
sh_shal \1,\2,\3,\4
.endm
sh_shal:.macro
move.w \3,d0
\1.l d0,d1
set_cc0
move.\4 d1,\2
.endm
sh_all: .macro // asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
mvz.\4 \2,d1
.ifc \4,b
byterev.l d1
.else
swap.w d1
.endif
sh_asr \1,\2,\3,\4
.endm
sh_ror: .macro // ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
move.\4 \2,d1 /
move.w \3,d0
.ifc \4,b
lsl.l #8,d1
move.b \2,d1
and.l #0x7,d0
lsr.l d0,d1
.else
.ifc \4,w
swap.w d1
move.w \2,d1
and.l #0xf,d0
lsr.l d0,d1
.else
and.l #0x1f,d0
lsr.l d0,d1
move.l d1,a1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsl.l d0,d1
add.l a1,d1
.endif
.endif
move.\4 d1,\2
move.w ccr,d0
and.l #1,d1 // ist auch carry bit
or.l d1,d0
move.b d0,ccr_off(a7)
.endm
sh_rol: .macro // rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
move.\4 \2,d1
move.w \3,d0
.ifc \4,b
lsl.l #8,d1
move.b \2,d1
and.l #0x7,d0
lsl.l d0,d1
lsr.l #8,d1
moveq #7,d0
.else
.ifc \4,w
swap.w d1
move.w \2,d1
and.l #0xf,d0
lsr.l d0,d1
swap.w d1
moveq #15,d0
.else
and.l #0x1f,d0
lsl.l d0,d1
move.l d1,a1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsr.l d0,d1
add.l a1,d1
moveq #31,d0
.endif
.endif
move.\4 d1,\2
lsr.l d0,d1 // carry bit schieben
move.w ccr,d0
and.l #1,d1
or.l d1,d0
move.b d0,ccr_off(a7)
.endm
sh_roxr: .macro // roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
clr.l d0
addx.l d0,d0
ifc \4,b
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
move.b \2,d1
move.w \3,d0
and.l #0x7,d0
lsr.l d0,d1
set_cc0
else
.ifc \4,w
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
lsl.l #8,d1
move.w \2,d1
move.w \3,d0
and.l #0xf,d0
lsr.l d0,d1
set_cc0
.else
bitrev.l d0
move.l \2,d1
lsr.l #1,d1
add.l d0,d1
move.w \3,d0
subq.l #1,d0
and.l #0x1f,d0
lsr.l d0,d1
move.l d1,a1
set_cc1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsl.l d0,d1
add.l a1,d1
.endif
.endif
move.\4 d1,\2
.endm
sh_roxl: .macro // roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
clr.l d0
addx.l d0,d0
ifc \4,b
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
move.b \2,d1
lsl.l #8,d1
lsl.l #7,d1
move.w \3,d0
and.l #0x7,d0
lsl.l d0,d1
set_cc0
byterev.l d1
else
.ifc \4,w
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
lsl.l #7,d1
mvz.w \2,d0
lsr.l #1,d0
add.l d0,d1
move.w \3,d0
and.l #0xf,d0
lsl.l d0,d1
set_cc0
swap.w d1
.else
move.l \2,d1
lsl.l #1,d1
add.l d0,d1
move.w \3,d0
subq.l #1,d0
and.l #0x1f,d0
lsl.l d0,d1
move.l d1,a1
set_cc1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsr.l d0,d1
add.l a1,d1
.endif
.endif
move.\4 d1,\2
.endm

687
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/*****************************************************************************************/
// opertionen
/*****************************************************************************************/
ii_shift_lset:.macro
/******************************************************/
// byt
/******************************************************/
// asx.b #,dx
ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,01
ii_lset_dx \1,02
ii_lset_dx \1,03
ii_lset_dx \1,04
ii_lset_dx \1,05
ii_lset_dx \1,06
ii_lset_dx \1,07
// lsx.b #,dx
ii_lset_dxu \1,08
ii_lset_dxu \1,09
ii_lset_dxu \1,0a
ii_lset_dxu \1,0b
ii_lset_dxu \1,0c
ii_lset_dxu \1,0d
ii_lset_dxu \1,0e
ii_lset_dxu \1,0f
// roxx.b #,dx
ii_lset_dx \1,10
ii_lset_dx \1,11
ii_lset_dx \1,12
ii_lset_dx \1,13
ii_lset_dx \1,14
ii_lset_dx \1,15
ii_lset_dx \1,16
ii_lset_dx \1,17
// rox.b #,dx
ii_lset_dx \1,18
ii_lset_dx \1,19
ii_lset_dx \1,1a
ii_lset_dx \1,1b
ii_lset_dx \1,1c
ii_lset_dx \1,1d
ii_lset_dx \1,1e
ii_lset_dx \1,1f
// asx.b dy,dx
ii_lset_dx \1,20
ii_lset_dx \1,21
ii_lset_dx \1,22
ii_lset_dx \1,23
ii_lset_dx \1,24
ii_lset_dx \1,25
ii_lset_dx \1,26
ii_lset_dx \1,27
// lsx.b dy,dx
ii_lset_dx \1,28
ii_lset_dx \1,29
ii_lset_dx \1,2a
ii_lset_dx \1,2b
ii_lset_dx \1,2c
ii_lset_dx \1,2d
ii_lset_dx \1,2e
ii_lset_dx \1,2f
// roxx.dy,dx
ii_lset_dx \1,30
ii_lset_dx \1,31
ii_lset_dx \1,32
ii_lset_dx \1,33
ii_lset_dx \1,34
ii_lset_dx \1,35
ii_lset_dx \1,36
ii_lset_dx \1,37
// rox.b dy,dx
ii_lset_dx \1,38
ii_lset_dx \1,39
ii_lset_dx \1,3a
ii_lset_dx \1,3b
ii_lset_dx \1,3c
ii_lset_dx \1,3d
ii_lset_dx \1,3e
ii_lset_dx \1,3f
/******************************************************/
// word
/******************************************************/
// asx.w #x,dx
ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,41
ii_lset_dx \1,42
ii_lset_dx \1,43
ii_lset_dx \1,44
ii_lset_dx \1,45
ii_lset_dx \1,46
ii_lset_dx \1,47
// lsx.w #,dx
ii_lset_dx \1,48
ii_lset_dx \1,49
ii_lset_dx \1,4a
ii_lset_dx \1,4b
ii_lset_dx \1,4c
ii_lset_dx \1,4d
ii_lset_dx \1,4e
ii_lset_dx \1,4f
// roxx.w #,dx
ii_lset_dx \1,50
ii_lset_dx \1,51
ii_lset_dx \1,52
ii_lset_dx \1,53
ii_lset_dx \1,54
ii_lset_dx \1,55
ii_lset_dx \1,56
ii_lset_dx \1,57
// rox.w #xdx
ii_lset_dx \1,58
ii_lset_dx \1,59
ii_lset_dx \1,5a
ii_lset_dx \1,5b
ii_lset_dx \1,5c
ii_lset_dx \1,5d
ii_lset_dx \1,5e
ii_lset_dx \1,5f
// asx.w dy,dx
ii_lset_dx \1,60
ii_lset_dx \1,61
ii_lset_dx \1,62
ii_lset_dx \1,63
ii_lset_dx \1,64
ii_lset_dx \1,65
ii_lset_dx \1,66
ii_lset_dx \1,67
// lsx.w dy,dx
ii_lset_dx \1,68
ii_lset_dx \1,69
ii_lset_dx \1,6a
ii_lset_dx \1,6b
ii_lset_dx \1,6c
ii_lset_dx \1,6d
ii_lset_dx \1,6e
ii_lset_dx \1,6f
// roxx.w dy,dx
ii_lset_dx \1,70
ii_lset_dx \1,71
ii_lset_dx \1,72
ii_lset_dx \1,73
ii_lset_dx \1,74
ii_lset_dx \1,75
ii_lset_dx \1,76
ii_lset_dx \1,77
// rox.w dy,dx
ii_lset_dx \1,78
ii_lset_dx \1,79
ii_lset_dx \1,7a
ii_lset_dx \1,7b
ii_lset_dx \1,7c
ii_lset_dx \1,7d
ii_lset_dx \1,7e
ii_lset_dx \1,7f
/******************************************************/
// long
/******************************************************/
// roxx.l #,dx
ii_lset_dx \1,90
ii_lset_dx \1,91
ii_lset_dx \1,92
ii_lset_dx \1,93
ii_lset_dx \1,94
ii_lset_dx \1,95
ii_lset_dx \1,96
ii_lset_dx \1,97
// rox.l #xdx
ii_lset_dx \1,98
ii_lset_dx \1,99
ii_lset_dx \1,9a
ii_lset_dx \1,9b
ii_lset_dx \1,9c
ii_lset_dx \1,9d
ii_lset_dx \1,9e
ii_lset_dx \1,9f
// roxx.l dy,dx
ii_lset_dx \1,b0
ii_lset_dx \1,b1
ii_lset_dx \1,b2
ii_lset_dx \1,b3
ii_lset_dx \1,b4
ii_lset_dx \1,b5
ii_lset_dx \1,b6
ii_lset_dx \1,b7
// rox.l dy,dx
ii_lset_dx \1,b8
ii_lset_dx \1,b9
ii_lset_dx \1,ba
ii_lset_dx \1,bb
ii_lset_dx \1,bc
ii_lset_dx \1,bd
ii_lset_dx \1,be
ii_lset_dx \1,bf
//--------------------------------------------------------------------
// asr.w ea
ii_lset_opea \10,d // (ax), (ax)+
ii_lset_opea \10,e // -(ax),d16(ax)
ii_lset_opeag \10,f // d8(ax,dy)
lea table+0x\10\2f8*4,a0
move.l #ii_0x\10f8,(a0)+ // xxx.w
move.l #ii_0x\10f9,(a0)+ // xxx.l
// asl.w ea
ii_lset_opea \11,d // (ax), (ax)+
ii_lset_opea \11,e // -(ax),d16(ax)
ii_lset_opeag \11,f // d8(ax,dy)
lea table+0x\11\2f8*4,a0
move.l #ii_0x\11f8,(a0)+ // xxx.w
move.l #ii_0x\11f9,(a0)+ // xxx.l
// lsr.w ea
ii_lset_opea \12,d // (ax), (ax)+
ii_lset_opea \12,e // -(ax),d16(ax)
ii_lset_opeag \12,f // d8(ax,dy)
lea table+0x\12\2f8*4,a0
move.l #ii_0x\12f8,(a0)+ // xxx.w
move.l #ii_0x\12f9,(a0)+ // xxx.l
// lsr.w ea
ii_lset_opea \13,d // (ax), (ax)+
ii_lset_opea \13,e // -(ax),d16(ax)
ii_lset_opeag \13,f // d8(ax,dy)
lea table+0x\13\2f8*4,a0
move.l #ii_0x\13f8,(a0)+ // xxx.w
move.l #ii_0x\13f9,(a0)+ // xxx.l
// roxr.w ea
ii_lset_opea \14,d // (ax), (ax)+
ii_lset_opea \14,e // -(ax),d16(ax)
ii_lset_opeag \14,f // d8(ax,dy)
lea table+0x\14\2f8*4,a0
move.l #ii_0x\14f8,(a0)+ // xxx.w
move.l #ii_0x\14f9,(a0)+ // xxx.l
// roxl.w ea
ii_lset_opea \15,e // (ax), (ax)+
ii_lset_opea \15,e // -(ax),d16(ax)
ii_lset_opeag \15,f // d8(ax,dy)
lea table+0x\15\2f8*4,a0
move.l #ii_0x\15f8,(a0)+ // xxx.w
move.l #ii_0x\15f9,(a0)+ // xxx.l
// ror.w ea
ii_lset_opea \16,d // (ax), (ax)+
ii_lset_opea \16,e // -(ax),d16(ax)
ii_lset_opeag \16,f // d8(ax,dy)
lea table+0x\16\2f8*4,a0
move.l #ii_0x\16f8,(a0)+ // xxx.w
move.l #ii_0x\16f9,(a0)+ // xxx.l
// rol.w ea
ii_lset_opea \17,d // (ax), (ax)+
ii_lset_opea \17,e // -(ax),d16(ax)
ii_lset_opeag \17,f // d8(ax,dy)
lea table+0x\17\2f8*4,a0
move.l #ii_0x\17f8,(a0)+ // xxx.w
move.l #ii_0x\17f9,(a0)+ // xxx.l
// ende
.endm;
/******************************************************/
ii_shift_op:.macro // 1=code
//byt-------------------------------
//asx.b #x,dx
ii_shift_op2agb 0,as,a
//lsx.b #x,dx
ii_shift_op2aub 0,ls,a
//roxx.b #x,dx
ii_shift_op2agb 1,rox,a
//rox.b #x,dx
ii_shift_op2aub 1,ro,a
//asx.b dy,dx
ii_shift_op2agb 2,as,b
//lsx.b dy,dx
ii_shift_op2aub 2,ls,b
//roxx.b dy,dx
ii_shift_op2agb 3,rox,b
//rox.b dy,dx
ii_shift_op2aub 3,ro,b
// word ---------------------------------------
//asx.w #x,dx
ii_shift_op2agw 4,as,a
//lsx.w #x,dx
ii_shift_op2auw 4,ls,a
//roxx.w #x,dx
ii_shift_op2agw 5,rox,a
//rox.w #x,dx
ii_shift_op2auw 5,ro,a
//asx.w dy,dx
ii_shift_op2agw 6,as,b
//lsx.w dy,dx
ii_shift_op2auw 6,ls,b
//roxx.w dy,dx
ii_shift_op2agw 7,rox,b
//rox.w dy,dx
ii_shift_op2auw 7,ro,b
// long ---------------------------------------
//roxx.l #x,dx
ii_shift_op2agw 9,rox,a
//rox.l #x,dx
ii_shift_op2auw 9,ro,a
//roxx.l dy,dx
ii_shift_op2agw b,rox,b
//rox.l dy,dx
ii_shift_op2auw b,ro,b
// ea ---------------------------------------
//asr.w #1,ea
ii_shift_op2ea 0,asr
//asl.w #1,ea
ii_shift_op2ea 1,asl
//lsr.w #1,ea
ii_shift_op2ea 2,lsr,
//lsl.w #1,ea
ii_shift_op2ea 3,lsl
//roxr.w #1,ea
ii_shift_op2ea 4,roxr
//roxl.w #1,ea
ii_shift_op2ea 5,roxl
//ror.w #1,ea
ii_shift_op2ea 6,ror
//rol.w #1,ea
ii_shift_op2ea 7,rol
.endm
//byt ============================================
ii_shift_op2agb:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b)
ii_shift_op1\3b \1,0,\2,d0_off+3(a7)
ii_shift_op1\3b \1,1,\2,d1_off+3(a7)
ii_shift_op1\3b \1,2,\2,d2
ii_shift_op1\3b \1,3,\2,d3
ii_shift_op1\3b \1,4,\2,d4
ii_shift_op1\3b \1,5,\2,d5
ii_shift_op1\3b \1,6,\2,d6
ii_shift_op1\3b \1,7,\2,d7
.endm
ii_shift_op2aub:.macro //byt: 1=code 2=operation
ii_shift_op1\3b \1,8,\2,d0_off+3(a7)
ii_shift_op1\3b \1,9,\2,d1_off+3(a7)
ii_shift_op1\3b \1,a,\2,d2
ii_shift_op1\3b \1,b,\2,d3
ii_shift_op1\3b \1,c,\2,d4
ii_shift_op1\3b \1,d,\2,d5
ii_shift_op1\3b \1,e,\2,d6
ii_shift_op1\3b \1,f,\2,d7
.endm
ii_shift_op1ab:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0 0\1\2,b,\3r,#8,\4
ii_shift_op0 2\1\2,b,\3r,#1,\4
ii_shift_op0 4\1\2,b,\3r,#2,\4
ii_shift_op0 6\1\2,b,\3r,#3,\4
ii_shift_op0 8\1\2,b,\3r,#4,\4
ii_shift_op0 a\1\2,b,\3r,#5,\4
ii_shift_op0 c\1\2,b,\3r,#6,\4
ii_shift_op0 e\1\2,b,\3r,#7,\4
ii_shift_op0 1\1\2,b,\3l,#8,\4
ii_shift_op0 3\1\2,b,\3l,#1,\4
ii_shift_op0 5\1\2,b,\3l,#2,\4
ii_shift_op0 7\1\2,b,\3l,#3,\4
ii_shift_op0 9\1\2,b,\3l,#4,\4
ii_shift_op0 b\1\2,b,\3l,#5,\4
ii_shift_op0 d\1\2,b,\3l,#6,\4
ii_shift_op0 f\1\2,b,\3l,#7,\4
.endm
ii_shift_op1bb:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0b 0\1\2,b,\3r,d0_off(a7),\4
ii_shift_op0b 2\1\2,b,\3r,d1_off(a7),\4
ii_shift_op0 4\1\2,b,\3r,d2,\4
ii_shift_op0 6\1\2,b,\3r,d3,\4
ii_shift_op0 8\1\2,b,\3r,d4,\4
ii_shift_op0 a\1\2,b,\3r,d5,\4
ii_shift_op0 c\1\2,b,\3r,d6,\4
ii_shift_op0 e\1\2,b,\3r,d7,\4
ii_shift_op0b 1\1\2,b,\3l,d0_off(a7),\4
ii_shift_op0b 3\1\2,b,\3l,d1_off(a7),\4
ii_shift_op0 5\1\2,b,\3l,d2,\4
ii_shift_op0 7\1\2,b,\3l,d3,\4
ii_shift_op0 9\1\2,b,\3l,d4,\4
ii_shift_op0 b\1\2,b,\3l,d5,\4
ii_shift_op0 d\1\2,b,\3l,d6,\4
ii_shift_op0 f\1\2,b,\3l,d7,\4
.endm
// word ---------------------------------------
ii_shift_op2agw:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b)
ii_shift_op1\3w \1,0,\2,d0_off+2(a7)
ii_shift_op1\3w \1,1,\2,d1_off+2(a7)
ii_shift_op1\3w \1,2,\2,d2
ii_shift_op1\3w \1,3,\2,d3
ii_shift_op1\3w \1,4,\2,d4
ii_shift_op1\3w \1,5,\2,d5
ii_shift_op1\3w \1,6,\2,d6
ii_shift_op1\3w \1,7,\2,d7
.endm
ii_shift_op2auw:.macro //byt: 1=code 2=operation
ii_shift_op1\3w \1,8,\2,d0_off+2(a7)
ii_shift_op1\3w \1,9,\2,d1_off+2(a7)
ii_shift_op1\3w \1,a,\2,d2
ii_shift_op1\3w \1,b,\2,d3
ii_shift_op1\3w \1,c,\2,d4
ii_shift_op1\3w \1,d,\2,d5
ii_shift_op1\3w \1,e,\2,d6
ii_shift_op1\3w \1,f,\2,d7
.endm
ii_shift_op1aw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0 0\1\2,w,\3r,#8,\4
ii_shift_op0 2\1\2,w,\3r,#1,\4
ii_shift_op0 4\1\2,w,\3r,#2,\4
ii_shift_op0 6\1\2,w,\3r,#3,\4
ii_shift_op0 8\1\2,w,\3r,#4,\4
ii_shift_op0 a\1\2,w,\3r,#5,\4
ii_shift_op0 c\1\2,w,\3r,#6,\4
ii_shift_op0 e\1\2,w,\3r,#7,\4
ii_shift_op0 1\1\2,w,\3l,#8,\4
ii_shift_op0 3\1\2,w,\3l,#1,\4
ii_shift_op0 5\1\2,w,\3l,#2,\4
ii_shift_op0 7\1\2,w,\3l,#3,\4
ii_shift_op0 9\1\2,w,\3l,#4,\4
ii_shift_op0 b\1\2,w,\3l,#5,\4
ii_shift_op0 d\1\2,w,\3l,#6,\4
ii_shift_op0 f\1\2,w,\3l,#7,\4
.endm
ii_shift_op1bw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0b 0\1\2,w,\3r,d0_off(a7),\4
ii_shift_op0b 2\1\2,w,\3r,d1_off(a7),\4
ii_shift_op0 4\1\2,w,\3r,d2,\4
ii_shift_op0 6\1\2,w,\3r,d3,\4
ii_shift_op0 8\1\2,w,\3r,d4,\4
ii_shift_op0 a\1\2,w,\3r,d5,\4
ii_shift_op0 c\1\2,w,\3r,d6,\4
ii_shift_op0 e\1\2,w,\3r,d7,\4
ii_shift_op0b 1\1\2,w,\3l,d0_off(a7),\4
ii_shift_op0b 3\1\2,w,\3l,d1_off(a7),\4
ii_shift_op0 5\1\2,w,\3l,d2,\4
ii_shift_op0 7\1\2,w,\3l,d3,\4
ii_shift_op0 9\1\2,w,\3l,d4,\4
ii_shift_op0 b\1\2,w,\3l,d5,\4
ii_shift_op0 d\1\2,w,\3l,d6,\4
ii_shift_op0 f\1\2,w,\3l,d7,\4
.endm
// long ---------------------------------------
ii_shift_op2agl:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b)
ii_shift_op1\3l \1,0,\2,d0_off(a7)
ii_shift_op1\3l \1,1,\2,d1_off(a7)
ii_shift_op1\3l \1,2,\2,d2
ii_shift_op1\3l \1,3,\2,d3
ii_shift_op1\3l \1,4,\2,d4
ii_shift_op1\3l \1,5,\2,d5
ii_shift_op1\3l \1,6,\2,d6
ii_shift_op1\3l \1,7,\2,d7
.endm
ii_shift_op2aul:.macro //byt: 1=code 2=operation
ii_shift_op1\3l \1,8,\2,d0_off(a7)
ii_shift_op1\3l \1,9,\2,d1_off(a7)
ii_shift_op1\3l \1,a,\2,d2
ii_shift_op1\3l \1,b,\2,d3
ii_shift_op1\3l \1,c,\2,d4
ii_shift_op1\3l \1,d,\2,d5
ii_shift_op1\3l \1,e,\2,d6
ii_shift_op1\3l \1,f,\2,d7
.endm
ii_shift_op1al:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0 0\1\2,l,\3r,#8,\4
ii_shift_op0 2\1\2,l,\3r,#1,\4
ii_shift_op0 4\1\2,l,\3r,#2,\4
ii_shift_op0 6\1\2,l,\3r,#3,\4
ii_shift_op0 8\1\2,l,\3r,#4,\4
ii_shift_op0 a\1\2,l,\3r,#5,\4
ii_shift_op0 c\1\2,l,\3r,#6,\4
ii_shift_op0 e\1\2,l,\3r,#7,\4
ii_shift_op0 1\1\2,l,\3l,#8,\4
ii_shift_op0 3\1\2,l,\3l,#1,\4
ii_shift_op0 5\1\2,l,\3l,#2,\4
ii_shift_op0 7\1\2,l,\3l,#3,\4
ii_shift_op0 9\1\2,l,\3l,#4,\4
ii_shift_op0 b\1\2,l,\3l,#5,\4
ii_shift_op0 d\1\2,l,\3l,#6,\4
ii_shift_op0 f\1\2,l,\3l,#7,\4
.endm
ii_shift_op1bl:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0b 0\1\2,l,\3r,d0_off(a7),\4
ii_shift_op0b 2\1\2,l,\3r,d1_off(a7),\4
ii_shift_op0 4\1\2,l,\3r,d2,\4
ii_shift_op0 6\1\2,l,\3r,d3,\4
ii_shift_op0 8\1\2,l,\3r,d4,\4
ii_shift_op0 a\1\2,l,\3r,d5,\4
ii_shift_op0 c\1\2,l,\3r,d6,\4
ii_shift_op0 e\1\2,l,\3r,d7,\4
ii_shift_op0b 1\1\2,l,\3l,d0_off(a7),\4
ii_shift_op0b 3\1\2,l,\3l,d1_off(a7),\4
ii_shift_op0 5\1\2,l,\3l,d2,\4
ii_shift_op0 7\1\2,l,\3l,d3,\4
ii_shift_op0 9\1\2,l,\3l,d4,\4
ii_shift_op0 b\1\2,l,\3l,d5,\4
ii_shift_op0 d\1\2,l,\3l,d6,\4
ii_shift_op0 f\1\2,l,\3l,d7,\4
.endm
// .word ea ============================================
ii_shift_op2ea:.macro //1=code 2.ziffer 2=shiftart
// (a0) bis (a7) ----------------------------
ii_0xe\1d0:
move.l a0_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1d1:
move.l a1_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1d2:
ii_shift_typ w,\2,#1,(a2),(a2).
ii_0xe\1d3:
ii_shift_typ w,\2,#1,(a3),(a3).
ii_0xe\1d4:
ii_shift_typ w,\2,#1,(a4),(a4).
ii_0xe\1d5:
ii_shift_typ w,\2,#1,(a5),(a5).
ii_0xe\1d6:
ii_shift_typ w,\2,#1,(a6),(a6).
ii_0xe\1d7:
move.l usp,a1
ii_shift_typ w,\2,#1,(a1),(a1).
// (a0)+ bis (a7)+ -----------------------------
ii_0xe\1d8:
move.l a0_off(a7),a1
addq.l #2,a0_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1d9:
move.l a1_off(a7),a1
addq.l #2,a0_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1da:
ii_shift_typ w,\2,#1,(a2),(a2)+.
ii_0xe\1db:
ii_shift_typ w,\2,#1,(a3),(a3)+
ii_0xe\1dc:
ii_shift_typ w,\2,#1,(a4),(a4)+
ii_0xe\1dd:
ii_shift_typ w,\2,#1,(a5),(a5)+
ii_0xe\1de:
ii_shift_typ w,\2,#1,(a6),(a6)+
ii_0xe\1df:
move.l usp,a1
addq.l #2,a1
move.l a1,usp
subq.l #2,a1
ii_shift_typ w,\2,#1,(a1),(a1).
// -(a0) bis -(a7) -----------------------------
ii_0xe\1e0:
move.l a0_off(a7),a1
subq.l #2,a1
move.l a1,a0_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1e1:
move.l a1_off(a7),a1
subq.l #2,a1
move.l a1,a1_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1e2:
ii_shift_typ w,\2,#1,-(a2),(a2).
ii_0xe\1e3:
ii_shift_typ w,\2,#1,-(a3),(a3)
ii_0xe\1e4:
ii_shift_typ w,\2,#1,-(a4),(a4)
ii_0xe\1e5:
ii_shift_typ w,\2,#1,-(a5),(a5)
ii_0xe\1e6:
ii_shift_typ w,\2,#1,-(a6),(a6)
ii_0xe\1e7:
move.l usp,a1
subq.l #2,a1
move.l a1,usp
ii_shift_typ w,\2,#1,(a1),(a1).
// d16(a0) bis d16(a7) -----------------------------
ii_0xe\1e8:
move.w (a0)+,a1
add.l a0_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1e9:
move.w (a0)+,a1
add.l a1_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1ea:
move.w (a0)+,a1
add.l a2,a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1eb:
move.w (a0)+,a1
add.l a3,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ec:
move.w (a0)+,a1
add.l a4,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ed:
move.w (a0)+,a1
add.l a5,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ee:
move.w (a0)+,a1
add.l a6,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ef:
mvs.w (a0)+,d0
move.l usp,a1
add.l d0,a1
ii_shift_typ w,\2,#1,(a1),(a1).
// d8(a0,dy) bis d8(a7,dy) -----------------------------
ii_0xe\1f0:
move.l a0_off(a0),a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f1:
move.l a1_off(a0),a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f2:
move.l a2,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f3:
move.l a3,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f4:
move.l a4,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f5:
move.l a5,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f6:
move.l a6,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f7:
move.l usp,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
// xxx.w xxx.l
ii_0xe\1f8:
move.w (a0)+,a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f9:
move.l (a0)+,a1
ii_shift_typ w,\2,#1,(a1),(a1).
.endm
//============================================================================
//subroutine
//------------------------------
ii_shift_op0:.macro // shift: 1=code 2=size 3=shift art 4=shift wert 5=ea
ii_0xe\1:
ii_shift_typ \2,\3,\4,\5,\5
.endm
ii_shift_op0b:.macro // shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea
ii_0xe\1:
move.l \4,d0
ii_shift_typ \2,\3,d0,\5,\5
.endm
ii_shift_typ:.macro //1=size 2=shift art 3=shift wert 4=source 5=dest
#ifdef halten
halt
#endif
.ifc asr,\2
mvs.\1 \4,d1
.else
mvz.\1 \4,d1
.endif
.ifc roxr,\2
nop
.else
.ifc roxl,\2
nop
.else
.ifc ror,\2
nop
.else
.ifc rol,\2
nop
.else
\2.l \3,d1
.endif
.endif
.endif
.endif
set_cc0
move.\1 d1,\5
ii_end
.endm

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//--------------------------------------------------------------------
// sub
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// sub.b #im,dx
//--------------------------------------------------------------------
subbir_macro:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
sub.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea,dx
//--------------------------------------------------------------------
subdd:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea(l)->dy(w),dx z.B. f<>r USP
//--------------------------------------------------------------------
subddd:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub (ea)->dy,dx
//--------------------------------------------------------------------
subdda:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea->ay,(ay)+,dx
//--------------------------------------------------------------------
subddai:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea->ay,-(ay),dx
//--------------------------------------------------------------------
subddad:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d16(ay),dx
//--------------------------------------------------------------------
subd16ad:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d8(ay,dy),dx
//--------------------------------------------------------------------
subd8ad:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub xxx.w,dx
//--------------------------------------------------------------------
subxwd:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub xxx.l,dx
//--------------------------------------------------------------------
subxld:.macro
#ifdef halten_sub
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d16(pc),dx
//--------------------------------------------------------------------
subd16pcd:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d8(pc,dy),dx
//--------------------------------------------------------------------
subd8pcd:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// sub dy,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // sub (ea)->dy,dx
//--------------------------------------------------------------------
subeda:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,(ay)+
//--------------------------------------------------------------------
subedai:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,(ay)+
//--------------------------------------------------------------------
subedaid:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,-(ay)
//--------------------------------------------------------------------
subedad:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,-(ay)
//--------------------------------------------------------------------
subedadd:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,d16(ay)
//--------------------------------------------------------------------
sube16ad:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,d8(ay,dy)
//--------------------------------------------------------------------
sube8ad:.macro
#ifdef halten_sub
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,xxx.w
//--------------------------------------------------------------------
subxwe:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,xxx.l
//--------------------------------------------------------------------
subxle:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
/******************************************************/
// adress register
/******************************************************/
//--------------------------------------------------------------------
// // suba.w ea,ax
//--------------------------------------------------------------------
subaw:.macro
#ifdef halten_sub
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
mvs.w \1,d0
suba.l d0,\2
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// sub.w ea,usp
//--------------------------------------------------------------------
subawa7:.macro
#ifdef halten_sub
halt
#endif
mvs.w \1,d0
move.l usp,a1
sub.l d0,a1
move.l a1,usp
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w usp?,ax
//--------------------------------------------------------------------
subawu:.macro
#ifdef halten_sub
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
move.l a7,_a7_save
move.l usp,a7
move.l \1,d0
suba.l d0,\2
move.l a7,usp
move.l _a7_save,a7
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// // suba.w usp?,usp
//--------------------------------------------------------------------
subawua7:.macro
subawu \1,\2
.endm;
//--------------------------------------------------------------------
// // suba.w d16(ay),ax
//--------------------------------------------------------------------
subawd16a:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
adda.l d0,a1
mvs.w (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w d8(ay,dy),ax
//--------------------------------------------------------------------
subawd8a:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w xxx.w,ax
//--------------------------------------------------------------------
subawxwax:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,a1
mvs.w (a1),d0
move.l \2,a1
suba.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w xxx.l,ax
//--------------------------------------------------------------------
subawxlax:.macro
#ifdef halten_sub
halt
#endif
move.l (a0)+,a1
mvs.w (a1),d0
move.l \2,a1
suba.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w d16(pc),ax
//--------------------------------------------------------------------
subawd16pcax:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,a1
adda.l a0,a1
mvs.w (a1),d0
move.l \2,a1
suba.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w d8(pc,dy),ax
//--------------------------------------------------------------------
subawd8pcax:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w #im,ax
//--------------------------------------------------------------------
subawim:.macro
#ifdef halten_sub
halt
#endif
mvs.w \1,d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.l d8(ay,dy),ax
//--------------------------------------------------------------------
subald8a:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.l d8(pc,dy),ax
//--------------------------------------------------------------------
subakd8pcax:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//*****************************************************************************************
// subx
//*****************************************************************************************
//--------------------------------------------------------------------
// // subx dy,dx
//--------------------------------------------------------------------
subdx:.macro
#ifdef halten_sub
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
mvs.\3 \2,d0
mvs.\3 \1,d1
subx.l d0,d1
set_cc0
move.\3 d1,\1
ii_end
.endm;
//--------------------------------------------------------------------
// // subx -(ay),-(ax)
//--------------------------------------------------------------------
subdax:.macro
#ifdef halten_sub
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
move.l \1,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d0
.endif
move.l \2,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d1
.endif
subx.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------

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/*******************************************************/
// allgemeine macros
/*******************************************************/
.text
wait_pll: .macro
wait1_pll\@:
tst.w (a1)
bmi wait1_pll\@
rts
.endm

256
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// movem
_ii_movem_lset: .macro
// movem rx,xxx.L
ii_lset 0x48f9
// movem rx,-(ax)
// movem (ax)+,rx
ii_lset 0x4cd8
ii_lset 0x4cd9
ii_lset 0x4cda
ii_lset 0x4cdb
ii_lset 0x4cdc
ii_lset 0x4cdd
ii_lset 0x4cde
ii_lset 0x4cdf
// movem xxx.L,rx
ii_lset 0x4cf9
.endm
//***********************************************************************************/
_ii_movem_func: .macro
//-------------------------------------------------------------------
// movem.l
//--------------------------------------------------------------------
// movem.l (ax)+,reg
//--------------------------------------------------------------------
//-------------------------------------------------------------------------------
ii_0x4cd8: // movem.l (a0)+,reglist
mvm_macro 0x4cd0,0x41e8,2
ii_0x4cd9: // movem.l (a1)+,reglist
mvm_macro 0x4cd1,0x43e9,2
ii_0x4cda: // movem.l (a2)+,reglist
mvm_macro 0x4cd2,0x45ea,2
ii_0x4cdb: // movem.l (a3)+,reglist
mvm_macro 0x4cd3,0x47eb,2
ii_0x4cdc: // movem.l (a4)+,reglist
mvm_macro 0x4cd4,0x49ec,2
ii_0x4cdd: // movem.l (a5)+,reglist
mvm_macro 0x4cd5,0x4bed,2
ii_0x4cde: // movem.l (a6)+,reglist
mvm_macro 0x4cd6,0x4dee,2
ii_0x4cdf: // movem.l (a7)+,reglist
mvm_macro 0x4cd7,0x4fef,2
//----------------------------------------------------------------------------
ii_0x48f9: // movem.l reg,xxx.L
move.w (a0)+,d0
move.l (a0)+,a1
movemrm_macro
ii_end
//---------------------------------------------------------------------------------------------
ii_0x4cf9: // movem.l xxx.L,reg
move.w (a0)+,d0
move.l (a0)+,a1
movemmr_macro
ii_end
.endm
//==============================================================
mvm_macro:.macro
halt
lea az_reg_table,a1
mvz.b (a0),d1
mvz.b 0(a1,d1)+,d0
mvz.b 1(a0),d1
mvz.b 0(a1,d1)+,d1
add.l d0,d1
lea ___RAMBAR1,a1
move.l a1,pc_off(a7)
move.l a1,d0
addq.l #1,d0
movec d0,RAMBAR1
move.w #\1,(a1)+ // movem.x (ax),reg_list
move.w (a0)+,(a1)+ // register list
move.w #\2,(a1)+ // lea 0(ax),ax
lsl.l #\3,d1 // * anzahl byts pro wert
move.w d1,(a1)+ // offset von lea
move.w #0x4ef9,(a1)+ // jmp.l
move.l a0,(a1) // r<>cksprungadresse
move.l #___RAMBAR1 + 0x81,d0 // instruction
movec d0,RAMBAR1
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm
.long 0
az_reg_table:
.byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0
.byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0
//---------------------------------------------------------------------------------
movemrm_macro:.macro // in d0 register liste, in a1 zieladresse
halt
tst.b d0 // datenregister zu verschieben?
bne mrm_dx // ja->
lsr.l #8,d0 // sonst zu addressregister
jmp mmrm_nd7 // ->
mrm_dx:
lsr.l #1,d0
bcc mmrm_nd0
move.l d0_off(a7),(a1)+
mmrm_nd0:
lsr.l #1,d0
bcc mmrm_nd1
move.l d1_off(a7),(a1)+
mmrm_nd1:
lsr.l #1,d0
bcc mmrm_nd2
move.l d2,(a1)+
mmrm_nd2:
lsr.l #1,d0
bcc mmrm_nd3
move.l d3,(a1)+
mmrm_nd3:
lsr.l #1,d0
bcc mmrm_nd4
move.l d4,(a1)+
mmrm_nd4:
lsr.l #1,d0
bcc mmrm_nd5
move.l d5,(a1)+
mmrm_nd5:
lsr.l #1,d0
bcc mmrm_nd6
move.l d6,(a1)+
mmrm_nd6:
lsr.l #1,d0
bcc mmrm_nd7
move.l d7,(a1)+
mmrm_nd7:
tst.b d0 // addressregister zu verschieben?
beq mmrm_na7
lsr.l #1,d0
bcc mmrm_na0
move.l a0_off(a7),(a1)+
mmrm_na0:
lsr.l #1,d0
bcc mmrm_na1
move.l a1_off(a7),(a1)+
mmrm_na1:
lsr.l #1,d0
bcc mmrm_na2
move.l a2,(a1)+
mmrm_na2:
lsr.l #1,d0
bcc mmrm_na3
move.l a3,(a1)+
mmrm_na3:
lsr.l #1,d0
bcc mmrm_na4
move.l a4,(a1)+
mmrm_na4:
lsr.l #1,d0
bcc mmrm_na5
move.l a5,(a1)+
mmrm_na5:
lsr.l #1,d0
bcc mmrm_na6
move.l a6,(a1)+
mmrm_na6:
lsr.l #1,d0
bcc mmrm_na7
move.l a0,d1 // sichern
move.l usp,a0 // ist ja usp
move.l a0,(a1)+ // nach a0
move.l d1,a0 // pc zur<75>ck
mmrm_na7:
.endm
//---------------------------------------------------------------------------------------------
movemmr_macro:.macro // in d0 register liste, in a1 source adr
halt
tst.b d0 // datenregister zu verschieben?
bne mmr_dx // ja->
lsr.l #8,d0 // sonst zu addressregister
bra mmmr_nd7 // ->
mmr_dx:
lsr.l #1,d0
bcc mmmr_nd0
move.l (a1)+,d0_off(a7)
mmmr_nd0:
lsr.l #1,d0
bcc mmmr_nd1
move.l (a1)+,d1_off(a7)
mmmr_nd1:
lsr.l #1,d0
bcc mmmr_nd2
move.l (a1)+,d2
mmmr_nd2:
lsr.l #1,d0
bcc mmmr_nd3
move.l (a1)+,d3
mmmr_nd3:
lsr.l #1,d0
bcc mmmr_nd4
move.l (a1)+,d4
mmmr_nd4:
lsr.l #1,d0
bcc mmmr_nd5
move.l (a1)+,d5
mmmr_nd5:
lsr.l #1,d0
bcc mmmr_nd6
move.l (a1)+,d6
mmmr_nd6:
lsr.l #1,d0
bcc mmmr_nd7
move.l (a1)+,d7
mmmr_nd7:
tst.b d0 // addressregister zu verschieben?
beq mmmr_na7 // nein->
lsr.l #1,d0
bcc mmmr_na0
move.l (a1)+,a0_off(a7)
mmmr_na0:
lsr.l #1,d0
bcc mmmr_na1
move.l (a1)+,a1_off(a7)
mmmr_na1:
lsr.l #1,d0
bcc mmmr_na2
move.l (a1)+,a2
mmmr_na2:
lsr.l #1,d0
bcc mmmr_na3
move.l (a1)+,a3
mmmr_na3:
lsr.l #1,d0
bcc mmmr_na4
move.l (a1)+,a4
mmmr_na4:
lsr.l #1,d0
bcc mmmr_na5
move.l (a1)+,a5
mmmr_na5:
lsr.l #1,d0
bcc mmmr_na6
move.l (a1)+,a6
mmmr_na6:
lsr.l #1,d0
bcc mmmr_na7
move.l a0,d1 // sichern
move.l (a1)+,a0 // nach a0
move.l a0,usp // war ja usp
move.l d1,a0 // pc zur<75>ck
mmmr_na7:
.endm

47
headers/startcf.h Normal file
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/******************************************************************************
FILE : startcf.h
PURPOSE : startup code for ColdFire
LANGUAGE: C
Notes:
1) Default entry point is _startup.
. disable interrupts
. the SP is set to __SP_AFTER_RESET
. SP must be initialized to valid memory
in case the memory it points to is not valid using MEMORY_INIT macro
2) __initialize_hardware is called. Here you can initialize memory and some peripherics
at this point global variables are not initialized yet
3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform
needed initialisations for the language (clear memory, data rom copy).
4) void __initialize_system(void); is called
to allow additional hardware initialization (UART, GPIOs, etc...)
5) Jump to main
*/
/********************************************************************************/
#ifdef ii_on
#define halten
#define halten_dbcc
#define halten_and
#define halten_add
#define halten_sub
#define halten_or
#define halten_op
#define halten_opc
#define halten_movem
#define halten_lea
#define halten_shift
#define halten_move
#define halten_exg
#define halten_movep
#define halten_ewf
#endif
#define DIP_SWITCH (*(vuint8 *)(&__MBAR[0xA2C]))
#define DIP_SWITCHa ___MBAR + 0xA2C
#define sca_page_ID 6

87
headers/sysinit.h Normal file
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/*
* File: sysinit.h
* Purpose: COLDARI Power-on Reset configuration
*
* Notes:
*
*/
#ifndef __SYSINIT_H__
#define __SYSINIT_H__
#ifdef __cplusplus
extern "C" {
#endif
#if ENABLE_UART_SUPPORT==1
/*
* System Bus Clock Info
*/
// 5475EVB has 133Mhz system clock
#define SYSTEM_CLOCK_KHZ 133000 /* system bus frequency in kHz */
/***
* Serial Port Info
* The baud rate to be : 19200
* Data bits : 8
* Parity : None
* Stop Bits : 1
* Flow Control : None
*/
#define TERMINAL_PORT (0) /* PSC channel used as terminal */
#define TERMINAL_BAUD kBaud19200 /* 115200 */
#undef HARDWARE_FLOW_CONTROL /* Flow control ON or OFF */
#endif
/***
* Board Memory map definitions from linker command files:
* __SDRAM,__SDRAM_SIZE, __FLASH, __FLASH_SIZE linker
* symbols must be defined in the linker command file.
*/
extern __declspec(system) uint8 __BOOT_FLASH[];
extern __declspec(system) uint8 __BOOT_FLASH_SIZE[];
extern __declspec(system) uint8 __SDRAM[];
extern __declspec(system) uint8 __SDRAM_SIZE[];
#define BOOT_FLASH_ADDRESS (uint32)__BOOT_FLASH
#define BOOT_FLASH_SIZE (uint32)__BOOT_FLASH_SIZE
#define SDRAM_ADDRESS (uint32)__SDRAM
#define SDRAM_SIZE (uint32)__SDRAM_SIZE
/********************************************************************/
/* __initialize_hardware Startup code routine
*
* __initialize_hardware is called by the startup code right after reset,
* with interrupt disabled and SP pre-set to a valid memory area.
* Here you should initialize memory and some peripherics;
* at this point global variables are not initialized yet.
* The startup code will initialize SP on return of this function.
*/
void __initialize_hardware(void);
/********************************************************************/
/* __initialize_system Startup code routine
*
* __initialize_system is called by the startup code when all languages
* specific initialization are done to allow additional hardware setup.
*/
void __initialize_system(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSINIT_H__ */